mirror of
https://github.com/pj64team/Project64-Legacy.git
synced 2026-04-02 20:55:40 +00:00
3dfc995d02
This makes it so the Release External build can now be used to debug the roms without having to also provide a Release build. Next commit will add these options via the graphical interface and clean up some options that have become deprecated
476 lines
13 KiB
C
476 lines
13 KiB
C
/*
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* Project 64 - A Nintendo 64 emulator.
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*
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* (c) Copyright 2001 zilmar (zilmar@emulation64.com) and
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* Jabo (jabo@emulation64.com).
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*
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* pj64 homepage: www.pj64.net
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*
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* Permission to use, copy, modify and distribute Project64 in both binary and
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* source form, for non-commercial purposes, is hereby granted without fee,
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* providing that this license information and copyright notice appear with
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* all copies and any derived work.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event shall the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Project64 is freeware for PERSONAL USE only. Commercial users should
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* seek permission of the copyright holders first. Commercial use includes
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* charging money for Project64 or software derived from Project64.
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*
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* The copyright holders request that bug fixes and improvements to the code
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* should be forwarded to them so if they want them.
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*
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*/
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#include <Windows.h>
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#include <stdio.h>
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#include "main.h"
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#include "debugger.h"
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#include "CPU.h"
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int DMAUsed;
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void FirstDMA (void) {
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switch (GetCicChipID(ROM)) {
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case 1: *(DWORD *)&N64MEM[0x318] = RdramSize; break;
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case 2: *(DWORD *)&N64MEM[0x318] = RdramSize; break;
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case 3: *(DWORD *)&N64MEM[0x318] = RdramSize; break;
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case 5: *(DWORD *)&N64MEM[0x3F0] = RdramSize; break;
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case 6: *(DWORD *)&N64MEM[0x318] = RdramSize; break;
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case 9: *(DWORD *)&N64MEM[0x318] = RdramSize; break;
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case 10: *(DWORD *)&N64MEM[0x318] = RdramSize; break;
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default:
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*(DWORD *)&N64MEM[0x318] = RdramSize;
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if (ShowDebugMessages)
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DisplayError("Unhandled CicChip(%d) in first DMA",GetCicChipID(ROM));
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}
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}
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void PI_DMA_READ (void) {
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// PI_STATUS_REG |= PI_STATUS_DMA_BUSY;
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PI_RD_LEN_REG = (PI_RD_LEN_REG & 1) ? PI_RD_LEN_REG : PI_RD_LEN_REG + 1; // Fix for Ai Shogi 3
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PI_CART_ADDR_REG &= ~1; // Taz Express fix
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PI_DRAM_ADDR_REG &= ~7; // Tax Express fix
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if ( PI_DRAM_ADDR_REG + PI_RD_LEN_REG + 1 > RdramSize) {
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if (ShowDebugMessages)
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DisplayError("PI_DMA_READ not in Memory");
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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return;
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}
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// Trying to fix saves for Dezaemon 3D (J)
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// There is likely a better way to do this
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if ((PI_CART_ADDR_REG >= 0x08000000 && PI_CART_ADDR_REG <= 0x08010000) ||
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(PI_CART_ADDR_REG >= 0x08040000 && PI_CART_ADDR_REG <= 0x08050000) ||
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(PI_CART_ADDR_REG >= 0x08080000 && PI_CART_ADDR_REG <= 0x08090000))
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{
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switch (SaveUsing) {
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case Auto:
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SaveUsing = Sram;
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case Sram:
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DmaToSram(
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N64MEM+PI_DRAM_ADDR_REG,
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PI_CART_ADDR_REG - 0x08000000,
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PI_RD_LEN_REG + 1
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);
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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break;
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case FlashRam:
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DmaToFlashram(
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N64MEM+PI_DRAM_ADDR_REG,
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PI_CART_ADDR_REG - 0x08000000,
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PI_WR_LEN_REG + 1
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);
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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break;
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}
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return;
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}
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if (SaveUsing == FlashRam) {
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if (ShowDebugMessages)
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DisplayError("**** FLashRam DMA Read address %X *****",PI_CART_ADDR_REG);
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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return;
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}
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if (ShowDebugMessages)
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DisplayError("PI_DMA_READ where are you dmaing to ?");
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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return;
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}
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void PI_DMA_WRITE (void) {
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DWORD i;
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PI_WR_LEN_REG = (PI_WR_LEN_REG & 1) ? PI_WR_LEN_REG : PI_WR_LEN_REG + 1; // Fix for Ai Shogi 3
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PI_CART_ADDR_REG &= ~1; // Taz Express fix
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PI_DRAM_ADDR_REG &= ~7; // Taz Express fix
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PI_STATUS_REG |= PI_STATUS_DMA_BUSY;
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if ( PI_DRAM_ADDR_REG + PI_WR_LEN_REG + 1 > RdramSize) {
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if (ShowDebugMessages)
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DisplayError("PI_DMA_WRITE not in Memory");
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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return;
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}
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// Trying to fix saves for Dezaemon 3D (J)
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// There is likely a better way to do this
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if ((PI_CART_ADDR_REG >= 0x08000000 && PI_CART_ADDR_REG <= 0x08010000) ||
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(PI_CART_ADDR_REG >= 0x08040000 && PI_CART_ADDR_REG <= 0x08050000) ||
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(PI_CART_ADDR_REG >= 0x08080000 && PI_CART_ADDR_REG <= 0x08090000))
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{
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switch (SaveUsing) {
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case Auto:
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SaveUsing = Sram;
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case Sram:
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DmaFromSram(
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N64MEM+PI_DRAM_ADDR_REG,
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PI_CART_ADDR_REG - 0x08000000,
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PI_WR_LEN_REG + 1
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);
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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break;
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case FlashRam:
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DmaFromFlashram(
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N64MEM+PI_DRAM_ADDR_REG,
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PI_CART_ADDR_REG - 0x08000000,
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PI_WR_LEN_REG + 1
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);
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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break;
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}
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return;
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}
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if ( PI_CART_ADDR_REG >= 0x06000000 && PI_CART_ADDR_REG < 0x08000000) {
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#ifdef ROM_IN_MAPSPACE
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if (WrittenToRom) {
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DWORD OldProtect;
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VirtualProtect(ROM,RomFileSize,PAGE_READONLY, &OldProtect);
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}
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#endif
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PI_CART_ADDR_REG -= 0x06000000;
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if (PI_CART_ADDR_REG + PI_WR_LEN_REG + 1 < RomFileSize) {
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for (i = 0; i < PI_WR_LEN_REG + 1; i ++) {
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*(N64MEM+((PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM+((PI_CART_ADDR_REG + i) ^ 3));
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}
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} else if (RomFileSize > PI_CART_ADDR_REG) {
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DWORD Len;
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Len = RomFileSize - PI_CART_ADDR_REG;
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for (i = 0; i < Len; i ++) {
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*(N64MEM+((PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM+((PI_CART_ADDR_REG + i) ^ 3));
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}
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for (i = Len; i < PI_WR_LEN_REG + 1 - Len; i ++) {
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*(N64MEM+((PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
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}
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}
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PI_CART_ADDR_REG += 0x06000000;
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if (!DMAUsed) {
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DMAUsed = TRUE;
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FirstDMA();
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}
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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//ChangeTimer(PiTimer,(int)(PI_WR_LEN_REG * 8.9) + 50);
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//ChangeTimer(PiTimer,(int)(PI_WR_LEN_REG * 8.9));
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CheckTimer();
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return;
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}
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if ( PI_CART_ADDR_REG >= 0x10000000 && PI_CART_ADDR_REG <= 0x1FBFFFFF) {
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#ifdef ROM_IN_MAPSPACE
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if (WrittenToRom) {
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DWORD OldProtect;
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VirtualProtect(ROM,RomFileSize,PAGE_READONLY, &OldProtect);
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}
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#endif
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PI_CART_ADDR_REG -= 0x10000000;
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if (PI_CART_ADDR_REG + PI_WR_LEN_REG + 1 < RomFileSize) {
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for (i = 0; i < PI_WR_LEN_REG + 1; i ++) {
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*(N64MEM+((PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM+((PI_CART_ADDR_REG + i) ^ 3));
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}
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} else if (RomFileSize > PI_CART_ADDR_REG) {
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DWORD Len;
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Len = RomFileSize - PI_CART_ADDR_REG;
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for (i = 0; i < Len; i ++) {
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*(N64MEM+((PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM+((PI_CART_ADDR_REG + i) ^ 3));
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}
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for (i = Len; i < PI_WR_LEN_REG + 1 - Len; i ++) {
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*(N64MEM+((PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
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}
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}
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PI_CART_ADDR_REG += 0x10000000;
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if (!DMAUsed) {
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DMAUsed = TRUE;
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FirstDMA();
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}
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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//ChangeTimer(PiTimer,(int)(PI_WR_LEN_REG * 8.9) + 50);
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//ChangeTimer(PiTimer,(int)(PI_WR_LEN_REG * 8.9));
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CheckTimer();
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return;
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}
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if (HaveDebugger && ShowUnhandledMemory) { DisplayError("PI_DMA_WRITE not in ROM"); }
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PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
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MI_INTR_REG |= MI_INTR_PI;
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CheckInterrupts();
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}
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void SI_DMA_READ (void) {
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BYTE * PifRamPos = &PIF_Ram[0];
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if ((int)SI_DRAM_ADDR_REG > (int)RdramSize) {
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if (ShowDebugMessages)
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DisplayError("SI DMA\nSI_DRAM_ADDR_REG not in RDRam space");
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return;
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}
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PifRamRead();
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SI_DRAM_ADDR_REG &= 0xFFFFFFF8;
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if ((int)SI_DRAM_ADDR_REG < 0) {
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int count, RdramPos;
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RdramPos = (int)SI_DRAM_ADDR_REG;
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for (count = 0; count < 0x40; count++, RdramPos++) {
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if (RdramPos < 0) { continue; }
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N64MEM[RdramPos ^3] = PIF_Ram[count];
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}
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} else {
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_asm {
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mov edi, dword ptr [RegSI]
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mov edi, dword ptr [edi]
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add edi, N64MEM
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mov ecx, PifRamPos
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mov edx, 0
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memcpyloop:
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mov eax, dword ptr [ecx + edx]
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bswap eax
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mov dword ptr [edi + edx],eax
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mov eax, dword ptr [ecx + edx + 4]
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bswap eax
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mov dword ptr [edi + edx + 4],eax
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mov eax, dword ptr [ecx + edx + 8]
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bswap eax
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mov dword ptr [edi + edx + 8],eax
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mov eax, dword ptr [ecx + edx + 12]
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bswap eax
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mov dword ptr [edi + edx + 12],eax
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add edx, 16
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cmp edx, 64
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jb memcpyloop
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}
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}
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if (HaveDebugger && LogOptions.LogPRDMAMemStores) {
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int count;
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char HexData[100], AsciiData[100], Addon[20];
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LogMessage("\tData DMAed to RDRAM:");
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LogMessage("\t--------------------");
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for (count = 0; count < 16; count ++ ) {
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if ((count % 4) == 0) {
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sprintf(HexData,"\0");
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sprintf(AsciiData,"\0");
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}
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sprintf(Addon,"%02X %02X %02X %02X",
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PIF_Ram[(count << 2) + 0], PIF_Ram[(count << 2) + 1],
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PIF_Ram[(count << 2) + 2], PIF_Ram[(count << 2) + 3] );
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strcat(HexData,Addon);
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if (((count + 1) % 4) != 0) {
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sprintf(Addon,"-");
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strcat(HexData,Addon);
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}
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sprintf(Addon,"%c%c%c%c",
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PIF_Ram[(count << 2) + 0], PIF_Ram[(count << 2) + 1],
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PIF_Ram[(count << 2) + 2], PIF_Ram[(count << 2) + 3] );
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strcat(AsciiData,Addon);
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if (((count + 1) % 4) == 0) {
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LogMessage("\t%s %s",HexData, AsciiData);
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}
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}
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LogMessage("");
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}
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if (DelaySI) {
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ChangeTimer(SiTimer,0x900);
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} else {
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MI_INTR_REG |= MI_INTR_SI;
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SI_STATUS_REG |= SI_STATUS_INTERRUPT;
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CheckInterrupts();
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}
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}
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void SI_DMA_WRITE (void) {
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BYTE * PifRamPos = &PIF_Ram[0];
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if ((int)SI_DRAM_ADDR_REG > (int)RdramSize) {
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if (ShowDebugMessages)
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DisplayError("SI DMA\nSI_DRAM_ADDR_REG not in RDRam space");
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return;
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}
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SI_DRAM_ADDR_REG &= 0xFFFFFFF8;
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if ((int)SI_DRAM_ADDR_REG < 0) {
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int count, RdramPos;
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RdramPos = (int)SI_DRAM_ADDR_REG;
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for (count = 0; count < 0x40; count++, RdramPos++) {
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if (RdramPos < 0) { PIF_Ram[count] = 0; continue; }
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PIF_Ram[count] = N64MEM[RdramPos ^3];
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}
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} else {
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_asm {
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mov ecx, dword ptr [RegSI]
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mov ecx, dword ptr [ecx]
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add ecx, N64MEM
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mov edi, PifRamPos
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mov edx, 0
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memcpyloop:
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mov eax, dword ptr [ecx + edx]
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bswap eax
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mov dword ptr [edi + edx],eax
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mov eax, dword ptr [ecx + edx + 4]
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bswap eax
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mov dword ptr [edi + edx + 4],eax
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mov eax, dword ptr [ecx + edx + 8]
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bswap eax
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mov dword ptr [edi + edx + 8],eax
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mov eax, dword ptr [ecx + edx + 12]
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bswap eax
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mov dword ptr [edi + edx + 12],eax
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add edx, 16
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cmp edx, 64
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jb memcpyloop
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}
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}
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if (HaveDebugger && LogOptions.LogPRDMAMemLoads) {
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int count;
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char HexData[100], AsciiData[100], Addon[20];
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LogMessage("");
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LogMessage("\tData DMAed to the Pif Ram:");
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LogMessage("\t--------------------------");
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for (count = 0; count < 16; count ++ ) {
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if ((count % 4) == 0) {
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sprintf(HexData,"\0");
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sprintf(AsciiData,"\0");
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}
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sprintf(Addon,"%02X %02X %02X %02X",
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PIF_Ram[(count << 2) + 0], PIF_Ram[(count << 2) + 1],
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PIF_Ram[(count << 2) + 2], PIF_Ram[(count << 2) + 3] );
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strcat(HexData,Addon);
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if (((count + 1) % 4) != 0) {
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sprintf(Addon,"-");
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strcat(HexData,Addon);
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}
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sprintf(Addon,"%c%c%c%c",
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PIF_Ram[(count << 2) + 0], PIF_Ram[(count << 2) + 1],
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PIF_Ram[(count << 2) + 2], PIF_Ram[(count << 2) + 3] );
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strcat(AsciiData,Addon);
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if (((count + 1) % 4) == 0) {
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LogMessage("\t%s %s",HexData, AsciiData);
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}
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}
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LogMessage("");
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}
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PifRamWrite();
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if (DelaySI) {
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ChangeTimer(SiTimer,0x900);
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} else {
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MI_INTR_REG |= MI_INTR_SI;
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SI_STATUS_REG |= SI_STATUS_INTERRUPT;
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CheckInterrupts();
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}
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}
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void SP_DMA_READ (void) {
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SP_DRAM_ADDR_REG &= 0x1FFFFFFF;
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if (SP_DRAM_ADDR_REG > RdramSize) {
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if (ShowDebugMessages)
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DisplayError("SP DMA\nSP_DRAM_ADDR_REG not in RDRam space");
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SP_DMA_BUSY_REG = 0;
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SP_STATUS_REG &= ~SP_STATUS_DMA_BUSY;
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return;
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}
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if (SP_RD_LEN_REG + 1 + (SP_MEM_ADDR_REG & 0xFFF) > 0x1000) {
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if (ShowDebugMessages)
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DisplayError("SP DMA\ncould not fit copy in memory segement");
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SP_DMA_BUSY_REG = 0;
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SP_STATUS_REG &= ~SP_STATUS_DMA_BUSY;
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return;
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}
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if ((SP_MEM_ADDR_REG & 3) != 0 || (SP_DRAM_ADDR_REG & 3) != 0 || ((SP_RD_LEN_REG + 1) & 3) != 0) {
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DisplayErrorFatal("Nonstandard DMA Transfer.\nStopping Emulation.");
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ExitThread(0);
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}
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/*
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if ((SP_MEM_ADDR_REG & 3) != 0) { _asm int 3 }
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if ((SP_DRAM_ADDR_REG & 3) != 0) { _asm int 3 }
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if (((SP_RD_LEN_REG + 1) & 3) != 0) { _asm int 3 }
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*/
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memcpy( DMEM + (SP_MEM_ADDR_REG & 0x1FFF), N64MEM + SP_DRAM_ADDR_REG,
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SP_RD_LEN_REG + 1 );
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SP_DMA_BUSY_REG = 0;
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SP_STATUS_REG &= ~SP_STATUS_DMA_BUSY;
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}
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void SP_DMA_WRITE (void) {
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if (SP_DRAM_ADDR_REG > RdramSize) {
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if (ShowDebugMessages)
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DisplayError("SP DMA WRITE\nSP_DRAM_ADDR_REG not in RDRam space");
|
|
return;
|
|
}
|
|
|
|
if (SP_WR_LEN_REG + 1 + (SP_MEM_ADDR_REG & 0xFFF) > 0x1000) {
|
|
if (ShowDebugMessages)
|
|
DisplayError("SP DMA WRITE\ncould not fit copy in memory segement");
|
|
return;
|
|
}
|
|
|
|
if ((SP_MEM_ADDR_REG & 3) != 0) { _asm int 3 }
|
|
if ((SP_DRAM_ADDR_REG & 3) != 0) { _asm int 3 }
|
|
if (((SP_WR_LEN_REG + 1) & 3) != 0) { _asm int 3 }
|
|
|
|
memcpy( N64MEM + SP_DRAM_ADDR_REG, DMEM + (SP_MEM_ADDR_REG & 0x1FFF),
|
|
SP_WR_LEN_REG + 1);
|
|
|
|
SP_DMA_BUSY_REG = 0;
|
|
SP_STATUS_REG &= ~SP_STATUS_DMA_BUSY;
|
|
}
|