diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h new file mode 100644 index 000000000000..33c615c35ba2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H +#define _DT_BINDINGS_CLK_MSM_GCC_660_H + +/* Hardware/Dummy/Voter clocks */ +#define GCC_XO 0 +#define GCC_GPLL0_EARLY_DIV 1 +#define GCC_GPLL1_EARLY_DIV 2 +#define GCC_CE1_AHB_M_CLK 3 +#define GCC_CE1_AXI_M_CLK 4 + +/* RCGs and Branches */ +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 10 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 11 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 12 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 13 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 14 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 17 +#define BLSP1_UART1_APPS_CLK_SRC 18 +#define BLSP1_UART2_APPS_CLK_SRC 19 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 20 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 21 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 22 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 23 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 24 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 25 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 26 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 27 +#define BLSP2_UART1_APPS_CLK_SRC 28 +#define BLSP2_UART2_APPS_CLK_SRC 29 +#define GCC_AGGRE2_UFS_AXI_CLK 30 +#define GCC_AGGRE2_USB3_AXI_CLK 31 +#define GCC_BIMC_GFX_CLK 32 +#define GCC_BIMC_HMSS_AXI_CLK 33 +#define GCC_BIMC_MSS_Q6_AXI_CLK 34 +#define GCC_BLSP1_AHB_CLK 35 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 +#define GCC_BLSP1_UART1_APPS_CLK 44 +#define GCC_BLSP1_UART2_APPS_CLK 45 +#define GCC_BLSP2_AHB_CLK 46 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 47 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 48 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 49 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 50 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 51 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 52 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 53 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 54 +#define GCC_BLSP2_UART1_APPS_CLK 55 +#define GCC_BLSP2_UART2_APPS_CLK 56 +#define GCC_BOOT_ROM_AHB_CLK 57 +#define GCC_CFG_NOC_USB2_AXI_CLK 58 +#define GCC_CFG_NOC_USB3_AXI_CLK 59 +#define GCC_DCC_AHB_CLK 60 +#define GCC_GP1_CLK 61 +#define GCC_GP2_CLK 62 +#define GCC_GP3_CLK 63 +#define GCC_GPU_BIMC_GFX_CLK 64 +#define GCC_GPU_CFG_AHB_CLK 66 +#define GCC_GPU_GPLL0_CLK 67 +#define GCC_GPU_GPLL0_DIV_CLK 68 +#define GCC_HMSS_DVM_BUS_CLK 71 +#define GCC_HMSS_RBCPR_CLK 72 +#define GCC_MMSS_GPLL0_CLK 73 +#define GCC_MMSS_GPLL0_DIV_CLK 74 +#define GCC_MMSS_NOC_CFG_AHB_CLK 75 +#define GCC_MMSS_SYS_NOC_AXI_CLK 76 +#define GCC_MSS_CFG_AHB_CLK 77 +#define GCC_MSS_GPLL0_DIV_CLK 78 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 79 +#define GCC_MSS_Q6_BIMC_AXI_CLK 80 +#define GCC_MSS_SNOC_AXI_CLK 81 +#define GCC_PDM2_CLK 82 +#define GCC_PDM_AHB_CLK 83 +#define GCC_PRNG_AHB_CLK 84 +#define GCC_QSPI_AHB_CLK 85 +#define GCC_QSPI_SER_CLK 86 +#define GCC_RX0_USB2_CLKREF_CLK 87 +#define GCC_RX1_USB2_CLKREF_CLK 88 +#define GCC_SDCC1_AHB_CLK 90 +#define GCC_SDCC1_APPS_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_UFS_AHB_CLK 95 +#define GCC_UFS_AXI_CLK 96 +#define GCC_UFS_CLKREF_CLK 97 +#define GCC_UFS_ICE_CORE_CLK 98 +#define GCC_UFS_PHY_AUX_CLK 99 +#define GCC_UFS_RX_SYMBOL_0_CLK 100 +#define GCC_UFS_RX_SYMBOL_1_CLK 101 +#define GCC_UFS_TX_SYMBOL_0_CLK 102 +#define GCC_UFS_UNIPRO_CORE_CLK 103 +#define GCC_USB20_MASTER_CLK 104 +#define GCC_USB20_MOCK_UTMI_CLK 105 +#define GCC_USB20_SLEEP_CLK 106 +#define GCC_USB30_MASTER_CLK 107 +#define GCC_USB30_MOCK_UTMI_CLK 108 +#define GCC_USB30_SLEEP_CLK 109 +#define GCC_USB3_CLKREF_CLK 110 +#define GCC_USB3_PHY_AUX_CLK 111 +#define GCC_USB3_PHY_PIPE_CLK 112 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 113 +#define GP1_CLK_SRC 114 +#define GP2_CLK_SRC 115 +#define GP3_CLK_SRC 116 +#define GPLL0 117 +#define GPLL0_OUT_AUX 118 +#define GPLL0_OUT_AUX2 119 +#define GPLL0_OUT_EARLY 120 +#define GPLL0_OUT_MAIN 121 +#define GPLL0_AO 122 +#define GPLL1 123 +#define GPLL1_OUT_AUX 124 +#define GPLL1_OUT_AUX2 125 +#define GPLL1_OUT_EARLY 126 +#define GPLL1_OUT_MAIN 127 +#define GPLL1_OUT_TEST 128 +#define GPLL2 129 +#define GPLL2_OUT_AUX 130 +#define GPLL2_OUT_AUX2 131 +#define GPLL2_OUT_EARLY 132 +#define GPLL2_OUT_MAIN 133 +#define GPLL2_OUT_TEST 134 +#define GPLL3 135 +#define GPLL3_OUT_AUX 136 +#define GPLL3_OUT_AUX2 137 +#define GPLL3_OUT_EARLY 138 +#define GPLL3_OUT_MAIN 139 +#define GPLL3_OUT_TEST 140 +#define GPLL4 141 +#define GPLL4_OUT_AUX 142 +#define GPLL4_OUT_AUX2 143 +#define GPLL4_OUT_EARLY 144 +#define GPLL4_OUT_MAIN 145 +#define GPLL4_OUT_TEST 146 +#define GPLL5 147 +#define GPLL5_OUT_AUX 148 +#define GPLL5_OUT_AUX2 149 +#define GPLL5_OUT_EARLY 150 +#define GPLL5_OUT_MAIN 151 +#define GPLL5_OUT_TEST 152 +#define GPLL6 153 +#define GPLL6_OUT_AUX 154 +#define GPLL6_OUT_AUX2 155 +#define GPLL6_OUT_EARLY 156 +#define GPLL6_OUT_MAIN 157 +#define GPLL6_OUT_TEST 158 +#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 159 +#define HMSS_GPLL0_CLK_SRC 161 +#define HMSS_GPLL4_CLK_SRC 162 +#define HMSS_RBCPR_CLK_SRC 163 +#define PDM2_CLK_SRC 164 +#define QSPI_SER_CLK_SRC 165 +#define SDCC1_APPS_CLK_SRC 166 +#define SDCC1_ICE_CORE_CLK_SRC 167 +#define SDCC2_APPS_CLK_SRC 168 +#define UFS_AXI_CLK_SRC 169 +#define UFS_ICE_CORE_CLK_SRC 170 +#define UFS_PHY_AUX_CLK_SRC 171 +#define UFS_UNIPRO_CORE_CLK_SRC 172 +#define USB20_MASTER_CLK_SRC 173 +#define USB20_MOCK_UTMI_CLK_SRC 174 +#define USB30_MASTER_CLK_SRC 175 +#define USB30_MOCK_UTMI_CLK_SRC 176 +#define USB3_PHY_AUX_CLK_SRC 177 +#define GPLL0_OUT_MSSCC 178 +#define GCC_UFS_AXI_HW_CTL_CLK 179 +#define GCC_UFS_ICE_CORE_HW_CTL_CLK 180 +#define GCC_UFS_PHY_AUX_HW_CTL_CLK 181 +#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 182 +#define HLOS1_VOTE_TURING_ADSP_SMMU_CLK 183 +#define HLOS2_VOTE_TURING_ADSP_SMMU_CLK 184 + +/* Block resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_BCR 2 +#define GCC_USB3_DP_PHY_BCR 3 +#define GCC_USB3_PHY_BCR 4 +#define GCC_USB3PHY_PHY_BCR 5 +#define GCC_USB_20_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpu-sdm660.h b/include/dt-bindings/clock/qcom,gpu-sdm660.h new file mode 100644 index 000000000000..d3d38acfc6b6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpu-sdm660.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GPU_660_H +#define _DT_BINDINGS_CLK_MSM_GPU_660_H + +#define GPU_PLL0_PLL 0 +#define GPU_PLL0_PLL_OUT_AUX 1 +#define GPU_PLL0_PLL_OUT_AUX2 2 +#define GPU_PLL0_PLL_OUT_EARLY 3 +#define GPU_PLL0_PLL_OUT_MAIN 4 +#define GPU_PLL0_PLL_OUT_TEST 5 +#define GPU_PLL1_PLL 6 +#define GPU_PLL1_PLL_OUT_AUX 7 +#define GPU_PLL1_PLL_OUT_AUX2 8 +#define GPU_PLL1_PLL_OUT_EARLY 9 +#define GPU_PLL1_PLL_OUT_MAIN 10 +#define GPU_PLL1_PLL_OUT_TEST 11 +#define GFX3D_CLK_SRC 12 +#define GPUCC_GFX3D_CLK 13 +#define GPUCC_RBBMTIMER_CLK 14 +#define RBBMTIMER_CLK_SRC 15 +#define GPUCC_CXO_CLK 16 + +/* RBCPR GPUCC clocks */ +#define RBCPR_CLK_SRC 0 +#define GPUCC_RBCPR_CLK 1 + +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#define GPUCC_GPU_CX_BCR 0 +#define GPUCC_GPU_GX_BCR 1 +#define GPUCC_RBCPR_BCR 2 +#define GPUCC_SPDM_BCR 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-sdm660.h b/include/dt-bindings/clock/qcom,mmcc-sdm660.h new file mode 100644 index 000000000000..21b0f5df5477 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-sdm660.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H +#define _DT_BINDINGS_CLK_MSM_MMCC_660_H + +#define MMSS_CAMSS_JPEG0_VOTE_CLK 0 +#define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK 1 + +#define AHB_CLK_SRC 5 +#define BYTE0_CLK_SRC 6 +#define BYTE1_CLK_SRC 7 +#define CAMSS_GP0_CLK_SRC 8 +#define CAMSS_GP1_CLK_SRC 9 +#define CCI_CLK_SRC 10 +#define CPP_CLK_SRC 11 +#define CSI0_CLK_SRC 12 +#define CSI0PHYTIMER_CLK_SRC 13 +#define CSI1_CLK_SRC 14 +#define CSI1PHYTIMER_CLK_SRC 15 +#define CSI2_CLK_SRC 16 +#define CSI2PHYTIMER_CLK_SRC 17 +#define CSI3_CLK_SRC 18 +#define CSIPHY_CLK_SRC 19 +#define DP_AUX_CLK_SRC 20 +#define DP_CRYPTO_CLK_SRC 21 +#define DP_GTC_CLK_SRC 22 +#define DP_LINK_CLK_SRC 23 +#define DP_PIXEL_CLK_SRC 24 +#define ESC0_CLK_SRC 25 +#define ESC1_CLK_SRC 26 +#define JPEG0_CLK_SRC 27 +#define MCLK0_CLK_SRC 28 +#define MCLK1_CLK_SRC 29 +#define MCLK2_CLK_SRC 30 +#define MCLK3_CLK_SRC 31 +#define MDP_CLK_SRC 32 +#define MMPLL0_PLL 33 +#define MMPLL0_PLL_OUT_AUX 34 +#define MMPLL0_PLL_OUT_AUX2 35 +#define MMPLL0_PLL_OUT_EARLY 36 +#define MMPLL0_PLL_OUT_MAIN 37 +#define MMPLL0_PLL_OUT_TEST 38 +#define MMPLL10_PLL 39 +#define MMPLL10_PLL_OUT_AUX 40 +#define MMPLL10_PLL_OUT_AUX2 41 +#define MMPLL10_PLL_OUT_EARLY 42 +#define MMPLL10_PLL_OUT_MAIN 43 +#define MMPLL10_PLL_OUT_TEST 44 +#define MMPLL1_PLL 45 +#define MMPLL1_PLL_OUT_AUX 46 +#define MMPLL1_PLL_OUT_AUX2 47 +#define MMPLL1_PLL_OUT_EARLY 48 +#define MMPLL1_PLL_OUT_MAIN 49 +#define MMPLL1_PLL_OUT_TEST 50 +#define MMPLL3_PLL 51 +#define MMPLL3_PLL_OUT_AUX 52 +#define MMPLL3_PLL_OUT_AUX2 53 +#define MMPLL3_PLL_OUT_EARLY 54 +#define MMPLL3_PLL_OUT_MAIN 55 +#define MMPLL3_PLL_OUT_TEST 56 +#define MMPLL4_PLL 57 +#define MMPLL4_PLL_OUT_AUX 58 +#define MMPLL4_PLL_OUT_AUX2 59 +#define MMPLL4_PLL_OUT_EARLY 60 +#define MMPLL4_PLL_OUT_MAIN 61 +#define MMPLL4_PLL_OUT_TEST 62 +#define MMPLL5_PLL 63 +#define MMPLL5_PLL_OUT_AUX 64 +#define MMPLL5_PLL_OUT_AUX2 65 +#define MMPLL5_PLL_OUT_EARLY 66 +#define MMPLL5_PLL_OUT_MAIN 67 +#define MMPLL5_PLL_OUT_TEST 68 +#define MMPLL6_PLL 69 +#define MMPLL6_PLL_OUT_AUX 70 +#define MMPLL6_PLL_OUT_AUX2 71 +#define MMPLL6_PLL_OUT_EARLY 72 +#define MMPLL6_PLL_OUT_MAIN 73 +#define MMPLL6_PLL_OUT_TEST 74 +#define MMPLL7_PLL 75 +#define MMPLL7_PLL_OUT_AUX 76 +#define MMPLL7_PLL_OUT_AUX2 77 +#define MMPLL7_PLL_OUT_EARLY 78 +#define MMPLL7_PLL_OUT_MAIN 79 +#define MMPLL7_PLL_OUT_TEST 80 +#define MMPLL8_PLL 81 +#define MMPLL8_PLL_OUT_AUX 82 +#define MMPLL8_PLL_OUT_AUX2 83 +#define MMPLL8_PLL_OUT_EARLY 84 +#define MMPLL8_PLL_OUT_MAIN 85 +#define MMPLL8_PLL_OUT_TEST 86 +#define MMSS_BIMC_SMMU_AHB_CLK 87 +#define MMSS_BIMC_SMMU_AXI_CLK 88 +#define MMSS_CAMSS_AHB_CLK 89 +#define MMSS_CAMSS_CCI_AHB_CLK 90 +#define MMSS_CAMSS_CCI_CLK 91 +#define MMSS_CAMSS_CPHY_CSID0_CLK 92 +#define MMSS_CAMSS_CPHY_CSID1_CLK 93 +#define MMSS_CAMSS_CPHY_CSID2_CLK 94 +#define MMSS_CAMSS_CPHY_CSID3_CLK 95 +#define MMSS_CAMSS_CPP_AHB_CLK 96 +#define MMSS_CAMSS_CPP_AXI_CLK 97 +#define MMSS_CAMSS_CPP_CLK 98 +#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 99 +#define MMSS_CAMSS_CSI0_AHB_CLK 100 +#define MMSS_CAMSS_CSI0_CLK 101 +#define MMSS_CAMSS_CSI0PHYTIMER_CLK 102 +#define MMSS_CAMSS_CSI0PIX_CLK 103 +#define MMSS_CAMSS_CSI0RDI_CLK 104 +#define MMSS_CAMSS_CSI1_AHB_CLK 105 +#define MMSS_CAMSS_CSI1_CLK 106 +#define MMSS_CAMSS_CSI1PHYTIMER_CLK 107 +#define MMSS_CAMSS_CSI1PIX_CLK 108 +#define MMSS_CAMSS_CSI1RDI_CLK 109 +#define MMSS_CAMSS_CSI2_AHB_CLK 110 +#define MMSS_CAMSS_CSI2_CLK 111 +#define MMSS_CAMSS_CSI2PHYTIMER_CLK 112 +#define MMSS_CAMSS_CSI2PIX_CLK 113 +#define MMSS_CAMSS_CSI2RDI_CLK 114 +#define MMSS_CAMSS_CSI3_AHB_CLK 115 +#define MMSS_CAMSS_CSI3_CLK 116 +#define MMSS_CAMSS_CSI3PIX_CLK 117 +#define MMSS_CAMSS_CSI3RDI_CLK 118 +#define MMSS_CAMSS_CSI_VFE0_CLK 119 +#define MMSS_CAMSS_CSI_VFE1_CLK 120 +#define MMSS_CAMSS_CSIPHY0_CLK 121 +#define MMSS_CAMSS_CSIPHY1_CLK 122 +#define MMSS_CAMSS_CSIPHY2_CLK 123 +#define MMSS_CAMSS_GP0_CLK 124 +#define MMSS_CAMSS_GP1_CLK 125 +#define MMSS_CAMSS_ISPIF_AHB_CLK 126 +#define MMSS_CAMSS_JPEG0_CLK 127 +#define MMSS_CAMSS_JPEG_AHB_CLK 128 +#define MMSS_CAMSS_JPEG_AXI_CLK 129 +#define MMSS_CAMSS_MCLK0_CLK 130 +#define MMSS_CAMSS_MCLK1_CLK 131 +#define MMSS_CAMSS_MCLK2_CLK 132 +#define MMSS_CAMSS_MCLK3_CLK 133 +#define MMSS_CAMSS_MICRO_AHB_CLK 134 +#define MMSS_CAMSS_TOP_AHB_CLK 135 +#define MMSS_CAMSS_VFE0_AHB_CLK 136 +#define MMSS_CAMSS_VFE0_CLK 137 +#define MMSS_CAMSS_VFE0_STREAM_CLK 138 +#define MMSS_CAMSS_VFE1_AHB_CLK 139 +#define MMSS_CAMSS_VFE1_CLK 140 +#define MMSS_CAMSS_VFE1_STREAM_CLK 141 +#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 142 +#define MMSS_CAMSS_VFE_VBIF_AXI_CLK 143 +#define MMSS_CSIPHY_AHB2CRIF_CLK 144 +#define MMSS_CXO_CLK 145 +#define MMSS_MDSS_AHB_CLK 146 +#define MMSS_MDSS_AXI_CLK 147 +#define MMSS_MDSS_BYTE0_CLK 148 +#define MMSS_MDSS_BYTE0_INTF_CLK 149 +#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 150 +#define MMSS_MDSS_BYTE1_CLK 151 +#define MMSS_MDSS_BYTE1_INTF_CLK 152 +#define MMSS_MDSS_DP_AUX_CLK 153 +#define MMSS_MDSS_DP_CRYPTO_CLK 154 +#define MMSS_MDSS_DP_GTC_CLK 155 +#define MMSS_MDSS_DP_LINK_CLK 156 +#define MMSS_MDSS_DP_LINK_INTF_CLK 157 +#define MMSS_MDSS_DP_PIXEL_CLK 158 +#define MMSS_MDSS_ESC0_CLK 159 +#define MMSS_MDSS_ESC1_CLK 160 +#define MMSS_MDSS_HDMI_DP_AHB_CLK 161 +#define MMSS_MDSS_MDP_CLK 162 +#define MMSS_MDSS_PCLK0_CLK 163 +#define MMSS_MDSS_PCLK1_CLK 164 +#define MMSS_MDSS_ROT_CLK 165 +#define MMSS_MDSS_VSYNC_CLK 166 +#define MMSS_MISC_AHB_CLK 167 +#define MMSS_MISC_CXO_CLK 168 +#define MMSS_MNOC_AHB_CLK 169 +#define MMSS_SNOC_DVM_AXI_CLK 170 +#define MMSS_THROTTLE_CAMSS_AHB_CLK 171 +#define MMSS_THROTTLE_CAMSS_AXI_CLK 172 +#define MMSS_THROTTLE_CAMSS_CXO_CLK 173 +#define MMSS_THROTTLE_MDSS_AHB_CLK 174 +#define MMSS_THROTTLE_MDSS_AXI_CLK 175 +#define MMSS_THROTTLE_MDSS_CXO_CLK 176 +#define MMSS_THROTTLE_VIDEO_AHB_CLK 177 +#define MMSS_THROTTLE_VIDEO_AXI_CLK 178 +#define MMSS_THROTTLE_VIDEO_CXO_CLK 179 +#define MMSS_VIDEO_AHB_CLK 180 +#define MMSS_VIDEO_AXI_CLK 181 +#define MMSS_VIDEO_CORE_CLK 182 +#define MMSS_VIDEO_SUBCORE0_CLK 183 +#define PCLK0_CLK_SRC 184 +#define PCLK1_CLK_SRC 185 +#define ROT_CLK_SRC 186 +#define VFE0_CLK_SRC 187 +#define VFE1_CLK_SRC 188 +#define VIDEO_CORE_CLK_SRC 189 +#define VSYNC_CLK_SRC 190 +#define MMSS_MDSS_BYTE1_INTF_DIV_CLK 191 + +#define BIMC_SMMU_GDSC 0 +#define CAMSS_CPP_GDSC 1 +#define CAMSS_TOP_GDSC 2 +#define CAMSS_VFE0_GDSC 3 +#define CAMSS_VFE1_GDSC 4 +#define MDSS_GDSC 5 +#define VIDEO_SUBCORE0_GDSC 6 +#define VIDEO_TOP_GDSC 7 + +#define CAMSS_MICRO_BCR 0 + +#endif