Chip Select delay is the timing from the cs assert to first clock
toggle and last clock toggle to cs de-assert.
On minicore based targets like bengal, the cs delay could not be
increased using spi_cs_clk_dly register (the conventional register) as
it introduces some unexpected inter words delay. So, SB_PIPE_SEL
register can be used to achieve this purpose. It increases the last
clock to cs de-assert time.
In such cases, delay the clock initially by the same number of clocks
as SB_PIPE_SEL by setting the SPI_PRE_POST_CMD_DLY = n+SB_PIPE_SEL
(if it was set as n before) to increase the PRE_CMD delay as well.
Change-Id: Icc1c679e1c7930cb05f6e6a44a787a4afa0e00c3
Signed-off-by: Vipin Deep Kaur <vkaur@codeaurora.org>
21620b1d5b