mirror of
https://github.com/joeycastillo/second-movement.git
synced 2026-02-04 07:35:29 +00:00
137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
/*
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* MIT License
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*
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* Copyright (c) 2022 Joey Castillo
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* Copyright (c) 2025 Alessandro Genova
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <stddef.h>
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#include "rtc32.h"
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#include "sam.h"
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rtc_cb_t _rtc_callback = NULL;
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#if defined(_SAMD21_) || defined(_SAMD11_)
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#define CTRLREG (RTC->MODE0.CTRL)
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#define MODE_SETTING (RTC_MODE0_CTRL_MODE_COUNT32_Val) // Mode 0 Count32
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#define PRESCALER_SETTING (RTC_MODE0_CTRL_PRESCALER_DIV8_Val)
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#else
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#define CTRLREG (RTC->MODE0.CTRLA)
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#define MODE_SETTING (RTC_MODE0_CTRLA_MODE_COUNT32_Val) // Mode 0 Count32
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#define PRESCALER_SETTING (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val)
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#endif
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bool rtc_is_enabled(void) {
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return CTRLREG.bit.ENABLE;
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}
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static void _rtc_sync(void) {
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#if defined(_SAMD21_) || defined(_SAMD11_)
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while (RTC->MODE0.STATUS.bit.SYNCBUSY);
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#else
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while (RTC->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_MASK);
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#endif
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}
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void rtc_init(void) {
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#if defined(_SAMD21_) || defined(_SAMD11_)
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// enable the RTC
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PM->APBAMASK.reg |= PM_APBAMASK_RTC;
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// clock RTC with GCLK3 (prescaled 1024 Hz output from the external crystal)
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(3) | GCLK_CLKCTRL_ID(RTC_GCLK_ID) | GCLK_CLKCTRL_CLKEN;
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#else
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC;
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#endif
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if (rtc_is_enabled()) return; // don't reset the RTC if it's already set up.
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_rtc_sync();
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CTRLREG.bit.SWRST = 1;
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_rtc_sync();
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CTRLREG.bit.MODE = MODE_SETTING;
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CTRLREG.bit.PRESCALER = PRESCALER_SETTING;
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#if defined(_SAML21_) || defined(_SAML22_) || defined(_SAMD51_)
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CTRLREG.bit.COUNTSYNC = 1;
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#endif
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RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
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}
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void rtc_enable(void) {
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if (rtc_is_enabled()) return;
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CTRLREG.bit.ENABLE = 1;
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_rtc_sync();
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}
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void rtc_set_counter(rtc_counter_t counter) {
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// // syncing before and after was found to increase reliability on Sensor Watch
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_rtc_sync();
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RTC->MODE0.COUNT.reg = counter;
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_rtc_sync();
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}
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rtc_counter_t rtc_get_counter(void) {
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rtc_counter_t counter;
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#if defined(_SAML21_) || defined(_SAML22_) || defined(_SAMD51_)
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CTRLREG.bit.COUNTSYNC = 1;
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#endif
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_rtc_sync();
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counter = RTC->MODE0.COUNT.reg;
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return counter;
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}
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void rtc_enable_compare_interrupt(uint32_t compare_time) {
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RTC->MODE0.COMP[0].reg = compare_time;
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_rtc_sync();
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RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
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// NVIC_ClearPendingIRQ(RTC_IRQn);
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// NVIC_EnableIRQ(RTC_IRQn);
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}
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void rtc_configure_callback(rtc_cb_t callback) {
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_rtc_callback = callback;
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}
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void rtc_disable_compare_interrupt(void){
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RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0;
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// NVIC_ClearPendingIRQ(RTC_IRQn);
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// NVIC_DisableIRQ(RTC_IRQn);
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}
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void irq_handler_rtc(void);
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void irq_handler_rtc(void) {
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uint16_t int_cause = (uint16_t)RTC->MODE0.INTFLAG.reg;
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RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
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(void)RTC->MODE0.INTFLAG.reg;
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/* Invoke registered Callback function */
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if (_rtc_callback != NULL) {
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_rtc_callback(int_cause);
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}
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// NVIC_ClearPendingIRQ(RTC_IRQn);
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}
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