From a412a8e50d07fc789ea598f101a94570b1f33fc4 Mon Sep 17 00:00:00 2001 From: gab-k Date: Wed, 10 Dec 2025 23:04:39 +0100 Subject: [PATCH 1/8] hw/mcu: add support for NXP RW612 --- README.rst | 4 +- src/common/tusb_mcu.h | 8 ++++ src/portable/chipidea/ci_hs/ci_hs_rw61x.h | 48 +++++++++++++++++++++++ src/portable/chipidea/ci_hs/dcd_ci_hs.c | 3 ++ src/portable/ehci/ehci.c | 2 +- src/tusb_option.h | 1 + 6 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 src/portable/chipidea/ci_hs/ci_hs_rw61x.h diff --git a/README.rst b/README.rst index 6a6f07825..463cc8b42 100644 --- a/README.rst +++ b/README.rst @@ -208,7 +208,9 @@ Supported CPUs | | MCX | N9 | ✔ | | ✔ | ci_fs, ci_hs, ehci | | | | +-------------------+--------+------+-----------+------------------------+-------------------+ | | | A15 | ✔ | | | ci_fs | | -+--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+ +| +---------+-------------------+--------+------+-----------+------------------------+-------------------+ +| | RW61x | ✔ | | ✔ | ci_hs, ehci | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ | Raspberry Pi | RP2040, RP2350 | ✔ | ✔ | ✖ | rp2040, pio_usb | | +--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ | Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | rusb2 | | diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 1e773bf96..89316ee77 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -111,6 +111,14 @@ #define TUP_DCD_ENDPOINT_MAX 16 +#elif TU_CHECK_MCU(OPT_MCU_RW61X) + // USB0 is chipidea HS + #define TUP_USBIP_CHIPIDEA_HS + #define TUP_USBIP_EHCI + + #define TUP_DCD_ENDPOINT_MAX 8 + #define TUP_RHPORT_HIGHSPEED 1 + #elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX) #include "fsl_device_registers.h" diff --git a/src/portable/chipidea/ci_hs/ci_hs_rw61x.h b/src/portable/chipidea/ci_hs/ci_hs_rw61x.h new file mode 100644 index 000000000..114fe26c3 --- /dev/null +++ b/src/portable/chipidea/ci_hs/ci_hs_rw61x.h @@ -0,0 +1,48 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CI_HS_RW61X_H_ +#define _CI_HS_RW61X_H_ + +#include "fsl_device_registers.h" + +static const ci_hs_controller_t _ci_controller[] = { + {.reg_base = USBOTG_BASE, .irqnum = USB_IRQn} +}; + +TU_ATTR_ALWAYS_INLINE static inline ci_hs_regs_t* CI_HS_REG(uint8_t port) { + (void) port; + return ((ci_hs_regs_t*) _ci_controller[0].reg_base); +} + +#define CI_DCD_INT_ENABLE(_p) do { (void) _p; NVIC_EnableIRQ (_ci_controller[0].irqnum); } while (0) +#define CI_DCD_INT_DISABLE(_p) do { (void) _p; NVIC_DisableIRQ(_ci_controller[0].irqnum); } while (0) + +#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) +#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) + + +#endif diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 4a5e5c91f..27298989c 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -55,6 +55,9 @@ bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { // MCX N9 only port 1 use this controller #include "ci_hs_mcx.h" +#elif TU_CHECK_MCU(OPT_MCU_RW61X) + #include "ci_hs_rw61x.h" + #else #error "Unsupported MCUs" #endif diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index c33c970e4..e604a0360 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -40,7 +40,7 @@ #include "ehci.h" // NXP specific fixes -#if TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX, OPT_MCU_LPC55, OPT_MCU_MCXN9) +#if TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX, OPT_MCU_LPC55, OPT_MCU_MCXN9, OPT_MCU_RW61X) #include "fsl_device_registers.h" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index be954e01a..68f2d3598 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -199,6 +199,7 @@ // NXP LPC MCX #define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series #define OPT_MCU_MCXA15 2301 ///< NXP MCX A15 Series +#define OPT_MCU_RW61X 2302 ///< NXP RW61x Series // Analog Devices #define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 From b43b99a571e81fb99f6603d9534f7d4bb55e8d02 Mon Sep 17 00:00:00 2001 From: gab-k Date: Sun, 14 Dec 2025 01:30:12 +0100 Subject: [PATCH 2/8] bsp: nxp: add support for RW612 (FRDM-RW612) - Added `rw61x` family support. - Added `frdm_rw612` board support. - Update `get_deps.py` to include mcux-sdk for RW61x. - Add ci_hs_rw61x include to ChipIdea HS driver and enable host examples. --- examples/host/bare_api/only.txt | 1 + examples/host/cdc_msc_hid/only.txt | 1 + examples/host/cdc_msc_hid_freertos/only.txt | 1 + examples/host/device_info/only.txt | 1 + examples/host/hid_controller/only.txt | 1 + examples/host/midi_rx/only.txt | 1 + examples/host/msc_file_explorer/only.txt | 1 + hw/bsp/rw61x/FreeRTOSConfig/FreeRTOSConfig.h | 150 ++++++++++++ hw/bsp/rw61x/boards/frdm_rw612/board.cmake | 30 +++ hw/bsp/rw61x/boards/frdm_rw612/board.h | 76 ++++++ hw/bsp/rw61x/boards/frdm_rw612/board.mk | 20 ++ hw/bsp/rw61x/boards/frdm_rw612/clock_config.c | 170 +++++++++++++ hw/bsp/rw61x/boards/frdm_rw612/clock_config.h | 116 +++++++++ hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c | 223 ++++++++++++++++++ hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h | 146 ++++++++++++ hw/bsp/rw61x/family.c | 135 +++++++++++ hw/bsp/rw61x/family.cmake | 102 ++++++++ hw/bsp/rw61x/family.mk | 52 ++++ src/portable/chipidea/ci_hs/hcd_ci_hs.c | 3 + tools/get_deps.py | 4 +- 20 files changed, 1232 insertions(+), 2 deletions(-) create mode 100644 hw/bsp/rw61x/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/rw61x/boards/frdm_rw612/board.cmake create mode 100644 hw/bsp/rw61x/boards/frdm_rw612/board.h create mode 100644 hw/bsp/rw61x/boards/frdm_rw612/board.mk create mode 100644 hw/bsp/rw61x/boards/frdm_rw612/clock_config.c create mode 100644 hw/bsp/rw61x/boards/frdm_rw612/clock_config.h create mode 100644 hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c create mode 100644 hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h create mode 100644 hw/bsp/rw61x/family.c create mode 100644 hw/bsp/rw61x/family.cmake create mode 100644 hw/bsp/rw61x/family.mk diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index cba58f8e8..1c9ae72eb 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -8,6 +8,7 @@ mcu:LPC43XX mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX +mcu:RW61X mcu:RP2040 mcu:MSP432E4 mcu:RX65X diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index cba58f8e8..1c9ae72eb 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -8,6 +8,7 @@ mcu:LPC43XX mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX +mcu:RW61X mcu:RP2040 mcu:MSP432E4 mcu:RX65X diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index ef0a1ac96..5c5b7c56d 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -6,6 +6,7 @@ mcu:LPC43XX mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX +mcu:RW61X mcu:MSP432E4 mcu:RX65X mcu:MAX3421 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index 61a08f68d..892cbf4b8 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -9,6 +9,7 @@ mcu:MAX3421 mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX +mcu:RW61X mcu:MSP432E4 mcu:RP2040 mcu:RX65X diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index cba58f8e8..1c9ae72eb 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -8,6 +8,7 @@ mcu:LPC43XX mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX +mcu:RW61X mcu:RP2040 mcu:MSP432E4 mcu:RX65X diff --git a/examples/host/midi_rx/only.txt b/examples/host/midi_rx/only.txt index 133a7c9a0..ff9c0bcb8 100644 --- a/examples/host/midi_rx/only.txt +++ b/examples/host/midi_rx/only.txt @@ -12,6 +12,7 @@ mcu:MAX3421 mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX +mcu:RW61X mcu:MSP432E4 mcu:RP2040 mcu:RX65X diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index cba58f8e8..1c9ae72eb 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -8,6 +8,7 @@ mcu:LPC43XX mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX +mcu:RW61X mcu:RP2040 mcu:MSP432E4 mcu:RX65X diff --git a/hw/bsp/rw61x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/rw61x/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..281b4d40c --- /dev/null +++ b/hw/bsp/rw61x/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "fsl_device_registers.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 0 // RW61x has FPU but is disabled due to using cortex-m33-nodsp-nofp.mk +#define configENABLE_TRUSTZONE 0 +#define configRUN_FREERTOS_SECURE_ONLY 1 // Cortex-M33 runs in secure mode after reset by default! +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 3 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U) + { + /* Enable the CAU sleep clock. */ + CLOCK_EnableClock(kCLOCK_RefClkCauSlp); + } + if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U) + { + /* Enable the REFCLK_SYS clock. */ + CLOCK_EnableClock(kCLOCK_RefClkSys); + } + /* Initialize T3 PLL and enable outputs that are not clock gated. */ + CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m); + /* Enable FFRO - T3 PLL 48/60 MHz IRC clock output */ + CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk); + /* Enable T3 PLL 256 MHz clock output */ + CLOCK_EnableClock(kCLOCK_T3PllMci256mClk); + /* Set core clock to safe system oscillator clock for initialization of other sources. */ + CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1); + /* Enable TCPU PLL MCI clock output */ + CLOCK_EnableClock(kCLOCK_TcpuMciClk); + /* Initialize TDDR PLL and enable outputs that are not clock gated. */ + CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10); + /* Enable TDDR PLL FlexSPI clock output */ + CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk); + /* Initialize AVPLL and enable both channels. */ + CLOCK_InitAvPll(&avpllConfig_BOARD_BootClockRUN); + /* Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kRC32K_to_CLK32K); /* Switch CLK32K to RC32K */ + /*!< Please note SYSTICK_CLK source is used only if the SysTick SYST_CSR register CLKSOURCE bit is set to 0. */ + CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK); /* Switch SYSTICK_CLK to SYSTICK_DIV */ + /* Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); /* Set .AUDIOPLLCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); /* Set .FRGPLLCLKDIV divider to value 13 */ + CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); /* Set .MAINPLLCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); /* Set .AUX0PLLCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U); /* Set .SYSTICKFCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U); /* Set .PMUFCLKDIV divider to value 5 */ + /* Select the main clock source for the main system clock (MAINCLKSELA and MAINCLKSELB). */ + CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_HCLK; +} + diff --git a/hw/bsp/rw61x/boards/frdm_rw612/clock_config.h b/hw/bsp/rw61x/boards/frdm_rw612/clock_config.h new file mode 100644 index 000000000..3b467d869 --- /dev/null +++ b/hw/bsp/rw61x/boards/frdm_rw612/clock_config.h @@ -0,0 +1,116 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AUDIO_PLL_CLK 12287999UL /* Clock consumers of audio_pll_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_AUX0_PLL_CLK 260000000UL /* Clock consumers of aux0_pll_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_AUX1_PLL_CLK 0UL /* Clock consumers of aux1_pll_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_AVPLL_CH1_CLKOUT 12287999UL /* Clock consumers of avpll_ch1_clkout output : N/A */ +#define BOARD_BOOTCLOCKRUN_AVPLL_CH2_CLKOUT 63999997UL /* Clock consumers of avpll_ch2_clkout output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAU_SLP_CLK 4000000UL /* Clock consumers of cau_slp_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_32K 32000UL /* Clock consumers of clk_32k output : RTC */ +#define BOARD_BOOTCLOCKRUN_CLK_OUT 0UL /* Clock consumers of clk_out output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_PMU_SYS 52000000UL /* Clock consumers of clk_pmu_sys output : PMU */ +#define BOARD_BOOTCLOCKRUN_CTIMER0_FCLK 0UL /* Clock consumers of ctimer0_fclk output : CTIMER0 */ +#define BOARD_BOOTCLOCKRUN_CTIMER1_FCLK 0UL /* Clock consumers of ctimer1_fclk output : CTIMER1 */ +#define BOARD_BOOTCLOCKRUN_CTIMER2_FCLK 0UL /* Clock consumers of ctimer2_fclk output : CTIMER2 */ +#define BOARD_BOOTCLOCKRUN_CTIMER3_FCLK 0UL /* Clock consumers of ctimer3_fclk output : CTIMER3 */ +#define BOARD_BOOTCLOCKRUN_DMIC_FCLK 0UL /* Clock consumers of dmic_fclk output : DMIC0 */ +#define BOARD_BOOTCLOCKRUN_ELS_128M_CLK 128000000UL /* Clock consumers of els_128m_clk output : ELS */ +#define BOARD_BOOTCLOCKRUN_ELS_256M_CLK 256000000UL /* Clock consumers of els_256m_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_ELS_64M_CLK 64000000UL /* Clock consumers of els_64m_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_ELS_FCLK 0UL /* Clock consumers of els_fclk output : ELS */ +#define BOARD_BOOTCLOCKRUN_FFRO_CLK_DIV4 12075471UL /* Clock consumers of ffro_clk_div4 output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXCOMM0_FCLK 0UL /* Clock consumers of flexcomm0_fclk output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKRUN_FLEXCOMM14_FCLK 0UL /* Clock consumers of flexcomm14_fclk output : FLEXCOMM14 */ +#define BOARD_BOOTCLOCKRUN_FLEXCOMM1_FCLK 0UL /* Clock consumers of flexcomm1_fclk output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKRUN_FLEXCOMM2_FCLK 0UL /* Clock consumers of flexcomm2_fclk output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKRUN_FLEXCOMM3_FCLK 0UL /* Clock consumers of flexcomm3_fclk output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_FCLK 0UL /* Clock consumers of flexspi_fclk output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GAU_FCLK 0UL /* Clock consumers of gau_fclk output : GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1 */ +#define BOARD_BOOTCLOCKRUN_HCLK 260000000UL /* Clock consumers of hclk output : AHB_SECURE_CTRL, APU0, APU1, BLEAPU, BLECTRL, BUCK11, BUCK18, CACHE64_CTRL0, CACHE64_CTRL1, CACHE64_POLSEL0, CACHE64_POLSEL1, CAU, CDOG, CLKCTL0, CLKCTL1, CRC, CTIMER0, CTIMER1, CTIMER2, CTIMER3, DMA0, DMA1, DMIC0, ELS, ENET, FLEXCOMM0, FLEXCOMM1, FLEXCOMM14, FLEXCOMM2, FLEXCOMM3, FLEXSPI, FREQME, GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1, GDMA, GPIO, INPUTMUX, ITRC, LCDIC, MCI_IO_MUX, MRT0, MRT1, OCOTP, OSTIMER, PINT, PKC, PMU, POWERQUAD, PUF, ROMCP, RSTCTL0, RSTCTL1, RTC, SCT0, SDU_FBR_CARD, SDU_FN0_CARD, SDU_FN_CARD, SECGPIO, SENSOR_CTRL, SOCCTRL, SOC_OTP_CTRL, SYSCTL0, SYSCTL1, SYSCTL2, SysTick, TRNG, USBOTG, USIM, UTICK, WLAPU, WLCTRL, WWDT0 */ +#define BOARD_BOOTCLOCKRUN_LCD_FCLK 0UL /* Clock consumers of lcd_fclk output : LCDIC */ +#define BOARD_BOOTCLOCKRUN_LPOSC_CLK_I 1000000UL /* Clock consumers of lposc_clk_i output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAIN_CLK 260000000UL /* Clock consumers of main_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAIN_PLL_CLK 260000000UL /* Clock consumers of main_pll_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_MCLK_OUT 0UL /* Clock consumers of mclk_out output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSEVENT_FCLK 0UL /* Clock consumers of osevent_fclk output : OSTIMER */ +#define BOARD_BOOTCLOCKRUN_OTP_FUSE_32M_CLK 32000000UL /* Clock consumers of otp_fuse_32m_clk output : OCOTP */ +#define BOARD_BOOTCLOCKRUN_REFCLK_PHY 40000000UL /* Clock consumers of refclk_phy output : USBOTG */ +#define BOARD_BOOTCLOCKRUN_REFCLK_SYS 0UL /* Clock consumers of refclk_sys output : N/A */ +#define BOARD_BOOTCLOCKRUN_SCT_FCLK 0UL /* Clock consumers of sct_fclk output : SCT0 */ +#define BOARD_BOOTCLOCKRUN_SFRO_CLK_I 16000000UL /* Clock consumers of sfro_clk_i output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYSOSC_CLK_I 0UL /* Clock consumers of sysosc_clk_i output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYSTICK_FCLK 260000000UL /* Clock consumers of systick_fclk output : SysTick */ +#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_213P3M 0UL /* Clock consumers of t3pll_mci_213p3m output : N/A */ +#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_256M 256000000UL /* Clock consumers of t3pll_mci_256m output : N/A */ +#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_48_60M_IRC 48301886UL /* Clock consumers of t3pll_mci_48_60m_irc output : N/A */ +#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_FLEXSPI_CLK 0UL /* Clock consumers of t3pll_mci_flexspi_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_TCPU_MCI_CLK 260000000UL /* Clock consumers of tcpu_mci_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_TCPU_MCI_FLEXSPI_CLK 0UL /* Clock consumers of tcpu_mci_flexspi_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_TDDR_MCI_ENET_CLK 0UL /* Clock consumers of tddr_mci_enet_clk output : ENET */ +#define BOARD_BOOTCLOCKRUN_TDDR_MCI_FLEXSPI_CLK 320000000UL /* Clock consumers of tddr_mci_flexspi_clk output : N/A */ +#define BOARD_BOOTCLOCKRUN_USIM_FCLK 0UL /* Clock consumers of usim_fclk output : USIM */ +#define BOARD_BOOTCLOCKRUN_UTICK_FCLK 0UL /* Clock consumers of utick_fclk output : UTICK */ +#define BOARD_BOOTCLOCKRUN_WDT0_FCLK 0UL /* Clock consumers of wdt0_fclk output : WWDT0 */ + +/*! @brief AVPLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN; +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c new file mode 100644 index 000000000..49b74b2bb --- /dev/null +++ b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c @@ -0,0 +1,223 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: RW612 +package_id: RW612ETA2I +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: FRDM-RW612 +pin_labels: +- {pin_num: M2, pin_signal: GPIO_11, label: 'J1[6]/WAKEUP_BTN', identifier: WAKEUP;WAKEUP_BTN} +- {pin_num: L7, pin_signal: GPIO_5, label: 'J1[7]/MCLK', identifier: MCLKOUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_io_mux.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); + BOARD_InitDEBUG_UARTPins(); + BOARD_InitSWD_DEBUGPins(); + BOARD_InitLEDPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: M2, peripheral: GPIO, signal: 'PIO0, 11', pin_signal: GPIO_11, identifier: WAKEUP_BTN, direction: INPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 */ +void BOARD_InitPins(void) +{ + /* Enables the clock for the GPIO0 module */ + GPIO_PortInit(GPIO, 0); + + gpio_pin_config_t WAKEUP_BTN_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_11 (pin M2) */ + GPIO_PinInit(BOARD_INITPINS_WAKEUP_BTN_GPIO, BOARD_INITPINS_WAKEUP_BTN_PORT, BOARD_INITPINS_WAKEUP_BTN_PIN, &WAKEUP_BTN_config); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: E5, peripheral: FLEXCOMM3, signal: USART_RXD, pin_signal: GPIO_24} + - {pin_num: F6, peripheral: FLEXCOMM3, signal: USART_TXD, pin_signal: GPIO_26} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Initialize FC3_USART_DATA functionality on pin GPIO_24, GPIO_26 (pin E5_F6) */ + IO_MUX_SetPinMux(IO_MUX_FC3_USART_DATA); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: G5, peripheral: SWD, signal: CLK, pin_signal: GPIO_13} + - {pin_num: K4, peripheral: SWD, signal: IO, pin_signal: GPIO_14} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 */ +void BOARD_InitSWD_DEBUGPins(void) +{ + + MCI_IO_MUX->C_TIMER_IN = ((MCI_IO_MUX->C_TIMER_IN & + /* Mask bits to zero which are setting */ + (~(MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL_MASK | MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL_MASK))) + + /* sel GPIO-13 as ct_inp3: 0x00u */ + | MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL(0x00u) + /* sel GPIO-14 as ct_inp4: 0x00u */ + | MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL(0x00u)); + + MCI_IO_MUX->C_TIMER_OUT = ((MCI_IO_MUX->C_TIMER_OUT & + /* Mask bits to zero which are setting */ + (~(MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL_MASK | MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL_MASK))) + + /* sel GPIO-13 as ct0mat3: 0x00u */ + | MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL(0x00u) + /* sel GPIO-14 as ct1mat0: 0x00u */ + | MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL(0x00u)); + + MCI_IO_MUX->FC2 = + ((MCI_IO_MUX->FC2 & + /* Mask bits to zero which are setting */ + (~(MCI_IO_MUX_FC2_SEL_FC2_I2C_MASK | MCI_IO_MUX_FC2_SEL_FC2_I2S_MASK | MCI_IO_MUX_FC2_SEL_FC2_SPI_MASK | MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY_MASK | MCI_IO_MUX_FC2_SEL_FC2_USART_DATA_MASK))) + + /* flexcomm2:select GPIO-13/14 as i2c function: 0x00u */ + | MCI_IO_MUX_FC2_SEL_FC2_I2C(0x00u) + /* flexcomm2:select GPIO-13/14/15 as i2s function: 0x00u */ + | MCI_IO_MUX_FC2_SEL_FC2_I2S(0x00u) + /* flexcomm2:select GPIO-13/14/15/16 as spi function: 0x00u */ + | MCI_IO_MUX_FC2_SEL_FC2_SPI(0x00u) + /* flexcomm2:select GPIO-13 as i2s data function: 0x00u */ + | MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY(0x00u) + /* flexcomm2:select GPIO-13/14 as usart rxd/txd: 0x00u */ + | MCI_IO_MUX_FC2_SEL_FC2_USART_DATA(0x00u)); + + MCI_IO_MUX->GPIO_GRP0 = ((MCI_IO_MUX->GPIO_GRP0 & + /* Mask bits to zero which are setting */ + (~(MCI_IO_MUX_GPIO_GRP0_SEL_13_MASK | MCI_IO_MUX_GPIO_GRP0_SEL_14_MASK))) + + /* pio0[31:0] selection, high valid; sel[i]->pio0[i]->GPIO[i]: 0x00u */ + | MCI_IO_MUX_GPIO_GRP0_SEL(0x00u)); + + SOCCTRL->MCI_IOMUX_EN0 = ((SOCCTRL->MCI_IOMUX_EN0 & + /* Mask bits to zero which are setting */ + (~(SOCCIU_MCI_IOMUX_EN0_EN_21_0_13_MASK | SOCCIU_MCI_IOMUX_EN0_EN_21_0_14_MASK))) + + /* Bitwise enable control for mci_io_mux GPIO[21:0]: 0x00u */ + | SOCCIU_MCI_IOMUX_EN0_EN_21_0(0x00u)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: M1, peripheral: GPIO, signal: 'PIO0, 0', pin_signal: GPIO_0, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: N2, peripheral: GPIO, signal: 'PIO0, 1', pin_signal: GPIO_1, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: N8, peripheral: GPIO, signal: 'PIO0, 12', pin_signal: GPIO_12, direction: OUTPUT, gpio_init_state: 'true'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 */ +void BOARD_InitLEDPins(void) +{ + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_HsGpio0); + + gpio_pin_config_t LED_BLUE_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO0_0 (pin M1) */ + GPIO_PinInit(BOARD_INITLEDPINS_LED_BLUE_GPIO, BOARD_INITLEDPINS_LED_BLUE_PORT, BOARD_INITLEDPINS_LED_BLUE_PIN, &LED_BLUE_config); + + gpio_pin_config_t LED_RED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO0_1 (pin N2) */ + GPIO_PinInit(BOARD_INITLEDPINS_LED_RED_GPIO, BOARD_INITLEDPINS_LED_RED_PORT, BOARD_INITLEDPINS_LED_RED_PIN, &LED_RED_config); + + gpio_pin_config_t LED_GREEN_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO0_12 (pin N8) */ + GPIO_PinInit(BOARD_INITLEDPINS_LED_GREEN_GPIO, BOARD_INITLEDPINS_LED_GREEN_PORT, BOARD_INITLEDPINS_LED_GREEN_PIN, &LED_GREEN_config); + /* Initialize GPIO0 functionality on pin GPIO_0 (pin M1) */ + IO_MUX_SetPinMux(IO_MUX_GPIO0); + /* Initialize GPIO1 functionality on pin GPIO_1 (pin N2) */ + IO_MUX_SetPinMux(IO_MUX_GPIO1); + /* Initialize GPIO12 functionality on pin GPIO_12 (pin N8) */ + IO_MUX_SetPinMux(IO_MUX_GPIO12); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h new file mode 100644 index 000000000..f4c9a9127 --- /dev/null +++ b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h @@ -0,0 +1,146 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief mclk direction control: MCLK is in the output direction. */ +#define MCLKPINDIR_MCLKPINDIR_OUTPUT_DIRECTION 0x01u + +/*! @name GPIO_5 (coord L7), J1[7]/MCLK + @{ */ +/* Routed pin properties */ +#define BOARD_INITPINS_MCLKOUT_PERIPHERAL CLKCTL1 /*!<@brief Peripheral name */ +#define BOARD_INITPINS_MCLKOUT_SIGNAL MCLK /*!<@brief Signal name */ +#define BOARD_INITPINS_MCLKOUT_GPIO_PIN 5U /*!<@brief GPIO pin number */ +#define BOARD_INITPINS_MCLKOUT_PORT 0U /*!<@brief PORT number */ +#define BOARD_INITPINS_MCLKOUT_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITPINS_MCLKOUT_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name GPIO_11 (coord M2), J1[6]/WAKEUP_BTN + @{ */ +/* Routed pin properties */ +#define BOARD_INITPINS_WAKEUP_BTN_PERIPHERAL GPIO /*!<@brief Peripheral name */ +#define BOARD_INITPINS_WAKEUP_BTN_SIGNAL PIO0 /*!<@brief Signal name */ +#define BOARD_INITPINS_WAKEUP_BTN_CHANNEL 11 /*!<@brief Signal channel */ +#define BOARD_INITPINS_WAKEUP_BTN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITPINS_WAKEUP_BTN_GPIO_PIN 11U /*!<@brief GPIO pin number */ +#define BOARD_INITPINS_WAKEUP_BTN_PORT 0U /*!<@brief PORT number */ +#define BOARD_INITPINS_WAKEUP_BTN_PIN 11U /*!<@brief PORT pin number */ +#define BOARD_INITPINS_WAKEUP_BTN_PIN_MASK (1U << 11U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief pio0[31:0] selection, high valid; sel[i]->pio0[i]->GPIO[i] Mask for item 13. */ +#define MCI_IO_MUX_GPIO_GRP0_SEL_13_MASK 0x2000u +/*! + * @brief pio0[31:0] selection, high valid; sel[i]->pio0[i]->GPIO[i] Mask for item 14. */ +#define MCI_IO_MUX_GPIO_GRP0_SEL_14_MASK 0x4000u +/*! + * @brief Bitwise enable control for mci_io_mux GPIO[21:0] Mask for item 13. */ +#define SOCCIU_MCI_IOMUX_EN0_EN_21_0_13_MASK 0x2000u +/*! + * @brief Bitwise enable control for mci_io_mux GPIO[21:0] Mask for item 14. */ +#define SOCCIU_MCI_IOMUX_EN0_EN_21_0_14_MASK 0x4000u + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 */ + +/*! @name GPIO_0 (coord M1), J1[14]/LED_BLUE + @{ */ +/* Routed pin properties */ +#define BOARD_INITLEDPINS_LED_BLUE_PERIPHERAL GPIO /*!<@brief Peripheral name */ +#define BOARD_INITLEDPINS_LED_BLUE_SIGNAL PIO0 /*!<@brief Signal name */ +#define BOARD_INITLEDPINS_LED_BLUE_CHANNEL 0 /*!<@brief Signal channel */ +#define BOARD_INITLEDPINS_LED_BLUE_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDPINS_LED_BLUE_GPIO_PIN 0U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDPINS_LED_BLUE_PORT 0U /*!<@brief PORT number */ +#define BOARD_INITLEDPINS_LED_BLUE_PIN 0U /*!<@brief PORT pin number */ +#define BOARD_INITLEDPINS_LED_BLUE_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name GPIO_1 (coord N2), J5[1]/LED_RED + @{ */ +/* Routed pin properties */ +#define BOARD_INITLEDPINS_LED_RED_PERIPHERAL GPIO /*!<@brief Peripheral name */ +#define BOARD_INITLEDPINS_LED_RED_SIGNAL PIO0 /*!<@brief Signal name */ +#define BOARD_INITLEDPINS_LED_RED_CHANNEL 1 /*!<@brief Signal channel */ +#define BOARD_INITLEDPINS_LED_RED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDPINS_LED_RED_GPIO_PIN 1U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDPINS_LED_RED_PORT 0U /*!<@brief PORT number */ +#define BOARD_INITLEDPINS_LED_RED_PIN 1U /*!<@brief PORT pin number */ +#define BOARD_INITLEDPINS_LED_RED_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name GPIO_12 (coord N8), LED_GREEN + @{ */ +/* Routed pin properties */ +#define BOARD_INITLEDPINS_LED_GREEN_PERIPHERAL GPIO /*!<@brief Peripheral name */ +#define BOARD_INITLEDPINS_LED_GREEN_SIGNAL PIO0 /*!<@brief Signal name */ +#define BOARD_INITLEDPINS_LED_GREEN_CHANNEL 12 /*!<@brief Signal channel */ +#define BOARD_INITLEDPINS_LED_GREEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDPINS_LED_GREEN_GPIO_PIN 12U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDPINS_LED_GREEN_PORT 0U /*!<@brief PORT number */ +#define BOARD_INITLEDPINS_LED_GREEN_PIN 12U /*!<@brief PORT pin number */ +#define BOARD_INITLEDPINS_LED_GREEN_PIN_MASK (1U << 12U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDPins(void); /* Function assigned for the Cortex-M33 */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/rw61x/family.c b/hw/bsp/rw61x/family.c new file mode 100644 index 000000000..226956f15 --- /dev/null +++ b/hw/bsp/rw61x/family.c @@ -0,0 +1,135 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2025, Gabriel Koppenstein + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: NXP +*/ + +#include "bsp/board_api.h" +#include "fsl_device_registers.h" +#include "fsl_gpio.h" +#include "board.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#include "pin_mux.h" +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +void USB_IRQHandler(void) { + tusb_int_handler(1, true); +} + +void board_init(void) { + + // Init button pin, LED pins, SWD pins & UART pins + BOARD_InitBootPins(); + + // Init Clocks + BOARD_InitBootClocks(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR from running before scheduler start + SysTick->CTRL &= ~1U; + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + +#ifdef NEOPIXEL_PIN + // No neo pixel support yet +#endif + +#ifdef UART_DEV + // Enable UART when debug log is on + board_uart_init_clock(); + usart_config_t uart_config; + USART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableRx = true; + uart_config.enableTx = true; + USART_Init(UART_DEV, &uart_config, CLOCK_GetFlexCommClkFreq(LP_FLEXCOMM_INST)); +#endif + + // USB Initialization + // Reset USB + RESET_PeripheralReset(kUSB_RST_SHIFT_RSTn); + + // Enable USB Clock + CLOCK_EnableClock(kCLOCK_Usb); + + // Enable USB PHY + CLOCK_EnableUsbhsPhyClock(); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { + GPIO_PinWrite(LED_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); +} + +uint32_t board_button_read(void) { +#ifdef BUTTON_GPIO + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BOARD_INITPINS_WAKEUP_BTN_PORT, BUTTON_PIN); +#endif +} + +int board_uart_read(uint8_t* buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const* buf, int len) { +#ifdef UART_DEV + USART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len); + return len; +#else + (void) buf; (void) len; + return 0; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} + +#endif diff --git a/hw/bsp/rw61x/family.cmake b/hw/bsp/rw61x/family.cmake new file mode 100644 index 000000000..5428b7e50 --- /dev/null +++ b/hw/bsp/rw61x/family.cmake @@ -0,0 +1,102 @@ +include_guard() + +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS RW61X CACHE INTERNAL "") + +#------------------------------------ +# Startup & Linker script +#------------------------------------ + +set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) +set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +function(family_add_board BOARD_TARGET) + add_library(${BOARD_TARGET} STATIC + ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c + ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c + ${SDK_DIR}/drivers/common/fsl_common_arm.c + ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c + ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c + ${SDK_DIR}/drivers/flexspi/fsl_flexspi.c + ) + + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMSIS_5}/CMSIS/Core/Include + ${SDK_DIR}/devices/${MCU_VARIANT} + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/drivers + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/lpc_gpio + ${SDK_DIR}/drivers/flexcomm + ${SDK_DIR}/drivers/flexcomm/usart + ${SDK_DIR}/drivers/flexspi + ) + + update_board(${BOARD_TARGET}) +endfunction() + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_RW61X) + + target_sources(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + + # ChipIdea HS + ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c + ${TOP}/src/portable/ehci/ehci.c + + # Startup File + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + + # Add Board specific includes + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Linker Options + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + --specs=nosys.specs + --specs=nano.specs + ) + endif() + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") + set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes") + endif () + + # Handle Startup File Properties (Linting/Warnings) + set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES + SKIP_LINTING ON + COMPILE_OPTIONS -w + ) + + # Flashing & Binary Generation + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() \ No newline at end of file diff --git a/hw/bsp/rw61x/family.mk b/hw/bsp/rw61x/family.mk new file mode 100644 index 000000000..e715adfa8 --- /dev/null +++ b/hw/bsp/rw61x/family.mk @@ -0,0 +1,52 @@ +UF2_FAMILY_ID = 0x2abc77ec +SDK_DIR = hw/mcu/nxp/mcux-sdk + +include $(TOP)/$(BOARD_PATH)/board.mk + +# Default to Highspeed PORT1 +PORT ?= 1 + +CFLAGS += \ + -flto \ + -DBOARD_TUD_RHPORT=$(PORT) \ + -DBOARD_TUH_RHPORT=$(PORT) \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED \ + -DBOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED \ + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls + +LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs + +# All source paths should be relative to the top level. +LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld + +SRC_C += \ + src/portable/chipidea/ci_hs/dcd_ci_hs.c \ + src/portable/chipidea/ci_hs/hcd_ci_hs.c \ + src/portable/ehci/ehci.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_power.c \ + $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ + $(SDK_DIR)/drivers/common/fsl_common_arm.c\ + $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ + $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ + $(SDK_DIR)/drivers/flexspi/fsl_flexspi.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \ + $(TOP)/$(SDK_DIR)/drivers/ \ + $(TOP)/$(SDK_DIR)/drivers/common\ + $(TOP)/$(SDK_DIR)/drivers/lpc_gpio\ + $(TOP)/$(SDK_DIR)/drivers/flexcomm \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ + $(TOP)/$(SDK_DIR)/drivers/flexspi \ + + +SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index b5324a754..fe2895f6a 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -61,6 +61,9 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { #include "ci_hs_lpc18_43.h" +#elif TU_CHECK_MCU(OPT_MCU_RW61X) +#include "ci_hs_rw61x.h" + #else #error "Unsupported MCUs" #endif diff --git a/tools/get_deps.py b/tools/get_deps.py index 0d9c1a8f1..17c2ab8b8 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -60,7 +60,7 @@ deps_optional = { 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'], 'hw/mcu/nxp/mcux-sdk': ['https://github.com/nxp-mcuxpresso/mcux-sdk', 'a1bdae309a14ec95a4f64a96d3315a4f89c397c6', - 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], + 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', '675543bcc9baa8170f868ab7ba316d418dbcf41f', 'rp2040'], @@ -246,7 +246,7 @@ deps_optional = { 'at32f413'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c', - 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' + 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x mm32 msp432e4 nrf saml2x ' 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' 'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u0 stm32u5 stm32wb stm32wba ' From dd78e2eeb5b4970e05e2ca5e6168befa5e9a2b80 Mon Sep 17 00:00:00 2001 From: gab-k Date: Sun, 14 Dec 2025 01:42:43 +0100 Subject: [PATCH 3/8] Update README --- README.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.rst b/README.rst index 463cc8b42..95943de8e 100644 --- a/README.rst +++ b/README.rst @@ -209,7 +209,7 @@ Supported CPUs | | +-------------------+--------+------+-----------+------------------------+-------------------+ | | | A15 | ✔ | | | ci_fs | | | +---------+-------------------+--------+------+-----------+------------------------+-------------------+ -| | RW61x | ✔ | | ✔ | ci_hs, ehci | | +| | RW61x | ✔ | ✔ | ✔ | ci_hs, ehci | | +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ | Raspberry Pi | RP2040, RP2350 | ✔ | ✔ | ✖ | rp2040, pio_usb | | +--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ From 412f4d306901f6d373213b972191b2decba330a1 Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Tue, 16 Dec 2025 12:14:35 +0100 Subject: [PATCH 4/8] update preset Signed-off-by: Zixun LI --- hw/bsp/BoardPresets.json | 66 ++++++++++++++-------------------------- 1 file changed, 22 insertions(+), 44 deletions(-) diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json index 5df924138..5fbc378d2 100644 --- a/hw/bsp/BoardPresets.json +++ b/hw/bsp/BoardPresets.json @@ -234,6 +234,10 @@ "name": "frdm_mcxn947", "inherits": "default" }, + { + "name": "frdm_rw612", + "inherits": "default" + }, { "name": "itsybitsy_m0", "inherits": "default" @@ -362,10 +366,6 @@ "name": "metro_m7_1011_sd", "inherits": "default" }, - { - "name": "metro_nrf52840", - "inherits": "default" - }, { "name": "mimxrt1010_evk", "inherits": "default" @@ -518,10 +518,6 @@ "name": "raspberry_pi_pico2", "inherits": "default" }, - { - "name": "raspberry_pi_pico2_riscv", - "inherits": "default" - }, { "name": "raspberry_pi_pico_w", "inherits": "default" @@ -1228,6 +1224,11 @@ "description": "Build preset for the frdm_mcxn947 board", "configurePreset": "frdm_mcxn947" }, + { + "name": "frdm_rw612", + "description": "Build preset for the frdm_rw612 board", + "configurePreset": "frdm_rw612" + }, { "name": "itsybitsy_m0", "description": "Build preset for the itsybitsy_m0 board", @@ -1388,11 +1389,6 @@ "description": "Build preset for the metro_m7_1011_sd board", "configurePreset": "metro_m7_1011_sd" }, - { - "name": "metro_nrf52840", - "description": "Build preset for the metro_nrf52840 board", - "configurePreset": "metro_nrf52840" - }, { "name": "mimxrt1010_evk", "description": "Build preset for the mimxrt1010_evk board", @@ -1583,11 +1579,6 @@ "description": "Build preset for the raspberry_pi_pico2 board", "configurePreset": "raspberry_pi_pico2" }, - { - "name": "raspberry_pi_pico2_riscv", - "description": "Build preset for the raspberry_pi_pico2_riscv board", - "configurePreset": "raspberry_pi_pico2_riscv" - }, { "name": "raspberry_pi_pico_w", "description": "Build preset for the raspberry_pi_pico_w board", @@ -2854,6 +2845,19 @@ } ] }, + { + "name": "frdm_rw612", + "steps": [ + { + "type": "configure", + "name": "frdm_rw612" + }, + { + "type": "build", + "name": "frdm_rw612" + } + ] + }, { "name": "itsybitsy_m0", "steps": [ @@ -3270,19 +3274,6 @@ } ] }, - { - "name": "metro_nrf52840", - "steps": [ - { - "type": "configure", - "name": "metro_nrf52840" - }, - { - "type": "build", - "name": "metro_nrf52840" - } - ] - }, { "name": "mimxrt1010_evk", "steps": [ @@ -3777,19 +3768,6 @@ } ] }, - { - "name": "raspberry_pi_pico2_riscv", - "steps": [ - { - "type": "configure", - "name": "raspberry_pi_pico2_riscv" - }, - { - "type": "build", - "name": "raspberry_pi_pico2_riscv" - } - ] - }, { "name": "raspberry_pi_pico_w", "steps": [ From d768735e0cacbd370bf1b8cc023caaef600b7ddc Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Tue, 16 Dec 2025 12:16:55 +0100 Subject: [PATCH 5/8] update ci Signed-off-by: Zixun LI --- .github/workflows/ci_set_matrix.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index 933a8375f..dfe7e7780 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -21,8 +21,8 @@ family_list = { "imxrt": ["arm-gcc", "arm-clang"], "kinetis_k kinetis_kl kinetis_k32l2": ["arm-gcc", "arm-clang"], "lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"], - "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"], - "maxim mcx mm32 msp432e4 tm4c": ["arm-gcc"], + "lpc51 lpc54 lpc55 mcx rw61x": ["arm-gcc", "arm-clang"], + "maxim mm32 msp432e4 tm4c": ["arm-gcc"], "msp430": ["msp430-gcc"], "nrf": ["arm-gcc", "arm-clang"], "nuc100_120 nuc121_125 nuc126 nuc505 xmc4000": ["arm-gcc"], From c130fc07c628a0b2d79f35b743857aa53d79130b Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Tue, 16 Dec 2025 12:29:04 +0100 Subject: [PATCH 6/8] fix pre-commit Signed-off-by: Zixun LI --- hw/bsp/rw61x/boards/frdm_rw612/board.cmake | 2 +- hw/bsp/rw61x/boards/frdm_rw612/board.h | 6 ++---- hw/bsp/rw61x/boards/frdm_rw612/clock_config.c | 1 - hw/bsp/rw61x/boards/frdm_rw612/clock_config.h | 1 - hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c | 2 +- hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h | 2 +- hw/bsp/rw61x/family.c | 6 +++--- hw/bsp/rw61x/family.cmake | 4 ++-- hw/bsp/rw61x/family.mk | 4 ++-- src/tusb_option.h | 2 +- 10 files changed, 13 insertions(+), 17 deletions(-) diff --git a/hw/bsp/rw61x/boards/frdm_rw612/board.cmake b/hw/bsp/rw61x/boards/frdm_rw612/board.cmake index 09feb0cab..7d77956fa 100644 --- a/hw/bsp/rw61x/boards/frdm_rw612/board.cmake +++ b/hw/bsp/rw61x/boards/frdm_rw612/board.cmake @@ -27,4 +27,4 @@ function(update_board BOARD_TARGET) target_include_directories(${BOARD_TARGET} PUBLIC ${BOARD_DIR}/flash_config ) -endfunction() \ No newline at end of file +endfunction() diff --git a/hw/bsp/rw61x/boards/frdm_rw612/board.h b/hw/bsp/rw61x/boards/frdm_rw612/board.h index ebb357c29..fd9eec8b6 100644 --- a/hw/bsp/rw61x/boards/frdm_rw612/board.h +++ b/hw/bsp/rw61x/boards/frdm_rw612/board.h @@ -41,8 +41,8 @@ // LED - Green channel of RGB LED #define LED_GPIO BOARD_INITLEDPINS_LED_GREEN_PERIPHERAL #define LED_CLK kCLOCK_HsGpio0 -#define LED_PIN BOARD_INITLEDPINS_LED_GREEN_PIN -#define LED_PORT BOARD_INITLEDPINS_LED_GREEN_PORT +#define LED_PIN BOARD_INITLEDPINS_LED_GREEN_PIN +#define LED_PORT BOARD_INITLEDPINS_LED_GREEN_PORT #define LED_STATE_ON 0 // WAKE button (Dummy, use unused pin @@ -72,5 +72,3 @@ static inline void board_uart_init_clock(void) { #endif #endif - - diff --git a/hw/bsp/rw61x/boards/frdm_rw612/clock_config.c b/hw/bsp/rw61x/boards/frdm_rw612/clock_config.c index 513e40f66..9ad78fe43 100644 --- a/hw/bsp/rw61x/boards/frdm_rw612/clock_config.c +++ b/hw/bsp/rw61x/boards/frdm_rw612/clock_config.c @@ -167,4 +167,3 @@ void BOARD_BootClockRUN(void) /*!< Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_HCLK; } - diff --git a/hw/bsp/rw61x/boards/frdm_rw612/clock_config.h b/hw/bsp/rw61x/boards/frdm_rw612/clock_config.h index 3b467d869..57e3bbb4d 100644 --- a/hw/bsp/rw61x/boards/frdm_rw612/clock_config.h +++ b/hw/bsp/rw61x/boards/frdm_rw612/clock_config.h @@ -113,4 +113,3 @@ void BOARD_BootClockRUN(void); #endif /* _CLOCK_CONFIG_H_ */ - diff --git a/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c index 49b74b2bb..eba6b4123 100644 --- a/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c +++ b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c @@ -53,7 +53,7 @@ BOARD_InitPins: /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitPins - * Description : + * Description : * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ diff --git a/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h index f4c9a9127..c43b304d5 100644 --- a/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h +++ b/hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h @@ -54,7 +54,7 @@ void BOARD_InitBootPins(void); /* @} */ /*! - * @brief + * @brief * */ void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ diff --git a/hw/bsp/rw61x/family.c b/hw/bsp/rw61x/family.c index 226956f15..265d5fcc0 100644 --- a/hw/bsp/rw61x/family.c +++ b/hw/bsp/rw61x/family.c @@ -51,7 +51,7 @@ void board_init(void) { // Init button pin, LED pins, SWD pins & UART pins BOARD_InitBootPins(); - + // Init Clocks BOARD_InitBootClocks(); @@ -86,8 +86,8 @@ void board_init(void) { // Enable USB Clock CLOCK_EnableClock(kCLOCK_Usb); - - // Enable USB PHY + + // Enable USB PHY CLOCK_EnableUsbhsPhyClock(); } diff --git a/hw/bsp/rw61x/family.cmake b/hw/bsp/rw61x/family.cmake index 5428b7e50..62233a404 100644 --- a/hw/bsp/rw61x/family.cmake +++ b/hw/bsp/rw61x/family.cmake @@ -81,7 +81,7 @@ function(family_configure_example TARGET RTOS) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - --specs=nosys.specs + --specs=nosys.specs --specs=nano.specs ) endif() @@ -99,4 +99,4 @@ function(family_configure_example TARGET RTOS) # Flashing & Binary Generation family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) -endfunction() \ No newline at end of file +endfunction() diff --git a/hw/bsp/rw61x/family.mk b/hw/bsp/rw61x/family.mk index e715adfa8..08eafddbc 100644 --- a/hw/bsp/rw61x/family.mk +++ b/hw/bsp/rw61x/family.mk @@ -13,7 +13,7 @@ CFLAGS += \ -DSERIAL_PORT_TYPE_UART=1 \ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED \ -DBOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED \ - + # mcu driver cause following warnings CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls @@ -35,7 +35,7 @@ SRC_C += \ $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ $(SDK_DIR)/drivers/flexspi/fsl_flexspi.c \ - + INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ diff --git a/src/tusb_option.h b/src/tusb_option.h index 413bf2a82..caf8c4156 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -199,7 +199,7 @@ // NXP LPC MCX #define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series #define OPT_MCU_MCXA15 2301 ///< NXP MCX A15 Series -#define OPT_MCU_RW61X 2302 ///< NXP RW61x Series +#define OPT_MCU_RW61X 2302 ///< NXP RW61x Series // Analog Devices #define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 From cb1873881e3cc51f522978e165748ad7ef7a7b0a Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Tue, 16 Dec 2025 12:40:44 +0100 Subject: [PATCH 7/8] fix build Signed-off-by: Zixun LI --- hw/bsp/rw61x/family.cmake | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/bsp/rw61x/family.cmake b/hw/bsp/rw61x/family.cmake index 62233a404..8c332f96e 100644 --- a/hw/bsp/rw61x/family.cmake +++ b/hw/bsp/rw61x/family.cmake @@ -81,10 +81,18 @@ function(family_configure_example TARGET RTOS) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - --specs=nosys.specs - --specs=nano.specs + --specs=nosys.specs --specs=nano.specs + -nostartfiles ) - endif() + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes") From ce7b15d6f94b1f8efe917f40eb61b8c3a703d0f8 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 16 Dec 2025 21:11:13 +0100 Subject: [PATCH 8/8] more fixes Signed-off-by: HiFiPhile --- .github/workflows/ci_set_matrix.py | 4 ++-- README.rst | 4 ++-- hw/bsp/rw61x/family.cmake | 1 - hw/bsp/stm32h5/family.mk | 1 + 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index b682da1a2..c276d5253 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -21,8 +21,8 @@ family_list = { "imxrt": ["arm-gcc", "arm-clang"], "kinetis_k kinetis_kl kinetis_k32l2": ["arm-gcc", "arm-clang"], "lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"], - "lpc51 lpc54 lpc55 mcx rw61x": ["arm-gcc", "arm-clang"], - "maxim mm32 msp432e4 tm4c": ["arm-gcc"], + "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"], + "maxim mcx mm32 msp432e4 rw61x tm4c": ["arm-gcc"], "msp430": ["msp430-gcc"], "nrf": ["arm-gcc", "arm-clang"], "nuc100_120 nuc121_125 nuc126 nuc505 xmc4000": ["arm-gcc"], diff --git a/README.rst b/README.rst index 58a9e393e..178a084ce 100644 --- a/README.rst +++ b/README.rst @@ -209,8 +209,8 @@ Supported CPUs | | +-------------------+--------+------+-----------+------------------------+--------------------+ | | | A15 | ✔ | | | ci_fs | | | +---------+-------------------+--------+------+-----------+------------------------+--------------------+ -| | RW61x | ✔ | ✔ | ✔ | ci_hs, ehci | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | RW61x | ✔ | ✔ | ✔ | ci_hs, ehci | | ++--------------+-----------------------------+--------+------+-----------+------------------------+--------------------+ | Raspberry Pi | RP2040, RP2350 | ✔ | ✔ | ✖ | rp2040, pio_usb | | +--------------+-----+-----------------------+--------+------+-----------+------------------------+--------------------+ | Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | rusb2 | | diff --git a/hw/bsp/rw61x/family.cmake b/hw/bsp/rw61x/family.cmake index 8c332f96e..6782e87e3 100644 --- a/hw/bsp/rw61x/family.cmake +++ b/hw/bsp/rw61x/family.cmake @@ -82,7 +82,6 @@ function(family_configure_example TARGET RTOS) target_link_options(${TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs - -nostartfiles ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC diff --git a/hw/bsp/stm32h5/family.mk b/hw/bsp/stm32h5/family.mk index 89a2eddd5..e34bb513e 100644 --- a/hw/bsp/stm32h5/family.mk +++ b/hw/bsp/stm32h5/family.mk @@ -49,6 +49,7 @@ SRC_C += \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_i2c.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c INC += \