diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 32f6827b0..f19c4a327 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -828,7 +828,9 @@ static bool set_line_state_on_enum(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) {
     ENUM_SET_LINE_CONTROL,
     ENUM_SET_LINE_COMPLETE,
   };
+  #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
   const uint8_t idx = get_idx_by_ptr(p_cdc);
+  #endif
   const uintptr_t state = xfer->user_data;
 
   switch (state) {
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 55f7e0b7c..ebe486e40 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -245,13 +245,12 @@
   #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
-  #include "stm32h7xx.h"
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
 
   #define TUP_DCD_ENDPOINT_MAX 9
 
-  #if __CORTEX_M == 7
+  #ifndef CORE_CM4
     // Enable dcache if DMA is enabled
     #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
     #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE