8444c25ab6
replace board_millis() with tusb_time_millis_api()
2026-02-28 00:01:40 +07:00
a42184b6fe
remove legacy DEPS_SUBMODULES in make
2025-07-02 11:03:50 +07:00
6a36c74b10
embed metadata to family.c and board.h to generate supported boards doc
2024-12-27 09:11:09 +07:00
01df8c36de
fix ci
2024-11-21 22:03:52 +07:00
27fc8a21cd
update gr_citrus as well
2024-04-09 17:07:59 +07:00
2828a56a4f
apply oldPRCR to board_init()
2024-04-09 17:05:25 +07:00
82880eecbd
make nanolib linking explicitly by each family/board
2023-11-23 12:43:13 +07:00
3b0ffd0f48
change hcd_int_handler(rhport, in_isr) signature: add in_isr
...
change tuh_int_handler() to take in_isr as optional parameter (default =
true)
2023-09-27 15:51:03 +07:00
a5768f52b4
more board_api.h rename
2023-08-03 15:50:52 +07:00
3623ba1884
fix trailing space and new line
...
temporarily disable codespell
2023-03-17 16:12:49 +07:00
ffdffc7e06
rename FREERTOS_PORT to FREERTOS_PORTABLE_SRC
...
also fix trailing spaces
2023-03-16 23:11:11 +07:00
bc2127b330
rename file link to rusb2
2023-03-16 11:03:53 +07:00
fe77976765
Merge branch 'master' into renesas-ra
2023-03-11 08:15:23 +07:00
206a9a21e6
fix ci
2023-03-10 23:54:30 +07:00
05e0205ad0
Merge branch 'master' into renesas-ra
2023-03-08 21:05:06 +07:00
4f6e770eda
add more warning option, also fix -Wconversion with rp2040
...
-Wuninitialized, -Wunused, -Wredundant-decls
2022-06-24 19:46:19 +07:00
2a17a7e8f8
rework make freertos port handling
...
this allows ports to specify a freertos port outside the FreeRTOS-Kernel lib directory, which would otherwise not be possible
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt >
2022-06-02 09:35:30 +01:00
03777f4a46
generalize renesas LINK core driver
...
create local register access struct and move mcu specific code
in preparation of support for other mcu families that use the LINK usb core
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt >
2022-06-02 09:35:30 +01:00
dcadbf3364
rename renesas driver to link
...
link was chosen according to the name for the usb core on datasheets, LINK core
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt >
2022-06-02 09:35:30 +01:00
31aa077cb0
rename TUSB_OPT_HOST_ENABLED to CFG_TUH_ENABLED
2022-02-25 18:35:21 +07:00
d10326cb4e
rename TUSB_OPT_DEVICE_ENABLED to CFG_TUD_ENABLED
...
TUSB_OPT_DEVICE_ENABLED still usable for backward compatible
2022-02-25 18:35:21 +07:00
a750c9c902
Increase stack size
2021-12-27 21:28:46 +09:00
a76799b085
Add hcd for Renesas RX
2021-12-27 21:19:02 +09:00
a5f516893b
more with -Wcast-qual
2021-10-17 16:36:53 +07:00
ea9ec1fb43
extend stack areas to enable logging
...
add dummy functions to avoid warnings when logging is enable
remove codes regarding OPTLIB
2021-07-02 11:37:23 +09:00
b2fa7358cf
fix typo
2021-06-29 16:38:38 +07:00
2d423514ee
rename rx65n cloud kit to target
...
adding note for adding jlink support for rx65n_target board
2021-06-29 16:33:32 +07:00
856dc0bab9
update doc and clean up
2021-06-28 12:59:53 +07:00
e3b1110cce
rename rx63n to simply rx
2021-06-28 12:51:11 +07:00
