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H5 hangs its debug AP if trace CoreSight is touched unclocked (recover = power-cycle): the reference's AfterTargetConnect clocks the DBGMCU trace domain but defers IOEN to firmware, or the mid-boot clock switch desyncs the decoder. Stock solder bridges make the CN5 path marginal: validated config is 100 MHz core, width 1, +5 ns (board.h selects the reduced clock for TRACE_ETM builds); width 4 / 250 MHz retest waits on SB removal.