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J403 (bottom-side Cortex Debug+ETM footprint, header required): TRACECLK=PD8 peripheral D, TRACED0-3=PD4-7 peripheral C. TRACE_ETM builds hold the KSZ8081 PHY in reset (PD4-7 are its RMII receive outputs and it drives against the trace stream), clock the TPIU from PCK3 (MCK/2) and mux the pins; the ozone reference starts PCK3 in the post-reset/download hooks - TPIU programming while PCK3 is stopped is silently lost. Width-1 validated at the stock 300 MHz core; width 4 blocked on a dead D1 line (suspect probe channel, h743eval crosscheck pending).