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Second stage: the USBSS SuperSpeed device driver (SPEED=super now links). The LINK layer is the same IP as the CH569 but the endpoint engine is the H417's reworked chain-DMA design (hardware SEQ_AUTO/ERDY_AUTO, persistent RB_EP_*_HALT, per-chain completion). The RCC/PHY/LINK bring-up and EP0 control sequences are transcribed from the WCH EVT USBSS device demo; data endpoints arm one chain per packet (burst 1) for correctness-first bring-up, matching the CH569 port's initial path - raise CFG_TUD_WCH_USB30_MAX_BURST once the hardware validates. Buffers may live anywhere in the shared SRAM (all DMA-reachable), so no bounce machinery is needed. - src/portable/wch/dcd_ch32h417_usb30.c (+ ch32h417_usb30_reg.h): full dcd with a STATE_CHG-driven LTSSM handler, LMP PORT_CAP/PORT_CFG exchange, EP0 DPH/ERDY flow with software sequence, chain-armed data endpoints, per-EP HALT stall, and a TIM12-backstopped runtime USB2 fallback that hands rhport 0 to ch32h417_usb2_* when SuperSpeed training fails (host has no SS port). - examples/device/*/skip.txt: add mcu:CH32H417 to the FreeRTOS + audio/video examples (no FreeRTOSConfig for this family yet), mirroring mcu:CH569. Build-verified: all 20 device examples build for SPEED=super, and cdc_msc for SPEED=high, clean under -Werror (riscv-none-elf-gcc 13.2). Hardware bring-up at 5 Gbps (usbtest battery, throughput) is pending rig availability. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm