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Merge tag 'v6.1.0' into merge/qemu-v6.1.0

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v6.1.0 release
This commit is contained in:
Matt Borgerson
2021-09-04 15:11:03 -07:00
parent 3c1fcf6202 f9baca549e
commit 0e63232072
2555 changed files with 125585 additions and 89914 deletions
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52
include/block/aio.h
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@ -232,6 +232,9 @@ struct AioContext {
int64_t poll_grow; /* polling time growth factor */
int64_t poll_shrink; /* polling time shrink factor */
/* AIO engine parameters */
int64_t aio_max_batch; /* maximum number of requests in a batch */
/*
* List of handlers participating in userspace polling. Protected by
* ctx->list_lock. Iterated and modified mostly by the event loop thread
@ -292,19 +295,44 @@ void aio_context_acquire(AioContext *ctx);
void aio_context_release(AioContext *ctx);
/**
* aio_bh_schedule_oneshot: Allocate a new bottom half structure that will run
* only once and as soon as possible.
* aio_bh_schedule_oneshot_full: Allocate a new bottom half structure that will
* run only once and as soon as possible.
*
* @name: A human-readable identifier for debugging purposes.
*/
void aio_bh_schedule_oneshot(AioContext *ctx, QEMUBHFunc *cb, void *opaque);
void aio_bh_schedule_oneshot_full(AioContext *ctx, QEMUBHFunc *cb, void *opaque,
const char *name);
/**
* aio_bh_new: Allocate a new bottom half structure.
* aio_bh_schedule_oneshot: Allocate a new bottom half structure that will run
* only once and as soon as possible.
*
* A convenience wrapper for aio_bh_schedule_oneshot_full() that uses cb as the
* name string.
*/
#define aio_bh_schedule_oneshot(ctx, cb, opaque) \
aio_bh_schedule_oneshot_full((ctx), (cb), (opaque), (stringify(cb)))
/**
* aio_bh_new_full: Allocate a new bottom half structure.
*
* Bottom halves are lightweight callbacks whose invocation is guaranteed
* to be wait-free, thread-safe and signal-safe. The #QEMUBH structure
* is opaque and must be allocated prior to its use.
*
* @name: A human-readable identifier for debugging purposes.
*/
QEMUBH *aio_bh_new(AioContext *ctx, QEMUBHFunc *cb, void *opaque);
QEMUBH *aio_bh_new_full(AioContext *ctx, QEMUBHFunc *cb, void *opaque,
const char *name);
/**
* aio_bh_new: Allocate a new bottom half structure
*
* A convenience wrapper for aio_bh_new_full() that uses the cb as the name
* string.
*/
#define aio_bh_new(ctx, cb, opaque) \
aio_bh_new_full((ctx), (cb), (opaque), (stringify(cb)))
/**
* aio_notify: Force processing of pending events.
@ -691,10 +719,13 @@ void aio_co_enter(AioContext *ctx, struct Coroutine *co);
* Return the AioContext whose event loop runs in the current thread.
*
* If called from an IOThread this will be the IOThread's AioContext. If
* called from another thread it will be the main loop AioContext.
* called from the main thread or with the "big QEMU lock" taken it
* will be the main loop AioContext.
*/
AioContext *qemu_get_current_aio_context(void);
void qemu_set_current_aio_context(AioContext *ctx);
/**
* aio_context_setup:
* @ctx: the aio context
@ -727,4 +758,13 @@ void aio_context_set_poll_params(AioContext *ctx, int64_t max_ns,
int64_t grow, int64_t shrink,
Error **errp);
/**
* aio_context_set_aio_params:
* @ctx: the aio context
* @max_batch: maximum number of requests in a batch, 0 means that the
* engine will use its default
*/
void aio_context_set_aio_params(AioContext *ctx, int64_t max_batch,
Error **errp);
#endif

2
include/block/block-copy.h
View File

@ -18,6 +18,8 @@
#include "block/block.h"
#include "qemu/co-shared-resource.h"
/* All APIs are thread-safe */
typedef void (*BlockCopyAsyncCallbackFunc)(void *opaque);
typedef struct BlockCopyState BlockCopyState;
typedef struct BlockCopyCallState BlockCopyCallState;

20
include/block/block.h
View File

@ -9,6 +9,7 @@
#include "block/dirty-bitmap.h"
#include "block/blockjob.h"
#include "qemu/hbitmap.h"
#include "qemu/transactions.h"
/*
* generated_co_wrapper
@ -101,6 +102,7 @@ typedef struct HDGeometry {
uint32_t cylinders;
} HDGeometry;
#define BDRV_O_NO_SHARE 0x0001 /* don't share permissions */
#define BDRV_O_RDWR 0x0002
#define BDRV_O_RESIZE 0x0004 /* request permission for resizing the node */
#define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
@ -206,9 +208,8 @@ typedef struct BDRVReopenState {
int flags;
BlockdevDetectZeroesOptions detect_zeroes;
bool backing_missing;
bool replace_backing_bs; /* new_backing_bs is ignored if this is false */
BlockDriverState *new_backing_bs; /* If NULL then detach the current bs */
uint64_t perm, shared_perm;
BlockDriverState *old_backing_bs; /* keep pointer for permissions update */
BlockDriverState *old_file_bs; /* keep pointer for permissions update */
QDict *options;
QDict *explicit_options;
void *opaque;
@ -362,6 +363,7 @@ int bdrv_replace_node(BlockDriverState *from, BlockDriverState *to,
Error **errp);
BlockDriverState *bdrv_insert_node(BlockDriverState *bs, QDict *node_options,
int flags, Error **errp);
int bdrv_drop_filter(BlockDriverState *bs, Error **errp);
int bdrv_parse_aio(const char *mode, int *flags);
int bdrv_parse_cache_mode(const char *mode, int *flags, bool *writethrough);
@ -384,13 +386,12 @@ BlockDriverState *bdrv_new_open_driver(BlockDriver *drv, const char *node_name,
BlockReopenQueue *bdrv_reopen_queue(BlockReopenQueue *bs_queue,
BlockDriverState *bs, QDict *options,
bool keep_old_opts);
void bdrv_reopen_queue_free(BlockReopenQueue *bs_queue);
int bdrv_reopen_multiple(BlockReopenQueue *bs_queue, Error **errp);
int bdrv_reopen(BlockDriverState *bs, QDict *opts, bool keep_old_opts,
Error **errp);
int bdrv_reopen_set_read_only(BlockDriverState *bs, bool read_only,
Error **errp);
int bdrv_reopen_prepare(BDRVReopenState *reopen_state,
BlockReopenQueue *queue, Error **errp);
void bdrv_reopen_commit(BDRVReopenState *reopen_state);
void bdrv_reopen_abort(BDRVReopenState *reopen_state);
int bdrv_pwrite_zeroes(BdrvChild *child, int64_t offset,
int64_t bytes, BdrvRequestFlags flags);
int bdrv_make_zero(BdrvChild *child, BdrvRequestFlags flags);
@ -424,7 +425,7 @@ int64_t bdrv_get_allocated_file_size(BlockDriverState *bs);
BlockMeasureInfo *bdrv_measure(BlockDriver *drv, QemuOpts *opts,
BlockDriverState *in_bs, Error **errp);
void bdrv_get_geometry(BlockDriverState *bs, uint64_t *nb_sectors_ptr);
void bdrv_refresh_limits(BlockDriverState *bs, Error **errp);
void bdrv_refresh_limits(BlockDriverState *bs, Transaction *tran, Error **errp);
int bdrv_commit(BlockDriverState *bs);
int bdrv_make_empty(BdrvChild *c, Error **errp);
int bdrv_change_backing_file(BlockDriverState *bs, const char *backing_file,
@ -702,6 +703,9 @@ bool bdrv_child_can_set_aio_context(BdrvChild *c, AioContext *ctx,
GSList **ignore, Error **errp);
bool bdrv_can_set_aio_context(BlockDriverState *bs, AioContext *ctx,
GSList **ignore, Error **errp);
AioContext *bdrv_child_get_parent_aio_context(BdrvChild *c);
AioContext *child_of_bds_get_parent_aio_context(BdrvChild *c);
int bdrv_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz);
int bdrv_probe_geometry(BlockDriverState *bs, HDGeometry *geo);

32
include/block/block_int.h
View File

@ -357,7 +357,7 @@ struct BlockDriver {
* of in-flight requests, so don't waste the time if possible.
*
* One example usage is to avoid waiting for an nbd target node reconnect
* timeout during job-cancel.
* timeout during job-cancel with force=true.
*/
void (*bdrv_cancel_in_flight)(BlockDriverState *bs);
@ -695,6 +695,13 @@ typedef struct BlockLimits {
* clamped down. */
uint32_t max_transfer;
/* Maximal hardware transfer length in bytes. Applies whenever
* transfers to the device bypass the kernel I/O scheduler, for
* example with SG_IO. If larger than max_transfer or if zero,
* blk_get_max_hw_transfer will fall back to max_transfer.
*/
uint64_t max_hw_transfer;
/* memory alignment, in bytes so that no bounce buffer is needed */
size_t min_mem_alignment;
@ -789,6 +796,8 @@ struct BdrvChildClass {
bool (*can_set_aio_ctx)(BdrvChild *child, AioContext *ctx,
GSList **ignore, Error **errp);
void (*set_aio_ctx)(BdrvChild *child, AioContext *ctx, GSList **ignore);
AioContext *(*get_parent_aio_context)(BdrvChild *child);
};
extern const BdrvChildClass child_of_bds;
@ -811,11 +820,6 @@ struct BdrvChild {
*/
uint64_t shared_perm;
/* backup of permissions during permission update procedure */
bool has_backup_perm;
uint64_t backup_perm;
uint64_t backup_shared_perm;
/*
* This link is frozen: the child can neither be replaced nor
* detached from the parent.
@ -846,7 +850,6 @@ struct BlockDriverState {
* locking needed during I/O...
*/
int open_flags; /* flags used to open the file, re-used for re-open */
bool read_only; /* if true, the media is read only */
bool encrypted; /* if true, the media is encrypted */
bool sg; /* if true, the device is a /dev/sg* */
bool probed; /* if true, format was probed rather than specified */
@ -957,12 +960,8 @@ struct BlockDriverState {
*/
int64_t total_sectors;
/* Callback before write request is processed */
NotifierWithReturnList before_write_notifiers;
/* threshold limit for writes, in bytes. "High water mark". */
uint64_t write_threshold_offset;
NotifierWithReturn write_threshold_notifier;
/* Writing to the list requires the BQL _and_ the dirty_bitmap_mutex.
* Reading from the list can be done with either the BQL or the
@ -1015,7 +1014,6 @@ struct BlockDriverState {
struct BlockBackendRootState {
int open_flags;
bool read_only;
BlockdevDetectZeroesOptions detect_zeroes;
};
@ -1087,15 +1085,6 @@ void bdrv_parse_filename_strip_prefix(const char *filename, const char *prefix,
bool bdrv_backing_overridden(BlockDriverState *bs);
/**
* bdrv_add_before_write_notifier:
*
* Register a callback that is invoked before write requests are processed but
* after any throttling or waiting for overlapping requests.
*/
void bdrv_add_before_write_notifier(BlockDriverState *bs,
NotifierWithReturn *notifier);
/**
* bdrv_add_aio_context_notifier:
*
@ -1306,7 +1295,6 @@ BdrvChild *bdrv_root_attach_child(BlockDriverState *child_bs,
const char *child_name,
const BdrvChildClass *child_class,
BdrvChildRole child_role,
AioContext *ctx,
uint64_t perm, uint64_t shared_perm,
void *opaque, Error **errp);
void bdrv_root_unref_child(BdrvChild *child);

18
include/block/nbd.h
View File

@ -406,4 +406,22 @@ const char *nbd_info_lookup(uint16_t info);
const char *nbd_cmd_lookup(uint16_t info);
const char *nbd_err_lookup(int err);
/* nbd/client-connection.c */
typedef struct NBDClientConnection NBDClientConnection;
void nbd_client_connection_enable_retry(NBDClientConnection *conn);
NBDClientConnection *nbd_client_connection_new(const SocketAddress *saddr,
bool do_negotiation,
const char *export_name,
const char *x_dirty_bitmap,
QCryptoTLSCreds *tlscreds);
void nbd_client_connection_release(NBDClientConnection *conn);
QIOChannel *coroutine_fn
nbd_co_establish_connection(NBDClientConnection *conn, NBDExportInfo *info,
bool blocking, Error **errp);
void coroutine_fn nbd_co_establish_connection_cancel(NBDClientConnection *conn);
#endif

90
include/block/nvme.h
View File

@ -7,9 +7,9 @@ typedef struct QEMU_PACKED NvmeBar {
uint32_t intms;
uint32_t intmc;
uint32_t cc;
uint32_t rsvd1;
uint8_t rsvd24[4];
uint32_t csts;
uint32_t nssrc;
uint32_t nssr;
uint32_t aqa;
uint64_t asq;
uint64_t acq;
@ -26,10 +26,38 @@ typedef struct QEMU_PACKED NvmeBar {
uint32_t pmrsts;
uint32_t pmrebs;
uint32_t pmrswtp;
uint64_t pmrmsc;
uint32_t pmrmscl;
uint32_t pmrmscu;
uint8_t css[484];
} NvmeBar;
enum NvmeBarRegs {
NVME_REG_CAP = offsetof(NvmeBar, cap),
NVME_REG_VS = offsetof(NvmeBar, vs),
NVME_REG_INTMS = offsetof(NvmeBar, intms),
NVME_REG_INTMC = offsetof(NvmeBar, intmc),
NVME_REG_CC = offsetof(NvmeBar, cc),
NVME_REG_CSTS = offsetof(NvmeBar, csts),
NVME_REG_NSSR = offsetof(NvmeBar, nssr),
NVME_REG_AQA = offsetof(NvmeBar, aqa),
NVME_REG_ASQ = offsetof(NvmeBar, asq),
NVME_REG_ACQ = offsetof(NvmeBar, acq),
NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc),
NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz),
NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo),
NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel),
NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl),
NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc),
NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts),
NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap),
NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl),
NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts),
NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs),
NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp),
NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl),
NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu),
};
enum NvmeCapShift {
CAP_MQES_SHIFT = 0,
CAP_CQR_SHIFT = 16,
@ -475,25 +503,25 @@ enum NvmePmrswtpMask {
#define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \
(pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT)
enum NvmePmrmscShift {
PMRMSC_CMSE_SHIFT = 1,
PMRMSC_CBA_SHIFT = 12,
enum NvmePmrmsclShift {
PMRMSCL_CMSE_SHIFT = 1,
PMRMSCL_CBA_SHIFT = 12,
};
enum NvmePmrmscMask {
PMRMSC_CMSE_MASK = 0x1,
PMRMSC_CBA_MASK = 0xfffffffffffff,
enum NvmePmrmsclMask {
PMRMSCL_CMSE_MASK = 0x1,
PMRMSCL_CBA_MASK = 0xfffff,
};
#define NVME_PMRMSC_CMSE(pmrmsc) \
((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK)
#define NVME_PMRMSC_CBA(pmrmsc) \
((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK)
#define NVME_PMRMSCL_CMSE(pmrmscl) \
((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK)
#define NVME_PMRMSCL_CBA(pmrmscl) \
((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK)
#define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \
(pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT)
#define NVME_PMRMSC_SET_CBA(pmrmsc, val) \
(pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT)
#define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \
(pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT)
#define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \
(pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT)
enum NvmeSglDescriptorType {
NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0,
@ -708,6 +736,14 @@ enum {
#define NVME_RW_PRINFO(control) ((control >> 10) & 0xf)
enum {
NVME_PRINFO_PRACT = 1 << 3,
NVME_PRINFO_PRCHK_GUARD = 1 << 2,
NVME_PRINFO_PRCHK_APP = 1 << 1,
NVME_PRINFO_PRCHK_REF = 1 << 0,
NVME_PRINFO_PRCHK_MASK = 7 << 0,
};
typedef struct QEMU_PACKED NvmeDsmCmd {
uint8_t opcode;
uint8_t flags;
@ -848,8 +884,8 @@ enum NvmeStatusCodes {
NVME_FW_REQ_SUSYSTEM_RESET = 0x0110,
NVME_NS_ALREADY_ATTACHED = 0x0118,
NVME_NS_PRIVATE = 0x0119,
NVME_NS_NOT_ATTACHED = 0x011A,
NVME_NS_CTRL_LIST_INVALID = 0x011C,
NVME_NS_NOT_ATTACHED = 0x011a,
NVME_NS_CTRL_LIST_INVALID = 0x011c,
NVME_CONFLICTING_ATTRS = 0x0180,
NVME_INVALID_PROT_INFO = 0x0181,
NVME_WRITE_TO_RO = 0x0182,
@ -980,6 +1016,7 @@ enum NvmeIdCns {
NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
NVME_ID_CNS_NS_PRESENT = 0x11,
NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12,
NVME_ID_CNS_CTRL_LIST = 0x13,
NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a,
NVME_ID_CNS_CS_NS_PRESENT = 0x1b,
NVME_ID_CNS_IO_COMMAND_SET = 0x1c,
@ -1341,6 +1378,15 @@ enum NvmeIdNsDps {
NVME_ID_NS_DPS_FIRST_EIGHT = 8,
};
enum NvmeIdNsFlbas {
NVME_ID_NS_FLBAS_EXTENDED = 1 << 4,
};
enum NvmeIdNsMc {
NVME_ID_NS_MC_EXTENDED = 1 << 0,
NVME_ID_NS_MC_SEPARATE = 1 << 1,
};
#define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK)
typedef struct NvmeDifTuple {
@ -1409,9 +1455,9 @@ typedef enum NvmeZoneState {
NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02,
NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03,
NVME_ZONE_STATE_CLOSED = 0x04,
NVME_ZONE_STATE_READ_ONLY = 0x0D,
NVME_ZONE_STATE_FULL = 0x0E,
NVME_ZONE_STATE_OFFLINE = 0x0F,
NVME_ZONE_STATE_READ_ONLY = 0x0d,
NVME_ZONE_STATE_FULL = 0x0e,
NVME_ZONE_STATE_OFFLINE = 0x0f,
} NvmeZoneState;
static inline void _nvme_check_size(void)

2
include/block/qdict.h
View File

@ -20,8 +20,6 @@ void qdict_join(QDict *dest, QDict *src, bool overwrite);
void qdict_extract_subqdict(QDict *src, QDict **dst, const char *start);
void qdict_array_split(QDict *src, QList **dst);
int qdict_array_entries(QDict *src, const char *subqdict);
QObject *qdict_crumple(const QDict *src, Error **errp);
void qdict_flatten(QDict *qdict);
typedef struct QDictRenames {
const char *from;

175
include/block/replication.h Normal file
View File

@ -0,0 +1,175 @@
/*
* Replication filter
*
* Copyright (c) 2016 HUAWEI TECHNOLOGIES CO., LTD.
* Copyright (c) 2016 Intel Corporation
* Copyright (c) 2016 FUJITSU LIMITED
*
* Author:
* Changlong Xie <xiecl.fnst@cn.fujitsu.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef REPLICATION_H
#define REPLICATION_H
#include "qapi/qapi-types-block-core.h"
#include "qemu/module.h"
#include "qemu/queue.h"
typedef struct ReplicationOps ReplicationOps;
typedef struct ReplicationState ReplicationState;
/**
* SECTION:block/replication.h
* @title:Base Replication System
* @short_description: interfaces for handling replication
*
* The Replication Model provides a framework for handling Replication
*
* <example>
* <title>How to use replication interfaces</title>
* <programlisting>
* #include "block/replication.h"
*
* typedef struct BDRVReplicationState {
* ReplicationState *rs;
* } BDRVReplicationState;
*
* static void replication_start(ReplicationState *rs, ReplicationMode mode,
* Error **errp);
* static void replication_do_checkpoint(ReplicationState *rs, Error **errp);
* static void replication_get_error(ReplicationState *rs, Error **errp);
* static void replication_stop(ReplicationState *rs, bool failover,
* Error **errp);
*
* static ReplicationOps replication_ops = {
* .start = replication_start,
* .checkpoint = replication_do_checkpoint,
* .get_error = replication_get_error,
* .stop = replication_stop,
* }
*
* static int replication_open(BlockDriverState *bs, QDict *options,
* int flags, Error **errp)
* {
* BDRVReplicationState *s = bs->opaque;
* s->rs = replication_new(bs, &replication_ops);
* return 0;
* }
*
* static void replication_close(BlockDriverState *bs)
* {
* BDRVReplicationState *s = bs->opaque;
* replication_remove(s->rs);
* }
*
* BlockDriver bdrv_replication = {
* .format_name = "replication",
* .instance_size = sizeof(BDRVReplicationState),
*
* .bdrv_open = replication_open,
* .bdrv_close = replication_close,
* };
*
* static void bdrv_replication_init(void)
* {
* bdrv_register(&bdrv_replication);
* }
*
* block_init(bdrv_replication_init);
* </programlisting>
* </example>
*
* We create an example about how to use replication interfaces in above.
* Then in migration, we can use replication_(start/stop/do_checkpoint/
* get_error)_all to handle all replication operations.
*/
/**
* ReplicationState:
* @opaque: opaque pointer value passed to this ReplicationState
* @ops: replication operation of this ReplicationState
* @node: node that we will insert into @replication_states QLIST
*/
struct ReplicationState {
void *opaque;
ReplicationOps *ops;
QLIST_ENTRY(ReplicationState) node;
};
/**
* ReplicationOps:
* @start: callback to start replication
* @stop: callback to stop replication
* @checkpoint: callback to do checkpoint
* @get_error: callback to check if error occurred during replication
*/
struct ReplicationOps {
void (*start)(ReplicationState *rs, ReplicationMode mode, Error **errp);
void (*stop)(ReplicationState *rs, bool failover, Error **errp);
void (*checkpoint)(ReplicationState *rs, Error **errp);
void (*get_error)(ReplicationState *rs, Error **errp);
};
/**
* replication_new:
* @opaque: opaque pointer value passed to ReplicationState
* @ops: replication operation of the new relevant ReplicationState
*
* Called to create a new ReplicationState instance, and then insert it
* into @replication_states QLIST
*
* Returns: the new ReplicationState instance
*/
ReplicationState *replication_new(void *opaque, ReplicationOps *ops);
/**
* replication_remove:
* @rs: the ReplicationState instance to remove
*
* Called to remove a ReplicationState instance, and then delete it from
* @replication_states QLIST
*/
void replication_remove(ReplicationState *rs);
/**
* replication_start_all:
* @mode: replication mode that could be "primary" or "secondary"
* @errp: returns an error if this function fails
*
* Start replication, called in migration/checkpoint thread
*
* Note: the caller of the function MUST make sure vm stopped
*/
void replication_start_all(ReplicationMode mode, Error **errp);
/**
* replication_do_checkpoint_all:
* @errp: returns an error if this function fails
*
* This interface is called after all VM state is transferred to Secondary QEMU
*/
void replication_do_checkpoint_all(Error **errp);
/**
* replication_get_error_all:
* @errp: returns an error if this function fails
*
* This interface is called to check if error occurred during replication
*/
void replication_get_error_all(Error **errp);
/**
* replication_stop_all:
* @failover: boolean value that indicates if we need do failover or not
* @errp: returns an error if this function fails
*
* It is called on failover. The vm should be stopped before calling it, if you
* use this API to shutdown the guest, or other things except failover
*/
void replication_stop_all(bool failover, Error **errp);
#endif /* REPLICATION_H */

27
include/block/write-threshold.h
View File

@ -13,7 +13,7 @@
#ifndef BLOCK_WRITE_THRESHOLD_H
#define BLOCK_WRITE_THRESHOLD_H
#include "block/block_int.h"
#include "qemu/typedefs.h"
/*
* bdrv_write_threshold_set:
@ -36,27 +36,12 @@ void bdrv_write_threshold_set(BlockDriverState *bs, uint64_t threshold_bytes);
uint64_t bdrv_write_threshold_get(const BlockDriverState *bs);
/*
* bdrv_write_threshold_is_set
* bdrv_write_threshold_check_write
*
* Tell if a write threshold is set for a given BDS.
* Check whether the specified request exceeds the write threshold.
* If so, send a corresponding event and disable write threshold checking.
*/
bool bdrv_write_threshold_is_set(const BlockDriverState *bs);
/*
* bdrv_write_threshold_exceeded
*
* Return the extent of a write request that exceeded the threshold,
* or zero if the request is below the threshold.
* Return zero also if the threshold was not set.
*
* NOTE: here we assume the following holds for each request this code
* deals with:
*
* assert((req->offset + req->bytes) <= UINT64_MAX)
*
* Please not there is *not* an actual C assert().
*/
uint64_t bdrv_write_threshold_exceeded(const BlockDriverState *bs,
const BdrvTrackedRequest *req);
void bdrv_write_threshold_check_write(BlockDriverState *bs, int64_t offset,
int64_t bytes);
#endif

8
include/chardev/char-fe.h
View File

@ -174,6 +174,9 @@ void qemu_chr_fe_set_open(CharBackend *be, int fe_open);
void qemu_chr_fe_printf(CharBackend *be, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
typedef gboolean (*FEWatchFunc)(void *do_not_use, GIOCondition condition, void *data);
/**
* qemu_chr_fe_add_watch:
* @cond: the condition to poll for
@ -188,10 +191,13 @@ void qemu_chr_fe_printf(CharBackend *be, const char *fmt, ...)
* Note that you are responsible to update the front-end sources if
* you are switching the main context with qemu_chr_fe_set_handlers().
*
* Warning: DO NOT use the first callback argument (it may be either
* a GIOChannel or a QIOChannel, depending on the underlying chardev)
*
* Returns: the source tag
*/
guint qemu_chr_fe_add_watch(CharBackend *be, GIOCondition cond,
GIOFunc func, void *user_data);
FEWatchFunc func, void *user_data);
/**
* qemu_chr_fe_write:

6
include/crypto/tls-cipher-suites.h
View File

@ -19,12 +19,6 @@ typedef struct QCryptoTLSCipherSuites QCryptoTLSCipherSuites;
DECLARE_INSTANCE_CHECKER(QCryptoTLSCipherSuites, QCRYPTO_TLS_CIPHER_SUITES,
TYPE_QCRYPTO_TLS_CIPHER_SUITES)
struct QCryptoTLSCipherSuites {
/* <private> */
QCryptoTLSCreds parent_obj;
/* <public> */
};
/**
* qcrypto_tls_cipher_suites_get_data:
* @obj: pointer to a TLS cipher suites object

30
include/crypto/tlscreds.h
View File

@ -24,10 +24,6 @@
#include "qapi/qapi-types-crypto.h"
#include "qom/object.h"
#ifdef CONFIG_GNUTLS
#include <gnutls/gnutls.h>
#endif
#define TYPE_QCRYPTO_TLS_CREDS "tls-creds"
typedef struct QCryptoTLSCreds QCryptoTLSCreds;
typedef struct QCryptoTLSCredsClass QCryptoTLSCredsClass;
@ -48,22 +44,24 @@ typedef bool (*CryptoTLSCredsReload)(QCryptoTLSCreds *, Error **);
* certificate credentials.
*/
struct QCryptoTLSCreds {
Object parent_obj;
char *dir;
QCryptoTLSCredsEndpoint endpoint;
#ifdef CONFIG_GNUTLS
gnutls_dh_params_t dh_params;
#endif
bool verifyPeer;
char *priority;
};
struct QCryptoTLSCredsClass {
ObjectClass parent_class;
CryptoTLSCredsReload reload;
};
/**
* qcrypto_tls_creds_check_endpoint:
* @creds: pointer to a TLS credentials object
* @endpoint: type of network endpoint that will be using the credentials
* @errp: pointer to a NULL-initialized error object
*
* Check whether the credentials is setup according to
* the type of @endpoint argument.
*
* Returns true if the credentials is setup for the endpoint, false otherwise
*/
bool qcrypto_tls_creds_check_endpoint(QCryptoTLSCreds *creds,
QCryptoTLSCredsEndpoint endpoint,
Error **errp);
#endif /* QCRYPTO_TLSCREDS_H */

12
include/crypto/tlscredsanon.h
View File

@ -92,18 +92,6 @@ typedef struct QCryptoTLSCredsAnonClass QCryptoTLSCredsAnonClass;
*
*/
struct QCryptoTLSCredsAnon {
QCryptoTLSCreds parent_obj;
#ifdef CONFIG_GNUTLS
union {
gnutls_anon_server_credentials_t server;
gnutls_anon_client_credentials_t client;
} data;
#endif
};
struct QCryptoTLSCredsAnonClass {
QCryptoTLSCredsClass parent_class;
};

12
include/crypto/tlscredspsk.h
View File

@ -87,18 +87,6 @@ typedef struct QCryptoTLSCredsPSKClass QCryptoTLSCredsPSKClass;
* The PSK file can be created and managed using psktool.
*/
struct QCryptoTLSCredsPSK {
QCryptoTLSCreds parent_obj;
char *username;
#ifdef CONFIG_GNUTLS
union {
gnutls_psk_server_credentials_t server;
gnutls_psk_client_credentials_t client;
} data;
#endif
};
struct QCryptoTLSCredsPSKClass {
QCryptoTLSCredsClass parent_class;
};

10
include/crypto/tlscredsx509.h
View File

@ -96,16 +96,6 @@ typedef struct QCryptoTLSCredsX509Class QCryptoTLSCredsX509Class;
*
*/
struct QCryptoTLSCredsX509 {
QCryptoTLSCreds parent_obj;
#ifdef CONFIG_GNUTLS
gnutls_certificate_credentials_t data;
#endif
bool sanityCheck;
char *passwordid;
};
struct QCryptoTLSCredsX509Class {
QCryptoTLSCredsClass parent_class;
};

16
include/disas/dis-asm.h
View File

@ -9,6 +9,12 @@
#ifndef DISAS_DIS_ASM_H
#define DISAS_DIS_ASM_H
#include "qemu/bswap.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void *PTR;
typedef uint64_t bfd_vma;
typedef int64_t bfd_signed_vma;
@ -243,8 +249,6 @@ enum bfd_architecture
#define bfd_mach_nios2 0
#define bfd_mach_nios2r1 1
#define bfd_mach_nios2r2 2
bfd_arch_lm32, /* Lattice Mico32 */
#define bfd_mach_lm32 1
bfd_arch_rx, /* Renesas RX */
#define bfd_mach_rx 0x75
#define bfd_mach_rx_v2 0x76
@ -437,7 +441,6 @@ int print_insn_m32r (bfd_vma, disassemble_info*);
int print_insn_m88k (bfd_vma, disassemble_info*);
int print_insn_mn10200 (bfd_vma, disassemble_info*);
int print_insn_mn10300 (bfd_vma, disassemble_info*);
int print_insn_moxie (bfd_vma, disassemble_info*);
int print_insn_ns32k (bfd_vma, disassemble_info*);
int print_insn_big_powerpc (bfd_vma, disassemble_info*);
int print_insn_little_powerpc (bfd_vma, disassemble_info*);
@ -452,7 +455,6 @@ int print_insn_crisv32 (bfd_vma, disassemble_info*);
int print_insn_crisv10 (bfd_vma, disassemble_info*);
int print_insn_microblaze (bfd_vma, disassemble_info*);
int print_insn_ia64 (bfd_vma, disassemble_info*);
int print_insn_lm32 (bfd_vma, disassemble_info*);
int print_insn_big_nios2 (bfd_vma, disassemble_info*);
int print_insn_little_nios2 (bfd_vma, disassemble_info*);
int print_insn_xtensa (bfd_vma, disassemble_info*);
@ -479,8 +481,6 @@ bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size);
/* from libbfd */
#include "qemu/bswap.h"
static inline bfd_vma bfd_getl64(const bfd_byte *addr)
{
return ldq_le_p(addr);
@ -508,4 +508,8 @@ static inline bfd_vma bfd_getb16(const bfd_byte *addr)
typedef bool bfd_boolean;
#ifdef __cplusplus
}
#endif
#endif /* DISAS_DIS_ASM_H */

13
include/elf.h
View File

@ -174,9 +174,8 @@ typedef struct mips_elf_abiflags_v0 {
#define EM_OPENRISC 92 /* OpenCores OpenRISC */
#define EM_UNICORE32 110 /* UniCore32 */
#define EM_HEXAGON 164 /* Qualcomm Hexagon */
#define EM_RX 173 /* Renesas RX family */
#define EM_RISCV 243 /* RISC-V */
@ -206,9 +205,6 @@ typedef struct mips_elf_abiflags_v0 {
#define EM_AARCH64 183
#define EM_MOXIE 223 /* Moxie processor family */
#define EM_MOXIE_OLD 0xFEED
#define EF_AVR_MACH 0x7F /* Mask for AVR e_flags to get core type */
/* This is the info that is needed to parse the dynamic section of the file */
@ -609,6 +605,13 @@ typedef struct {
#define HWCAP_S390_HIGH_GPRS 512
#define HWCAP_S390_TE 1024
#define HWCAP_S390_VXRS 2048
#define HWCAP_S390_VXRS_BCD 4096
#define HWCAP_S390_VXRS_EXT 8192
#define HWCAP_S390_GS 16384
#define HWCAP_S390_VXRS_EXT2 32768
#define HWCAP_S390_VXRS_PDE 65536
#define HWCAP_S390_SORT 131072
#define HWCAP_S390_DFLT 262144
/* M68K specific definitions. */
/* We use the top 24 bits to encode information about the

2
include/exec/cpu-common.h
View File

@ -57,7 +57,9 @@ const char *qemu_ram_get_idstr(RAMBlock *rb);
void *qemu_ram_get_host_addr(RAMBlock *rb);
ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
bool qemu_ram_is_shared(RAMBlock *rb);
bool qemu_ram_is_noreserve(RAMBlock *rb);
bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
void qemu_ram_set_uf_zeroable(RAMBlock *rb);
bool qemu_ram_is_migratable(RAMBlock *rb);

69
include/exec/exec-all.h
View File

@ -21,7 +21,6 @@
#define EXEC_ALL_H
#include "cpu.h"
#include "exec/tb-context.h"
#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
#endif
@ -262,6 +261,31 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
(CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
/**
* tlb_flush_range_by_mmuidx
* @cpu: CPU whose TLB should be flushed
* @addr: virtual address of the start of the range to be flushed
* @len: length of range to be flushed
* @idxmap: bitmap of mmu indexes to flush
* @bits: number of significant bits in address
*
* For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
* comparing only the low @bits worth of each virtual page.
*/
void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
target_ulong len, uint16_t idxmap,
unsigned bits);
/* Similarly, with broadcast and syncing. */
void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
target_ulong len, uint16_t idxmap,
unsigned bits);
void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
target_ulong addr,
target_ulong len,
uint16_t idxmap,
unsigned bits);
/**
* tlb_set_page_with_attrs:
* @cpu: CPU to add this TLB entry for
@ -365,6 +389,25 @@ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
uint16_t idxmap, unsigned bits)
{
}
static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
target_ulong len, uint16_t idxmap,
unsigned bits)
{
}
static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
target_ulong addr,
target_ulong len,
uint16_t idxmap,
unsigned bits)
{
}
static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
target_ulong addr,
target_long len,
uint16_t idxmap,
unsigned bits)
{
}
#endif
/**
* probe_access:
@ -449,13 +492,18 @@ struct TranslationBlock {
target_ulong cs_base; /* CS base for this block */
uint32_t flags; /* flags defining in which context the code was generated */
uint32_t cflags; /* compile flags */
#define CF_COUNT_MASK 0x00007fff
#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */
#define CF_USE_ICOUNT 0x00020000
#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */
#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */
#define CF_COUNT_MASK 0x000001ff
#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */
#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */
#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */
#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */
#define CF_USE_ICOUNT 0x00020000
#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */
#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
#define CF_CLUSTER_SHIFT 24
/* Per-vCPU dynamic tracing state used to generate this TB */
@ -520,10 +568,7 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)
}
/* current cflags for hashing/comparison */
static inline uint32_t curr_cflags(CPUState *cpu)
{
return cpu->tcg_cflags;
}
uint32_t curr_cflags(CPUState *cpu);
/* TranslationBlock invalidate API */
#if defined(CONFIG_USER_ONLY)

1
include/exec/gen-icount.h
View File

@ -1,6 +1,7 @@
#ifndef GEN_ICOUNT_H
#define GEN_ICOUNT_H
#include "exec/exec-all.h"
#include "qemu/timer.h"
/* Helpers for instruction counting code generation. */

4
include/exec/helper-gen.h
View File

@ -81,8 +81,8 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
#include "helper.h"
#include "trace/generated-helpers.h"
#include "trace/generated-helpers-wrappers.h"
#include "tcg-runtime.h"
#include "plugin-helpers.h"
#include "accel/tcg/tcg-runtime.h"
#include "accel/tcg/plugin-helpers.h"
#undef DEF_HELPER_FLAGS_0
#undef DEF_HELPER_FLAGS_1

37
include/exec/helper-head.h
View File

@ -85,32 +85,14 @@
#define dh_retvar_ptr tcgv_ptr_temp(retval)
#define dh_retvar(t) glue(dh_retvar_, dh_alias(t))
#define dh_is_64bit_void 0
#define dh_is_64bit_noreturn 0
#define dh_is_64bit_i32 0
#define dh_is_64bit_i64 1
#define dh_is_64bit_ptr (sizeof(void *) == 8)
#define dh_is_64bit_cptr dh_is_64bit_ptr
#define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t))
#define dh_is_signed_void 0
#define dh_is_signed_noreturn 0
#define dh_is_signed_i32 0
#define dh_is_signed_s32 1
#define dh_is_signed_i64 0
#define dh_is_signed_s64 1
#define dh_is_signed_f16 0
#define dh_is_signed_f32 0
#define dh_is_signed_f64 0
#define dh_is_signed_tl 0
#define dh_is_signed_int 1
/* ??? This is highly specific to the host cpu. There are even special
extension instructions that may be required, e.g. ia64's addp4. But
for now we don't support any 64-bit targets with 32-bit pointers. */
#define dh_is_signed_ptr 0
#define dh_is_signed_cptr dh_is_signed_ptr
#define dh_is_signed_env dh_is_signed_ptr
#define dh_is_signed(t) dh_is_signed_##t
#define dh_typecode_void 0
#define dh_typecode_noreturn 0
#define dh_typecode_i32 2
#define dh_typecode_s32 3
#define dh_typecode_i64 4
#define dh_typecode_s64 5
#define dh_typecode_ptr 6
#define dh_typecode(t) glue(dh_typecode_, dh_alias(t))
#define dh_callflag_i32 0
#define dh_callflag_s32 0
@ -126,8 +108,7 @@
#define dh_callflag_noreturn TCG_CALL_NO_RETURN
#define dh_callflag(t) glue(dh_callflag_, dh_alias(t))
#define dh_sizemask(t, n) \
((dh_is_64bit(t) << (n*2)) | (dh_is_signed(t) << (n*2+1)))
#define dh_typemask(t, n) (dh_typecode(t) << (n * 3))
#define dh_arg(t, n) \
glue(glue(tcgv_, dh_alias(t)), _temp)(glue(arg, n))

4
include/exec/helper-proto.h
View File

@ -39,8 +39,8 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
#include "helper.h"
#include "trace/generated-helpers.h"
#include "tcg-runtime.h"
#include "plugin-helpers.h"
#include "accel/tcg/tcg-runtime.h"
#include "accel/tcg/plugin-helpers.h"
#undef IN_HELPER_PROTO

38
include/exec/helper-tcg.h
View File

@ -13,55 +13,55 @@
#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) },
.typemask = dh_typemask(ret, 0) },
#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) },
.typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) },
#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) },
.typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
| dh_typemask(t2, 2) },
#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) },
.typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
| dh_typemask(t2, 2) | dh_typemask(t3, 3) },
#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) },
.typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
| dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) },
#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) },
.typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
| dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \
| dh_typemask(t5, 5) },
#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
.typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
| dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \
| dh_typemask(t5, 5) | dh_typemask(t6, 6) },
#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
.typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
| dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \
| dh_typemask(t5, 5) | dh_typemask(t6, 6) | dh_typemask(t7, 7) },
#include "helper.h"
#include "trace/generated-helpers.h"
#include "tcg-runtime.h"
#include "plugin-helpers.h"
#include "accel/tcg/tcg-runtime.h"
#include "accel/tcg/plugin-helpers.h"
#undef str
#undef DEF_HELPER_FLAGS_0

392
include/exec/memory.h
View File

@ -42,6 +42,12 @@ typedef struct IOMMUMemoryRegionClass IOMMUMemoryRegionClass;
DECLARE_OBJ_CHECKERS(IOMMUMemoryRegion, IOMMUMemoryRegionClass,
IOMMU_MEMORY_REGION, TYPE_IOMMU_MEMORY_REGION)
#define TYPE_RAM_DISCARD_MANAGER "qemu:ram-discard-manager"
typedef struct RamDiscardManagerClass RamDiscardManagerClass;
typedef struct RamDiscardManager RamDiscardManager;
DECLARE_OBJ_CHECKERS(RamDiscardManager, RamDiscardManagerClass,
RAM_DISCARD_MANAGER, TYPE_RAM_DISCARD_MANAGER);
#ifdef CONFIG_FUZZ
void fuzz_dma_read_cb(size_t addr,
size_t len,
@ -65,6 +71,28 @@ struct ReservedRegion {
unsigned type;
};
/**
* struct MemoryRegionSection: describes a fragment of a #MemoryRegion
*
* @mr: the region, or %NULL if empty
* @fv: the flat view of the address space the region is mapped in
* @offset_within_region: the beginning of the section, relative to @mr's start
* @size: the size of the section; will not exceed @mr's boundaries
* @offset_within_address_space: the address of the first byte of the section
* relative to the region's address space
* @readonly: writes to this section are ignored
* @nonvolatile: this section is non-volatile
*/
struct MemoryRegionSection {
Int128 size;
MemoryRegion *mr;
FlatView *fv;
hwaddr offset_within_region;
hwaddr offset_within_address_space;
bool readonly;
bool nonvolatile;
};
typedef struct IOMMUTLBEntry IOMMUTLBEntry;
/* See address_space_translate: bit 0 is read, bit 1 is write. */
@ -131,7 +159,7 @@ typedef struct IOMMUTLBEvent {
#define RAM_SHARED (1 << 1)
/* Only a portion of RAM (used_length) is actually used, and migrated.
* This used_length size can change across reboots.
* Resizing RAM while migrating can result in the migration being canceled.
*/
#define RAM_RESIZEABLE (1 << 2)
@ -155,6 +183,13 @@ typedef struct IOMMUTLBEvent {
*/
#define RAM_UF_WRITEPROTECT (1 << 6)
/*
* RAM is mmap-ed with MAP_NORESERVE. When set, reserving swap space (or huge
* pages if applicable) is skipped: will bail out if not supported. When not
* set, the OS will do the reservation, if supported for the memory type.
*/
#define RAM_NORESERVE (1 << 7)
static inline void iommu_notifier_init(IOMMUNotifier *n, IOMMUNotify fn,
IOMMUNotifierFlag flags,
hwaddr start, hwaddr end,
@ -441,6 +476,206 @@ struct IOMMUMemoryRegionClass {
Error **errp);
};
typedef struct RamDiscardListener RamDiscardListener;
typedef int (*NotifyRamPopulate)(RamDiscardListener *rdl,
MemoryRegionSection *section);
typedef void (*NotifyRamDiscard)(RamDiscardListener *rdl,
MemoryRegionSection *section);
struct RamDiscardListener {
/*
* @notify_populate:
*
* Notification that previously discarded memory is about to get populated.
* Listeners are able to object. If any listener objects, already
* successfully notified listeners are notified about a discard again.
*
* @rdl: the #RamDiscardListener getting notified
* @section: the #MemoryRegionSection to get populated. The section
* is aligned within the memory region to the minimum granularity
* unless it would exceed the registered section.
*
* Returns 0 on success. If the notification is rejected by the listener,
* an error is returned.
*/
NotifyRamPopulate notify_populate;
/*
* @notify_discard:
*
* Notification that previously populated memory was discarded successfully
* and listeners should drop all references to such memory and prevent
* new population (e.g., unmap).
*
* @rdl: the #RamDiscardListener getting notified
* @section: the #MemoryRegionSection to get populated. The section
* is aligned within the memory region to the minimum granularity
* unless it would exceed the registered section.
*/
NotifyRamDiscard notify_discard;
/*
* @double_discard_supported:
*
* The listener suppors getting @notify_discard notifications that span
* already discarded parts.
*/
bool double_discard_supported;
MemoryRegionSection *section;
QLIST_ENTRY(RamDiscardListener) next;
};
static inline void ram_discard_listener_init(RamDiscardListener *rdl,
NotifyRamPopulate populate_fn,
NotifyRamDiscard discard_fn,
bool double_discard_supported)
{
rdl->notify_populate = populate_fn;
rdl->notify_discard = discard_fn;
rdl->double_discard_supported = double_discard_supported;
}
typedef int (*ReplayRamPopulate)(MemoryRegionSection *section, void *opaque);
/*
* RamDiscardManagerClass:
*
* A #RamDiscardManager coordinates which parts of specific RAM #MemoryRegion
* regions are currently populated to be used/accessed by the VM, notifying
* after parts were discarded (freeing up memory) and before parts will be
* populated (consuming memory), to be used/acessed by the VM.
*
* A #RamDiscardManager can only be set for a RAM #MemoryRegion while the
* #MemoryRegion isn't mapped yet; it cannot change while the #MemoryRegion is
* mapped.
*
* The #RamDiscardManager is intended to be used by technologies that are
* incompatible with discarding of RAM (e.g., VFIO, which may pin all
* memory inside a #MemoryRegion), and require proper coordination to only
* map the currently populated parts, to hinder parts that are expected to
* remain discarded from silently getting populated and consuming memory.
* Technologies that support discarding of RAM don't have to bother and can
* simply map the whole #MemoryRegion.
*
* An example #RamDiscardManager is virtio-mem, which logically (un)plugs
* memory within an assigned RAM #MemoryRegion, coordinated with the VM.
* Logically unplugging memory consists of discarding RAM. The VM agreed to not
* access unplugged (discarded) memory - especially via DMA. virtio-mem will
* properly coordinate with listeners before memory is plugged (populated),
* and after memory is unplugged (discarded).
*
* Listeners are called in multiples of the minimum granularity (unless it
* would exceed the registered range) and changes are aligned to the minimum
* granularity within the #MemoryRegion. Listeners have to prepare for memory
* becomming discarded in a different granularity than it was populated and the
* other way around.
*/
struct RamDiscardManagerClass {
/* private */
InterfaceClass parent_class;
/* public */
/**
* @get_min_granularity:
*
* Get the minimum granularity in which listeners will get notified
* about changes within the #MemoryRegion via the #RamDiscardManager.
*
* @rdm: the #RamDiscardManager
* @mr: the #MemoryRegion
*
* Returns the minimum granularity.
*/
uint64_t (*get_min_granularity)(const RamDiscardManager *rdm,
const MemoryRegion *mr);
/**
* @is_populated:
*
* Check whether the given #MemoryRegionSection is completely populated
* (i.e., no parts are currently discarded) via the #RamDiscardManager.
* There are no alignment requirements.
*
* @rdm: the #RamDiscardManager
* @section: the #MemoryRegionSection
*
* Returns whether the given range is completely populated.
*/
bool (*is_populated)(const RamDiscardManager *rdm,
const MemoryRegionSection *section);
/**
* @replay_populated:
*
* Call the #ReplayRamPopulate callback for all populated parts within the
* #MemoryRegionSection via the #RamDiscardManager.
*
* In case any call fails, no further calls are made.
*
* @rdm: the #RamDiscardManager
* @section: the #MemoryRegionSection
* @replay_fn: the #ReplayRamPopulate callback
* @opaque: pointer to forward to the callback
*
* Returns 0 on success, or a negative error if any notification failed.
*/
int (*replay_populated)(const RamDiscardManager *rdm,
MemoryRegionSection *section,
ReplayRamPopulate replay_fn, void *opaque);
/**
* @register_listener:
*
* Register a #RamDiscardListener for the given #MemoryRegionSection and
* immediately notify the #RamDiscardListener about all populated parts
* within the #MemoryRegionSection via the #RamDiscardManager.
*
* In case any notification fails, no further notifications are triggered
* and an error is logged.
*
* @rdm: the #RamDiscardManager
* @rdl: the #RamDiscardListener
* @section: the #MemoryRegionSection
*/
void (*register_listener)(RamDiscardManager *rdm,
RamDiscardListener *rdl,
MemoryRegionSection *section);
/**
* @unregister_listener:
*
* Unregister a previously registered #RamDiscardListener via the
* #RamDiscardManager after notifying the #RamDiscardListener about all
* populated parts becoming unpopulated within the registered
* #MemoryRegionSection.
*
* @rdm: the #RamDiscardManager
* @rdl: the #RamDiscardListener
*/
void (*unregister_listener)(RamDiscardManager *rdm,
RamDiscardListener *rdl);
};
uint64_t ram_discard_manager_get_min_granularity(const RamDiscardManager *rdm,
const MemoryRegion *mr);
bool ram_discard_manager_is_populated(const RamDiscardManager *rdm,
const MemoryRegionSection *section);
int ram_discard_manager_replay_populated(const RamDiscardManager *rdm,
MemoryRegionSection *section,
ReplayRamPopulate replay_fn,
void *opaque);
void ram_discard_manager_register_listener(RamDiscardManager *rdm,
RamDiscardListener *rdl,
MemoryRegionSection *section);
void ram_discard_manager_unregister_listener(RamDiscardManager *rdm,
RamDiscardListener *rdl);
typedef struct CoalescedMemoryRange CoalescedMemoryRange;
typedef struct MemoryRegionIoeventfd MemoryRegionIoeventfd;
@ -487,6 +722,7 @@ struct MemoryRegion {
const char *name;
unsigned ioeventfd_nb;
MemoryRegionIoeventfd *ioeventfds;
RamDiscardManager *rdm; /* Only for RAM */
};
struct IOMMUMemoryRegion {
@ -571,7 +807,7 @@ struct MemoryListener {
* @log_start:
*
* Called during an address space update transaction, after
* one of #MemoryListener.region_add(),#MemoryListener.region_del() or
* one of #MemoryListener.region_add(), #MemoryListener.region_del() or
* #MemoryListener.region_nop(), if dirty memory logging clients have
* become active since the last transaction.
*
@ -616,6 +852,18 @@ struct MemoryListener {
*/
void (*log_sync)(MemoryListener *listener, MemoryRegionSection *section);
/**
* @log_sync_global:
*
* This is the global version of @log_sync when the listener does
* not have a way to synchronize the log with finer granularity.
* When the listener registers with @log_sync_global defined, then
* its @log_sync must be NULL. Vice versa.
*
* @listener: The #MemoryListener.
*/
void (*log_sync_global)(MemoryListener *listener);
/**
* @log_clear:
*
@ -806,28 +1054,6 @@ typedef bool (*flatview_cb)(Int128 start,
*/
void flatview_for_each_range(FlatView *fv, flatview_cb cb, void *opaque);
/**
* struct MemoryRegionSection: describes a fragment of a #MemoryRegion
*
* @mr: the region, or %NULL if empty
* @fv: the flat view of the address space the region is mapped in
* @offset_within_region: the beginning of the section, relative to @mr's start
* @size: the size of the section; will not exceed @mr's boundaries
* @offset_within_address_space: the address of the first byte of the section
* relative to the region's address space
* @readonly: writes to this section are ignored
* @nonvolatile: this section is non-volatile
*/
struct MemoryRegionSection {
Int128 size;
MemoryRegion *mr;
FlatView *fv;
hwaddr offset_within_region;
hwaddr offset_within_address_space;
bool readonly;
bool nonvolatile;
};
static inline bool MemoryRegionSection_eq(MemoryRegionSection *a,
MemoryRegionSection *b)
{
@ -840,6 +1066,26 @@ static inline bool MemoryRegionSection_eq(MemoryRegionSection *a,
a->nonvolatile == b->nonvolatile;
}
/**
* memory_region_section_new_copy: Copy a memory region section
*
* Allocate memory for a new copy, copy the memory region section, and
* properly take a reference on all relevant members.
*
* @s: the #MemoryRegionSection to copy
*/
MemoryRegionSection *memory_region_section_new_copy(MemoryRegionSection *s);
/**
* memory_region_section_new_copy: Free a copied memory region section
*
* Free a copy of a memory section created via memory_region_section_new_copy().
* properly dropping references on all relevant members.
*
* @s: the #MemoryRegionSection to copy
*/
void memory_region_section_free_copy(MemoryRegionSection *s);
/**
* memory_region_init: Initialize a memory region
*
@ -934,34 +1180,36 @@ void memory_region_init_ram_nomigrate(MemoryRegion *mr,
Error **errp);
/**
* memory_region_init_ram_shared_nomigrate: Initialize RAM memory region.
* Accesses into the region will
* modify memory directly.
* memory_region_init_ram_flags_nomigrate: Initialize RAM memory region.
* Accesses into the region will
* modify memory directly.
*
* @mr: the #MemoryRegion to be initialized.
* @owner: the object that tracks the region's reference count
* @name: Region name, becomes part of RAMBlock name used in migration stream
* must be unique within any device
* @size: size of the region.
* @share: allow remapping RAM to different addresses
* @ram_flags: RamBlock flags. Supported flags: RAM_SHARED, RAM_NORESERVE.
* @errp: pointer to Error*, to store an error if it happens.
*
* Note that this function is similar to memory_region_init_ram_nomigrate.
* The only difference is part of the RAM region can be remapped.
* Note that this function does not do anything to cause the data in the
* RAM memory region to be migrated; that is the responsibility of the caller.
*/
void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
Object *owner,
const char *name,
uint64_t size,
bool share,
Error **errp);
void memory_region_init_ram_flags_nomigrate(MemoryRegion *mr,
Object *owner,
const char *name,
uint64_t size,
uint32_t ram_flags,
Error **errp);
/**
* memory_region_init_resizeable_ram: Initialize memory region with resizeable
* RAM. Accesses into the region will
* modify memory directly. Only an initial
* portion of this RAM is actually used.
* The used size can change across reboots.
* Changing the size while migrating
* can result in the migration being
* canceled.
*
* @mr: the #MemoryRegion to be initialized.
* @owner: the object that tracks the region's reference count
@ -997,10 +1245,8 @@ void memory_region_init_resizeable_ram(MemoryRegion *mr,
* @size: size of the region.
* @align: alignment of the region base address; if 0, the default alignment
* (getpagesize()) will be used.
* @ram_flags: Memory region features:
* - RAM_SHARED: memory must be mmaped with the MAP_SHARED flag
* - RAM_PMEM: the memory is persistent memory
* Other bits are ignored now.
* @ram_flags: RamBlock flags. Supported flags: RAM_SHARED, RAM_PMEM,
* RAM_NORESERVE,
* @path: the path in which to allocate the RAM.
* @readonly: true to open @path for reading, false for read/write.
* @errp: pointer to Error*, to store an error if it happens.
@ -1026,7 +1272,8 @@ void memory_region_init_ram_from_file(MemoryRegion *mr,
* @owner: the object that tracks the region's reference count
* @name: the name of the region.
* @size: size of the region.
* @share: %true if memory must be mmaped with the MAP_SHARED flag
* @ram_flags: RamBlock flags. Supported flags: RAM_SHARED, RAM_PMEM,
* RAM_NORESERVE.
* @fd: the fd to mmap.
* @offset: offset within the file referenced by fd
* @errp: pointer to Error*, to store an error if it happens.
@ -1038,7 +1285,7 @@ void memory_region_init_ram_from_fd(MemoryRegion *mr,
Object *owner,
const char *name,
uint64_t size,
bool share,
uint32_t ram_flags,
int fd,
ram_addr_t offset,
Error **errp);
@ -1592,8 +1839,8 @@ void *memory_region_get_ram_ptr(MemoryRegion *mr);
/* memory_region_ram_resize: Resize a RAM region.
*
* Only legal before guest might have detected the memory size: e.g. on
* incoming migration, or right after reset.
* Resizing RAM while migrating can result in the migration being canceled.
* Care has to be taken if the guest might have already detected the memory.
*
* @mr: a memory region created with @memory_region_init_resizeable_ram.
* @newsize: the new size the region
@ -2028,6 +2275,41 @@ bool memory_region_present(MemoryRegion *container, hwaddr addr);
*/
bool memory_region_is_mapped(MemoryRegion *mr);
/**
* memory_region_get_ram_discard_manager: get the #RamDiscardManager for a
* #MemoryRegion
*
* The #RamDiscardManager cannot change while a memory region is mapped.
*
* @mr: the #MemoryRegion
*/
RamDiscardManager *memory_region_get_ram_discard_manager(MemoryRegion *mr);
/**
* memory_region_has_ram_discard_manager: check whether a #MemoryRegion has a
* #RamDiscardManager assigned
*
* @mr: the #MemoryRegion
*/
static inline bool memory_region_has_ram_discard_manager(MemoryRegion *mr)
{
return !!memory_region_get_ram_discard_manager(mr);
}
/**
* memory_region_set_ram_discard_manager: set the #RamDiscardManager for a
* #MemoryRegion
*
* This function must not be called for a mapped #MemoryRegion, a #MemoryRegion
* that does not cover RAM, or a #MemoryRegion that already has a
* #RamDiscardManager assigned.
*
* @mr: the #MemoryRegion
* @rdm: #RamDiscardManager to set
*/
void memory_region_set_ram_discard_manager(MemoryRegion *mr,
RamDiscardManager *rdm);
/**
* memory_region_find: translate an address/size relative to a
* MemoryRegion into a #MemoryRegionSection.
@ -2328,7 +2610,7 @@ static inline uint8_t address_space_ldub_cached(MemoryRegionCache *cache,
}
static inline void address_space_stb_cached(MemoryRegionCache *cache,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len);
if (likely(cache->ptr)) {
@ -2636,6 +2918,12 @@ static inline MemOp devend_memop(enum device_endian end)
*/
int ram_block_discard_disable(bool state);
/*
* See ram_block_discard_disable(): only disable uncoordinated discards,
* keeping coordinated discards (via the RamDiscardManager) enabled.
*/
int ram_block_uncoordinated_discard_disable(bool state);
/*
* Inhibit technologies that disable discarding of pages in RAM blocks.
*
@ -2645,12 +2933,20 @@ int ram_block_discard_disable(bool state);
int ram_block_discard_require(bool state);
/*
* Test if discarding of memory in ram blocks is disabled.
* See ram_block_discard_require(): only inhibit technologies that disable
* uncoordinated discarding of pages in RAM blocks, allowing co-existance with
* technologies that only inhibit uncoordinated discards (via the
* RamDiscardManager).
*/
int ram_block_coordinated_discard_require(bool state);
/*
* Test if any discarding of memory in ram blocks is disabled.
*/
bool ram_block_discard_is_disabled(void);
/*
* Test if discarding of memory in ram blocks is required to work reliably.
* Test if any discarding of memory in ram blocks is required to work reliably.
*/
bool ram_block_discard_is_required(void);

16
include/exec/memory_ldst.h.inc
View File

@ -20,7 +20,7 @@
*/
#ifdef TARGET_ENDIANNESS
extern uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
extern uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
@ -29,17 +29,17 @@ extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
#else
extern uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
extern uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
extern uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
extern uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
@ -50,11 +50,11 @@ extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stb, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,

46
include/exec/memory_ldst_cached.h.inc
View File

@ -24,6 +24,18 @@
#define LD_P(size) \
glue(glue(ld, size), glue(ENDIANNESS, _p))
static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
if (likely(cache->ptr)) {
return LD_P(uw)(cache->ptr + addr);
} else {
return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
}
}
static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
@ -48,18 +60,6 @@ static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
}
}
static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
if (likely(cache->ptr)) {
return LD_P(uw)(cache->ptr + addr);
} else {
return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
}
}
#undef ADDRESS_SPACE_LD_CACHED
#undef ADDRESS_SPACE_LD_CACHED_SLOW
#undef LD_P
@ -71,6 +71,17 @@ static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
#define ST_P(size) \
glue(glue(st, size), glue(ENDIANNESS, _p))
static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
if (likely(cache->ptr)) {
ST_P(w)(cache->ptr + addr, val);
} else {
ADDRESS_SPACE_ST_CACHED_SLOW(w)(cache, addr, val, attrs, result);
}
}
static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
{
@ -82,17 +93,6 @@ static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
}
}
static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
if (likely(cache->ptr)) {
ST_P(w)(cache->ptr + addr, val);
} else {
ADDRESS_SPACE_ST_CACHED_SLOW(w)(cache, addr, val, attrs, result);
}
}
static inline void ADDRESS_SPACE_ST_CACHED(q)(MemoryRegionCache *cache,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
{

72
include/exec/memory_ldst_phys.h.inc
View File

@ -20,6 +20,12 @@
*/
#ifdef TARGET_ENDIANNESS
static inline uint16_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_lduw, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint32_t glue(ldl_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldl, SUFFIX)(ARG1, addr,
@ -32,10 +38,10 @@ static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
{
return glue(address_space_lduw, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
glue(address_space_stw, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
@ -44,18 +50,30 @@ static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
glue(address_space_stw, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
{
glue(address_space_stq, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
#else
static inline uint8_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldub, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint16_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint16_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldl_le, SUFFIX)(ARG1, addr,
@ -80,22 +98,22 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val)
{
return glue(address_space_ldub, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
{
return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
glue(address_space_stw_le, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
{
return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
glue(address_space_stw_be, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
@ -110,24 +128,6 @@ static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t va
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
glue(address_space_stw_le, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
glue(address_space_stw_be, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
{
glue(address_space_stq_le, SUFFIX)(ARG1, addr, val,

11
include/exec/poison.h
View File

@ -4,6 +4,8 @@
#ifndef HW_POISON_H
#define HW_POISON_H
#include "config-poison.h"
#pragma GCC poison TARGET_I386
#pragma GCC poison TARGET_X86_64
#pragma GCC poison TARGET_AARCH64
@ -12,7 +14,6 @@
#pragma GCC poison TARGET_CRIS
#pragma GCC poison TARGET_HEXAGON
#pragma GCC poison TARGET_HPPA
#pragma GCC poison TARGET_LM32
#pragma GCC poison TARGET_M68K
#pragma GCC poison TARGET_MICROBLAZE
#pragma GCC poison TARGET_MIPS
@ -20,7 +21,6 @@
#pragma GCC poison TARGET_ABI_MIPSO32
#pragma GCC poison TARGET_MIPS64
#pragma GCC poison TARGET_ABI_MIPSN64
#pragma GCC poison TARGET_MOXIE
#pragma GCC poison TARGET_NIOS2
#pragma GCC poison TARGET_OPENRISC
#pragma GCC poison TARGET_PPC
@ -32,7 +32,6 @@
#pragma GCC poison TARGET_SPARC
#pragma GCC poison TARGET_SPARC64
#pragma GCC poison TARGET_TRICORE
#pragma GCC poison TARGET_UNICORE32
#pragma GCC poison TARGET_XTENSA
#pragma GCC poison TARGET_ALIGNED_ONLY
@ -74,12 +73,10 @@
#pragma GCC poison CONFIG_HPPA_DIS
#pragma GCC poison CONFIG_I386_DIS
#pragma GCC poison CONFIG_HEXAGON_DIS
#pragma GCC poison CONFIG_LM32_DIS
#pragma GCC poison CONFIG_M68K_DIS
#pragma GCC poison CONFIG_MICROBLAZE_DIS
#pragma GCC poison CONFIG_MIPS_DIS
#pragma GCC poison CONFIG_NANOMIPS_DIS
#pragma GCC poison CONFIG_MOXIE_DIS
#pragma GCC poison CONFIG_NIOS2_DIS
#pragma GCC poison CONFIG_PPC_DIS
#pragma GCC poison CONFIG_RISCV_DIS
@ -88,8 +85,12 @@
#pragma GCC poison CONFIG_SPARC_DIS
#pragma GCC poison CONFIG_XTENSA_DIS
#pragma GCC poison CONFIG_HAX
#pragma GCC poison CONFIG_HVF
#pragma GCC poison CONFIG_LINUX_USER
#pragma GCC poison CONFIG_KVM
#pragma GCC poison CONFIG_SOFTMMU
#pragma GCC poison CONFIG_WHPX
#pragma GCC poison CONFIG_XEN
#endif

9
include/exec/ram_addr.h
View File

@ -104,11 +104,8 @@ long qemu_maxrampagesize(void);
* Parameters:
* @size: the size in bytes of the ram block
* @mr: the memory region where the ram block is
* @ram_flags: specify the properties of the ram block, which can be one
* or bit-or of following values
* - RAM_SHARED: mmap the backing file or device with MAP_SHARED
* - RAM_PMEM: the backend @mem_path or @fd is persistent memory
* Other bits are ignored.
* @ram_flags: RamBlock flags. Supported flags: RAM_SHARED, RAM_PMEM,
* RAM_NORESERVE.
* @mem_path or @fd: specify the backing file or device
* @readonly: true to open @path for reading, false for read/write.
* @errp: pointer to Error*, to store an error if it happens
@ -126,7 +123,7 @@ RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
MemoryRegion *mr, Error **errp);
RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share, MemoryRegion *mr,
RAMBlock *qemu_ram_alloc(ram_addr_t size, uint32_t ram_flags, MemoryRegion *mr,
Error **errp);
RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t max_size,
void (*resized)(const char*,

10
include/exec/ramblock.h
View File

@ -59,6 +59,16 @@ struct RAMBlock {
*/
unsigned long *clear_bmap;
uint8_t clear_bmap_shift;
/*
* RAM block length that corresponds to the used_length on the migration
* source (after RAM block sizes were synchronized). Especially, after
* starting to run the guest, used_length and postcopy_length can differ.
* Used to register/unregister uffd handlers and as the size of the received
* bitmap. Receiving any page beyond this length will bail out, as it
* could not have been valid on the source.
*/
ram_addr_t postcopy_length;
};
#endif
#endif

13
include/exec/ramlist.h
View File

@ -67,15 +67,20 @@ void qemu_mutex_lock_ramlist(void);
void qemu_mutex_unlock_ramlist(void);
struct RAMBlockNotifier {
void (*ram_block_added)(RAMBlockNotifier *n, void *host, size_t size);
void (*ram_block_removed)(RAMBlockNotifier *n, void *host, size_t size);
void (*ram_block_added)(RAMBlockNotifier *n, void *host, size_t size,
size_t max_size);
void (*ram_block_removed)(RAMBlockNotifier *n, void *host, size_t size,
size_t max_size);
void (*ram_block_resized)(RAMBlockNotifier *n, void *host, size_t old_size,
size_t new_size);
QLIST_ENTRY(RAMBlockNotifier) next;
};
void ram_block_notifier_add(RAMBlockNotifier *n);
void ram_block_notifier_remove(RAMBlockNotifier *n);
void ram_block_notify_add(void *host, size_t size);
void ram_block_notify_remove(void *host, size_t size);
void ram_block_notify_add(void *host, size_t size, size_t max_size);
void ram_block_notify_remove(void *host, size_t size, size_t max_size);
void ram_block_notify_resize(void *host, size_t old_size, size_t new_size);
void ram_block_dump(Monitor *mon);

69
include/exec/tb-hash.h
View File

@ -1,69 +0,0 @@
/*
* internal execution defines for qemu
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef EXEC_TB_HASH_H
#define EXEC_TB_HASH_H
#include "exec/cpu-defs.h"
#include "exec/exec-all.h"
#include "qemu/xxhash.h"
#ifdef CONFIG_SOFTMMU
/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
addresses on the same page. The top bits are the same. This allows
TLB invalidation to quickly clear a subset of the hash table. */
#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
target_ulong tmp;
tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
}
static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
target_ulong tmp;
tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
| (tmp & TB_JMP_ADDR_MASK));
}
#else
/* In user-mode we can get better hashing because we do not have a TLB */
static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
}
#endif /* CONFIG_SOFTMMU */
static inline
uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t flags,
uint32_t cf_mask, uint32_t trace_vcpu_dstate)
{
return qemu_xxhash7(phys_pc, pc, flags, cf_mask, trace_vcpu_dstate);
}
#endif

49
include/exec/tb-lookup.h
View File

@ -1,49 +0,0 @@
/*
* Copyright (C) 2017, Emilio G. Cota <cota@braap.org>
*
* License: GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef EXEC_TB_LOOKUP_H
#define EXEC_TB_LOOKUP_H
#ifdef NEED_CPU_H
#include "cpu.h"
#else
#include "exec/poison.h"
#endif
#include "exec/exec-all.h"
#include "exec/tb-hash.h"
/* Might cause an exception, so have a longjmp destination ready */
static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
target_ulong cs_base,
uint32_t flags, uint32_t cflags)
{
TranslationBlock *tb;
uint32_t hash;
/* we should never be trying to look up an INVALID tb */
tcg_debug_assert(!(cflags & CF_INVALID));
hash = tb_jmp_cache_hash_func(pc);
tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
if (likely(tb &&
tb->pc == pc &&
tb->cs_base == cs_base &&
tb->flags == flags &&
tb->trace_vcpu_dstate == *cpu->trace_dstate &&
tb_cflags(tb) == cflags)) {
return tb;
}
tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
if (tb == NULL) {
return NULL;
}
qatomic_set(&cpu->tb_jmp_cache[hash], tb);
return tb;
}
#endif /* EXEC_TB_LOOKUP_H */

21
include/exec/translator.h
View File

@ -89,15 +89,6 @@ typedef struct DisasContextBase {
* @insn_start:
* Emit the tcg_gen_insn_start opcode.
*
* @breakpoint_check:
* When called, the breakpoint has already been checked to match the PC,
* but the target may decide the breakpoint missed the address
* (e.g., due to conditions encoded in their flags). Return true to
* indicate that the breakpoint did hit, in which case no more breakpoints
* are checked. If the breakpoint did hit, emit any code required to
* signal the exception, and set db->is_jmp as necessary to terminate
* the main loop.
*
* @translate_insn:
* Disassemble one instruction and set db->pc_next for the start
* of the following instruction. Set db->is_jmp as necessary to
@ -113,8 +104,6 @@ typedef struct TranslatorOps {
void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
void (*tb_start)(DisasContextBase *db, CPUState *cpu);
void (*insn_start)(DisasContextBase *db, CPUState *cpu);
bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu,
const CPUBreakpoint *bp);
void (*translate_insn)(DisasContextBase *db, CPUState *cpu);
void (*tb_stop)(DisasContextBase *db, CPUState *cpu);
void (*disas_log)(const DisasContextBase *db, CPUState *cpu);
@ -145,6 +134,16 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
void translator_loop_temp_check(DisasContextBase *db);
/**
* translator_use_goto_tb
* @db: Disassembly context
* @dest: target pc of the goto
*
* Return true if goto_tb is allowed between the current TB
* and the destination PC.
*/
bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
/*
* Translator Load Functions
*

9
include/fpu/softfloat-helpers.h
View File

@ -48,8 +48,8 @@ this code that are retained.
===============================================================================
*/
#ifndef _SOFTFLOAT_HELPERS_H_
#define _SOFTFLOAT_HELPERS_H_
#ifndef SOFTFLOAT_HELPERS_H
#define SOFTFLOAT_HELPERS_H
#include "fpu/softfloat-types.h"
@ -69,7 +69,7 @@ static inline void set_float_exception_flags(int val, float_status *status)
status->float_exception_flags = val;
}
static inline void set_floatx80_rounding_precision(int val,
static inline void set_floatx80_rounding_precision(FloatX80RoundPrec val,
float_status *status)
{
status->floatx80_rounding_precision = val;
@ -120,7 +120,8 @@ static inline int get_float_exception_flags(float_status *status)
return status->float_exception_flags;
}
static inline int get_floatx80_rounding_precision(float_status *status)
static inline FloatX80RoundPrec
get_floatx80_rounding_precision(float_status *status)
{
return status->floatx80_rounding_precision;
}

247
include/fpu/softfloat-macros.h
View File

@ -83,6 +83,43 @@ this code that are retained.
#define FPU_SOFTFLOAT_MACROS_H
#include "fpu/softfloat-types.h"
#include "qemu/host-utils.h"
/**
* shl_double: double-word merging left shift
* @l: left or most-significant word
* @r: right or least-significant word
* @c: shift count
*
* Shift @l left by @c bits, shifting in bits from @r.
*/
static inline uint64_t shl_double(uint64_t l, uint64_t r, int c)
{
#if defined(__x86_64__)
asm("shld %b2, %1, %0" : "+r"(l) : "r"(r), "ci"(c));
return l;
#else
return c ? (l << c) | (r >> (64 - c)) : l;
#endif
}
/**
* shr_double: double-word merging right shift
* @l: left or most-significant word
* @r: right or least-significant word
* @c: shift count
*
* Shift @r right by @c bits, shifting in bits from @l.
*/
static inline uint64_t shr_double(uint64_t l, uint64_t r, int c)
{
#if defined(__x86_64__)
asm("shrd %b2, %1, %0" : "+r"(r) : "r"(l), "ci"(c));
return r;
#else
return c ? (r >> c) | (l << (64 - c)) : r;
#endif
}
/*----------------------------------------------------------------------------
| Shifts `a' right by the number of bits given in `count'. If any nonzero
@ -403,16 +440,12 @@ static inline void
| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
*----------------------------------------------------------------------------*/
static inline void
add128(
uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, uint64_t *z1Ptr )
static inline void add128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1,
uint64_t *z0Ptr, uint64_t *z1Ptr)
{
uint64_t z1;
z1 = a1 + b1;
*z1Ptr = z1;
*z0Ptr = a0 + b0 + ( z1 < a1 );
bool c = 0;
*z1Ptr = uadd64_carry(a1, b1, &c);
*z0Ptr = uadd64_carry(a0, b0, &c);
}
/*----------------------------------------------------------------------------
@ -423,34 +456,14 @@ static inline void
| `z1Ptr', and `z2Ptr'.
*----------------------------------------------------------------------------*/
static inline void
add192(
uint64_t a0,
uint64_t a1,
uint64_t a2,
uint64_t b0,
uint64_t b1,
uint64_t b2,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
static inline void add192(uint64_t a0, uint64_t a1, uint64_t a2,
uint64_t b0, uint64_t b1, uint64_t b2,
uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Ptr)
{
uint64_t z0, z1, z2;
int8_t carry0, carry1;
z2 = a2 + b2;
carry1 = ( z2 < a2 );
z1 = a1 + b1;
carry0 = ( z1 < a1 );
z0 = a0 + b0;
z1 += carry1;
z0 += ( z1 < carry1 );
z0 += carry0;
*z2Ptr = z2;
*z1Ptr = z1;
*z0Ptr = z0;
bool c = 0;
*z2Ptr = uadd64_carry(a2, b2, &c);
*z1Ptr = uadd64_carry(a1, b1, &c);
*z0Ptr = uadd64_carry(a0, b0, &c);
}
/*----------------------------------------------------------------------------
@ -461,14 +474,12 @@ static inline void
| `z1Ptr'.
*----------------------------------------------------------------------------*/
static inline void
sub128(
uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, uint64_t *z1Ptr )
static inline void sub128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1,
uint64_t *z0Ptr, uint64_t *z1Ptr)
{
*z1Ptr = a1 - b1;
*z0Ptr = a0 - b0 - ( a1 < b1 );
bool c = 0;
*z1Ptr = usub64_borrow(a1, b1, &c);
*z0Ptr = usub64_borrow(a0, b0, &c);
}
/*----------------------------------------------------------------------------
@ -479,34 +490,14 @@ static inline void
| pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.
*----------------------------------------------------------------------------*/
static inline void
sub192(
uint64_t a0,
uint64_t a1,
uint64_t a2,
uint64_t b0,
uint64_t b1,
uint64_t b2,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
static inline void sub192(uint64_t a0, uint64_t a1, uint64_t a2,
uint64_t b0, uint64_t b1, uint64_t b2,
uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Ptr)
{
uint64_t z0, z1, z2;
int8_t borrow0, borrow1;
z2 = a2 - b2;
borrow1 = ( a2 < b2 );
z1 = a1 - b1;
borrow0 = ( a1 < b1 );
z0 = a0 - b0;
z0 -= ( z1 < borrow1 );
z1 -= borrow1;
z0 -= borrow0;
*z2Ptr = z2;
*z1Ptr = z1;
*z0Ptr = z0;
bool c = 0;
*z2Ptr = usub64_borrow(a2, b2, &c);
*z1Ptr = usub64_borrow(a1, b1, &c);
*z0Ptr = usub64_borrow(a0, b0, &c);
}
/*----------------------------------------------------------------------------
@ -515,27 +506,10 @@ static inline void
| `z0Ptr' and `z1Ptr'.
*----------------------------------------------------------------------------*/
static inline void mul64To128( uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr )
static inline void
mul64To128(uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr)
{
uint32_t aHigh, aLow, bHigh, bLow;
uint64_t z0, zMiddleA, zMiddleB, z1;
aLow = a;
aHigh = a>>32;
bLow = b;
bHigh = b>>32;
z1 = ( (uint64_t) aLow ) * bLow;
zMiddleA = ( (uint64_t) aLow ) * bHigh;
zMiddleB = ( (uint64_t) aHigh ) * bLow;
z0 = ( (uint64_t) aHigh ) * bHigh;
zMiddleA += zMiddleB;
z0 += ( ( (uint64_t) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
zMiddleA <<= 32;
z1 += zMiddleA;
z0 += ( z1 < zMiddleA );
*z1Ptr = z1;
*z0Ptr = z0;
mulu64(z1Ptr, z0Ptr, a, b);
}
/*----------------------------------------------------------------------------
@ -546,24 +520,14 @@ static inline void mul64To128( uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t
*----------------------------------------------------------------------------*/
static inline void
mul128By64To192(
uint64_t a0,
uint64_t a1,
uint64_t b,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr
)
mul128By64To192(uint64_t a0, uint64_t a1, uint64_t b,
uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Ptr)
{
uint64_t z0, z1, z2, more1;
mul64To128( a1, b, &z1, &z2 );
mul64To128( a0, b, &z0, &more1 );
add128( z0, more1, 0, z1, &z0, &z1 );
*z2Ptr = z2;
*z1Ptr = z1;
*z0Ptr = z0;
uint64_t z0, z1, m1;
mul64To128(a1, b, &m1, z2Ptr);
mul64To128(a0, b, &z0, &z1);
add128(z0, z1, 0, m1, z0Ptr, z1Ptr);
}
/*----------------------------------------------------------------------------
@ -573,34 +537,21 @@ static inline void
| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
*----------------------------------------------------------------------------*/
static inline void
mul128To256(
uint64_t a0,
uint64_t a1,
uint64_t b0,
uint64_t b1,
uint64_t *z0Ptr,
uint64_t *z1Ptr,
uint64_t *z2Ptr,
uint64_t *z3Ptr
)
static inline void mul128To256(uint64_t a0, uint64_t a1,
uint64_t b0, uint64_t b1,
uint64_t *z0Ptr, uint64_t *z1Ptr,
uint64_t *z2Ptr, uint64_t *z3Ptr)
{
uint64_t z0, z1, z2, z3;
uint64_t more1, more2;
uint64_t z0, z1, z2;
uint64_t m0, m1, m2, n1, n2;
mul64To128( a1, b1, &z2, &z3 );
mul64To128( a1, b0, &z1, &more2 );
add128( z1, more2, 0, z2, &z1, &z2 );
mul64To128( a0, b0, &z0, &more1 );
add128( z0, more1, 0, z1, &z0, &z1 );
mul64To128( a0, b1, &more1, &more2 );
add128( more1, more2, 0, z2, &more1, &z2 );
add128( z0, z1, 0, more1, &z0, &z1 );
*z3Ptr = z3;
*z2Ptr = z2;
*z1Ptr = z1;
*z0Ptr = z0;
mul64To128(a1, b0, &m1, &m2);
mul64To128(a0, b1, &n1, &n2);
mul64To128(a1, b1, &z2, z3Ptr);
mul64To128(a0, b0, &z0, &z1);
add192( 0, m1, m2, 0, n1, n2, &m0, &m1, &m2);
add192(m0, m1, m2, z0, z1, z2, z0Ptr, z1Ptr, z2Ptr);
}
/*----------------------------------------------------------------------------
@ -794,4 +745,38 @@ static inline bool ne128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
return a0 != b0 || a1 != b1;
}
/*
* Similarly, comparisons of 192-bit values.
*/
static inline bool eq192(uint64_t a0, uint64_t a1, uint64_t a2,
uint64_t b0, uint64_t b1, uint64_t b2)
{
return ((a0 ^ b0) | (a1 ^ b1) | (a2 ^ b2)) == 0;
}
static inline bool le192(uint64_t a0, uint64_t a1, uint64_t a2,
uint64_t b0, uint64_t b1, uint64_t b2)
{
if (a0 != b0) {
return a0 < b0;
}
if (a1 != b1) {
return a1 < b1;
}
return a2 <= b2;
}
static inline bool lt192(uint64_t a0, uint64_t a1, uint64_t a2,
uint64_t b0, uint64_t b1, uint64_t b2)
{
if (a0 != b0) {
return a0 < b0;
}
if (a1 != b1) {
return a1 < b1;
}
return a2 < b2;
}
#endif

14
include/fpu/softfloat-types.h
View File

@ -147,8 +147,10 @@ typedef enum __attribute__((__packed__)) {
float_round_up = 2,
float_round_to_zero = 3,
float_round_ties_away = 4,
/* Not an IEEE rounding mode: round to the closest odd mantissa value */
/* Not an IEEE rounding mode: round to closest odd, overflow to max */
float_round_to_odd = 5,
/* Not an IEEE rounding mode: round to closest odd, overflow to inf */
float_round_to_odd_inf = 6,
} FloatRoundMode;
/*
@ -165,6 +167,14 @@ enum {
float_flag_output_denormal = 128
};
/*
* Rounding precision for floatx80.
*/
typedef enum __attribute__((__packed__)) {
floatx80_precision_x,
floatx80_precision_d,
floatx80_precision_s,
} FloatX80RoundPrec;
/*
* Floating Point Status. Individual architectures may maintain
@ -176,7 +186,7 @@ enum {
typedef struct float_status {
FloatRoundMode float_rounding_mode;
uint8_t float_exception_flags;
signed char floatx80_rounding_precision;
FloatX80RoundPrec floatx80_rounding_precision;
bool tininess_before_rounding;
/* should denormalised results go to zero and set the inexact flag? */
bool flush_to_zero;

17
include/fpu/softfloat.h
View File

@ -100,7 +100,10 @@ typedef enum {
| Routine to raise any or all of the software IEC/IEEE floating-point
| exception flags.
*----------------------------------------------------------------------------*/
void float_raise(uint8_t flags, float_status *status);
static inline void float_raise(uint8_t flags, float_status *status)
{
status->float_exception_flags |= flags;
}
/*----------------------------------------------------------------------------
| If `a' is denormal and we are in flush-to-zero mode then set the
@ -1149,7 +1152,7 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status);
| Floating-Point Arithmetic.
*----------------------------------------------------------------------------*/
floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign,
floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign,
int32_t zExp, uint64_t zSig0, uint64_t zSig1,
float_status *status);
@ -1162,7 +1165,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign,
| normalized.
*----------------------------------------------------------------------------*/
floatx80 normalizeRoundAndPackFloatx80(int8_t roundingPrecision,
floatx80 normalizeRoundAndPackFloatx80(FloatX80RoundPrec roundingPrecision,
bool zSign, int32_t zExp,
uint64_t zSig0, uint64_t zSig1,
float_status *status);
@ -1194,11 +1197,19 @@ float128 float128_round_to_int(float128, float_status *status);
float128 float128_add(float128, float128, float_status *status);
float128 float128_sub(float128, float128, float_status *status);
float128 float128_mul(float128, float128, float_status *status);
float128 float128_muladd(float128, float128, float128, int,
float_status *status);
float128 float128_div(float128, float128, float_status *status);
float128 float128_rem(float128, float128, float_status *status);
float128 float128_sqrt(float128, float_status *status);
FloatRelation float128_compare(float128, float128, float_status *status);
FloatRelation float128_compare_quiet(float128, float128, float_status *status);
float128 float128_min(float128, float128, float_status *status);
float128 float128_max(float128, float128, float_status *status);
float128 float128_minnum(float128, float128, float_status *status);
float128 float128_maxnum(float128, float128, float_status *status);
float128 float128_minnummag(float128, float128, float_status *status);
float128 float128_maxnummag(float128, float128, float_status *status);
bool float128_is_quiet_nan(float128, float_status *status);
bool float128_is_signaling_nan(float128, float_status *status);
float128 float128_silence_nan(float128, float_status *status);

30
include/glib-compat.h
View File

@ -19,12 +19,12 @@
/* Ask for warnings for anything that was marked deprecated in
* the defined version, or before. It is a candidate for rewrite.
*/
#define GLIB_VERSION_MIN_REQUIRED GLIB_VERSION_2_48
#define GLIB_VERSION_MIN_REQUIRED GLIB_VERSION_2_56
/* Ask for warnings if code tries to use function that did not
* exist in the defined version. These risk breaking builds
*/
#define GLIB_VERSION_MAX_ALLOWED GLIB_VERSION_2_48
#define GLIB_VERSION_MAX_ALLOWED GLIB_VERSION_2_56
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
@ -68,15 +68,6 @@
* without generating warnings.
*/
#if defined(_WIN32) && !GLIB_CHECK_VERSION(2, 50, 0)
/*
* g_poll has a problem on Windows when using
* timeouts < 10ms, so use wrapper.
*/
#define g_poll(fds, nfds, timeout) g_poll_fixed(fds, nfds, timeout)
gint g_poll_fixed(GPollFD *fds, guint nfds, gint timeout);
#endif
#if defined(G_OS_UNIX)
/*
* Note: The fallback implementation is not MT-safe, and it returns a copy of
@ -100,6 +91,23 @@ g_unix_get_passwd_entry_qemu(const gchar *user_name, GError **error)
}
#endif /* G_OS_UNIX */
static inline bool
qemu_g_test_slow(void)
{
static int cached = -1;
if (cached == -1) {
cached = g_test_slow() || getenv("G_TEST_SLOW") != NULL;
}
return cached;
}
#undef g_test_slow
#undef g_test_thorough
#undef g_test_quick
#define g_test_slow() qemu_g_test_slow()
#define g_test_thorough() qemu_g_test_slow()
#define g_test_quick() (!qemu_g_test_slow())
#pragma GCC diagnostic pop
#endif

9
include/hw/acpi/ghes.h
View File

@ -64,6 +64,7 @@ enum {
typedef struct AcpiGhesState {
uint64_t ghes_addr_le;
bool present; /* True if GHES is present at all on this board */
} AcpiGhesState;
void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker);
@ -72,4 +73,12 @@ void acpi_build_hest(GArray *table_data, BIOSLinker *linker,
void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s,
GArray *hardware_errors);
int acpi_ghes_record_errors(uint8_t notify, uint64_t error_physical_addr);
/**
* acpi_ghes_present: Report whether ACPI GHES table is present
*
* Returns: true if the system has an ACPI GHES table and it is
* safe to call acpi_ghes_record_errors() to record a memory error.
*/
bool acpi_ghes_present(void);
#endif

5
include/hw/acpi/ich9.h
View File

@ -24,10 +24,13 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/cpu.h"
#include "hw/acpi/pcihp.h"
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/acpi_dev_interface.h"
#include "hw/acpi/tco.h"
#define ACPI_PCIHP_ADDR_ICH9 0x0cc4
typedef struct ICH9LPCPMRegs {
/*
* In ich9 spec says that pm1_cnt register is 32bit width and
@ -53,6 +56,8 @@ typedef struct ICH9LPCPMRegs {
AcpiCpuHotplug gpe_cpu;
CPUHotplugState cpuhp_state;
bool use_acpi_hotplug_bridge;
AcpiPciHpState acpi_pci_hotplug;
MemHotplugState acpi_memory_hotplug;
uint8_t disable_s3;

3
include/hw/acpi/pcihp.h
View File

@ -55,7 +55,8 @@ typedef struct AcpiPciHpState {
} AcpiPciHpState;
void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root,
MemoryRegion *address_space_io, bool bridges_enabled);
MemoryRegion *address_space_io, bool bridges_enabled,
uint16_t io_base);
void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp);

4
include/hw/acpi/tpm.h
View File

@ -21,6 +21,8 @@
#include "hw/acpi/aml-build.h"
#include "sysemu/tpm.h"
#ifdef CONFIG_TPM
#define TPM_TIS_ADDR_BASE 0xFED40000
#define TPM_TIS_ADDR_SIZE 0x5000
@ -209,4 +211,6 @@ REG32(CRB_DATA_BUFFER, 0x80)
void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);
#endif /* CONFIG_TPM */
#endif /* HW_ACPI_TPM_H */

0
include/hw/misc/max111x.h → include/hw/adc/max111x.h
View File

0
include/hw/misc/zynq-xadc.h → include/hw/adc/zynq-xadc.h
View File

2
include/hw/arm/allwinner-h3.h
View File

@ -18,7 +18,7 @@
*/
/*
* The Allwinner H3 is a System on Chip containing four ARM Cortex A7
* The Allwinner H3 is a System on Chip containing four ARM Cortex-A7
* processor cores. Features and specifications include DDR2/DDR3 memory,
* SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
* various I/O modules.

2
include/hw/arm/armsse.h
View File

@ -198,6 +198,8 @@ struct ARMSSE {
MemoryRegion alias2;
MemoryRegion alias3[SSE_MAX_CPUS];
MemoryRegion sram[MAX_SRAM_BANKS];
MemoryRegion itcm;
MemoryRegion dtcm;
qemu_irq *exp_irqs[SSE_MAX_CPUS];
qemu_irq ppc0_irq;

2
include/hw/arm/armv7m.h
View File

@ -46,6 +46,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
* devices will be automatically layered on top of this view.)
* + Property "idau": IDAU interface (forwarded to CPU object)
* + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
* + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object)
* + Property "vfp": enable VFP (forwarded to CPU object)
* + Property "dsp": enable DSP (forwarded to CPU object)
* + Property "enable-bitband": expose bitbanded IO
@ -69,6 +70,7 @@ struct ARMv7MState {
MemoryRegion *board_memory;
Object *idau;
uint32_t init_svtor;
uint32_t init_nsvtor;
bool enable_bitband;
bool start_powered_off;
bool vfp;

3
include/hw/arm/aspeed_soc.h
View File

@ -21,6 +21,7 @@
#include "hw/rtc/aspeed_rtc.h"
#include "hw/i2c/aspeed_i2c.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/misc/aspeed_hace.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
@ -50,6 +51,7 @@ struct AspeedSoCState {
AspeedTimerCtrlState timerctrl;
AspeedI2CState i2c;
AspeedSCUState scu;
AspeedHACEState hace;
AspeedXDMAState xdma;
AspeedSMCState fmc;
AspeedSMCState spi[ASPEED_SPIS_NUM];
@ -133,6 +135,7 @@ enum {
ASPEED_DEV_XDMA,
ASPEED_DEV_EMMC,
ASPEED_DEV_KCS,
ASPEED_DEV_HACE,
};
#endif /* ASPEED_SOC_H */

3
include/hw/arm/bcm2835_peripherals.h
View File

@ -24,6 +24,7 @@
#include "hw/misc/bcm2835_mphi.h"
#include "hw/misc/bcm2835_thermal.h"
#include "hw/misc/bcm2835_cprman.h"
#include "hw/misc/bcm2835_powermgt.h"
#include "hw/sd/sdhci.h"
#include "hw/sd/bcm2835_sdhost.h"
#include "hw/gpio/bcm2835_gpio.h"
@ -48,7 +49,7 @@ struct BCM2835PeripheralState {
BCM2835MphiState mphi;
UnimplementedDeviceState txp;
UnimplementedDeviceState armtmr;
UnimplementedDeviceState powermgt;
BCM2835PowerMgtState powermgt;
BCM2835CprmanState cprman;
PL011State uart0;
BCM2835AuxState aux;

57
include/hw/arm/stm32f100_soc.h Normal file
View File

@ -0,0 +1,57 @@
/*
* STM32F100 SoC
*
* Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_ARM_STM32F100_SOC_H
#define HW_ARM_STM32F100_SOC_H
#include "hw/char/stm32f2xx_usart.h"
#include "hw/ssi/stm32f2xx_spi.h"
#include "hw/arm/armv7m.h"
#include "qom/object.h"
#define TYPE_STM32F100_SOC "stm32f100-soc"
OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
#define STM_NUM_USARTS 3
#define STM_NUM_SPIS 2
#define FLASH_BASE_ADDRESS 0x08000000
#define FLASH_SIZE (128 * 1024)
#define SRAM_BASE_ADDRESS 0x20000000
#define SRAM_SIZE (8 * 1024)
struct STM32F100State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
char *cpu_type;
ARMv7MState armv7m;
STM32F2XXUsartState usart[STM_NUM_USARTS];
STM32F2XXSPIState spi[STM_NUM_SPIS];
};
#endif

1
include/hw/arm/virt.h
View File

@ -147,6 +147,7 @@ struct VirtMachineState {
OnOffAuto acpi;
VirtGICType gic_version;
VirtIOMMUType iommu;
bool default_bus_bypass_iommu;
VirtMSIControllerType msi_controller;
uint16_t virtio_iommu_bdf;
struct arm_boot_info bootinfo;

3
include/hw/block/block.h
View File

@ -19,6 +19,7 @@
typedef struct BlockConf {
BlockBackend *blk;
OnOffAuto backend_defaults;
uint32_t physical_block_size;
uint32_t logical_block_size;
uint32_t min_io_size;
@ -48,6 +49,8 @@ static inline unsigned int get_physical_block_exp(BlockConf *conf)
}
#define DEFINE_BLOCK_PROPERTIES_BASE(_state, _conf) \
DEFINE_PROP_ON_OFF_AUTO("backend_defaults", _state, \
_conf.backend_defaults, ON_OFF_AUTO_AUTO), \
DEFINE_PROP_BLOCKSIZE("logical_block_size", _state, \
_conf.logical_block_size), \
DEFINE_PROP_BLOCKSIZE("physical_block_size", _state, \

2
include/hw/block/flash.h
View File

@ -74,6 +74,6 @@ typedef struct {
uint8_t ecc_digest(ECCState *s, uint8_t sample);
void ecc_reset(ECCState *s);
extern VMStateDescription vmstate_ecc_state;
extern const VMStateDescription vmstate_ecc_state;
#endif

7
include/hw/boards.h
View File

@ -26,7 +26,6 @@ OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE)
extern MachineState *current_machine;
void machine_run_board_init(MachineState *machine);
bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp);
bool machine_usb(MachineState *machine);
int machine_phandle_start(MachineState *machine);
bool machine_dump_guest_core(MachineState *machine);
@ -210,7 +209,7 @@ struct MachineClass {
void (*reset)(MachineState *state);
void (*wakeup)(MachineState *state);
int (*kvm_type)(MachineState *machine, const char *arg);
void (*smp_parse)(MachineState *ms, QemuOpts *opts);
void (*smp_parse)(MachineState *ms, SMPConfiguration *config, Error **errp);
BlockInterfaceType block_default_type;
int units_per_default_bus;
@ -282,6 +281,7 @@ typedef struct DeviceMemoryState {
*/
typedef struct CpuTopology {
unsigned int cpus;
unsigned int dies;
unsigned int cores;
unsigned int threads;
unsigned int sockets;
@ -353,6 +353,9 @@ struct MachineState {
} \
type_init(machine_initfn##_register_types)
extern GlobalProperty hw_compat_6_0[];
extern const size_t hw_compat_6_0_len;
extern GlobalProperty hw_compat_5_2[];
extern const size_t hw_compat_5_2_len;

1
include/hw/char/avr_usart.h
View File

@ -24,7 +24,6 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "hw/hw.h"
#include "qom/object.h"
/* Offsets of registers. */

37
include/hw/char/ibex_uart.h
View File

@ -31,43 +31,6 @@
#include "qemu/timer.h"
#include "qom/object.h"
REG32(INTR_STATE, 0x00)
FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
FIELD(INTR_STATE, TX_EMPTY, 2, 1)
FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
REG32(INTR_ENABLE, 0x04)
REG32(INTR_TEST, 0x08)
REG32(CTRL, 0x0C)
FIELD(CTRL, TX_ENABLE, 0, 1)
FIELD(CTRL, RX_ENABLE, 1, 1)
FIELD(CTRL, NF, 2, 1)
FIELD(CTRL, SLPBK, 4, 1)
FIELD(CTRL, LLPBK, 5, 1)
FIELD(CTRL, PARITY_EN, 6, 1)
FIELD(CTRL, PARITY_ODD, 7, 1)
FIELD(CTRL, RXBLVL, 8, 2)
FIELD(CTRL, NCO, 16, 16)
REG32(STATUS, 0x10)
FIELD(STATUS, TXFULL, 0, 1)
FIELD(STATUS, RXFULL, 1, 1)
FIELD(STATUS, TXEMPTY, 2, 1)
FIELD(STATUS, RXIDLE, 4, 1)
FIELD(STATUS, RXEMPTY, 5, 1)
REG32(RDATA, 0x14)
REG32(WDATA, 0x18)
REG32(FIFO_CTRL, 0x1c)
FIELD(FIFO_CTRL, RXRST, 0, 1)
FIELD(FIFO_CTRL, TXRST, 1, 1)
FIELD(FIFO_CTRL, RXILVL, 2, 3)
FIELD(FIFO_CTRL, TXILVL, 5, 2)
REG32(FIFO_STATUS, 0x20)
FIELD(FIFO_STATUS, TXLVL, 0, 5)
FIELD(FIFO_STATUS, RXLVL, 16, 5)
REG32(OVRD, 0x24)
REG32(VAL, 0x28)
REG32(TIMEOUT_CTRL, 0x2c)
#define IBEX_UART_TX_FIFO_SIZE 16
#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */

13
include/hw/char/lm32_juart.h
View File

@ -1,13 +0,0 @@
#ifndef QEMU_HW_CHAR_LM32_JUART_H
#define QEMU_HW_CHAR_LM32_JUART_H
#include "hw/qdev-core.h"
#define TYPE_LM32_JUART "lm32-juart"
uint32_t lm32_juart_get_jtx(DeviceState *d);
uint32_t lm32_juart_get_jrx(DeviceState *d);
void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx);
void lm32_juart_set_jrx(DeviceState *d, uint32_t jrx);
#endif /* QEMU_HW_CHAR_LM32_JUART_H */

74
include/hw/char/shakti_uart.h Normal file
View File

@ -0,0 +1,74 @@
/*
* SHAKTI UART
*
* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_SHAKTI_UART_H
#define HW_SHAKTI_UART_H
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#define SHAKTI_UART_BAUD 0x00
#define SHAKTI_UART_TX 0x04
#define SHAKTI_UART_RX 0x08
#define SHAKTI_UART_STATUS 0x0C
#define SHAKTI_UART_DELAY 0x10
#define SHAKTI_UART_CONTROL 0x14
#define SHAKTI_UART_INT_EN 0x18
#define SHAKTI_UART_IQ_CYCLES 0x1C
#define SHAKTI_UART_RX_THRES 0x20
#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0)
#define SHAKTI_UART_STATUS_TX_FULL (1 << 1)
#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
#define SHAKTI_UART_STATUS_RX_FULL (1 << 3)
/* 9600 8N1 is the default setting */
/* Reg value = (50000000 Hz)/(16 * 9600)*/
#define SHAKTI_UART_BAUD_DEFAULT 0x0145
#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
#define TYPE_SHAKTI_UART "shakti-uart"
#define SHAKTI_UART(obj) \
OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
typedef struct {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion mmio;
uint32_t uart_baud;
uint32_t uart_tx;
uint32_t uart_rx;
uint32_t uart_status;
uint32_t uart_delay;
uint32_t uart_control;
uint32_t uart_interrupt;
uint32_t uart_iq_cycles;
uint32_t uart_rx_threshold;
CharBackend chr;
} ShaktiUartState;
#endif /* HW_SHAKTI_UART_H */

11
include/hw/char/sifive_uart.h
View File

@ -21,6 +21,7 @@
#define HW_SIFIVE_UART_H
#include "chardev/char-fe.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qom/object.h"
@ -49,12 +50,10 @@ enum {
#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
#define SIFIVE_UART_RX_FIFO_SIZE 8
#define TYPE_SIFIVE_UART "riscv.sifive.uart"
typedef struct SiFiveUARTState SiFiveUARTState;
DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
TYPE_SIFIVE_UART)
OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
struct SiFiveUARTState {
/*< private >*/
@ -64,8 +63,8 @@ struct SiFiveUARTState {
qemu_irq irq;
MemoryRegion mmio;
CharBackend chr;
uint8_t rx_fifo[8];
unsigned int rx_fifo_len;
uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
uint8_t rx_fifo_len;
uint32_t ie;
uint32_t ip;
uint32_t txctrl;

2
include/hw/core/accel-cpu.h
View File

@ -32,7 +32,7 @@ typedef struct AccelCPUClass {
void (*cpu_class_init)(CPUClass *cc);
void (*cpu_instance_init)(CPUState *cpu);
void (*cpu_realizefn)(CPUState *cpu, Error **errp);
bool (*cpu_realizefn)(CPUState *cpu, Error **errp);
} AccelCPUClass;
#endif /* ACCEL_CPU_H */

126
include/hw/core/cpu.h
View File

@ -80,6 +80,9 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
/* see sysemu-cpu-ops.h */
struct SysemuCPUOps;
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@ -87,16 +90,9 @@ struct AccelCPUClass;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
* not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@ -105,24 +101,11 @@ struct AccelCPUClass;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
* @get_phys_page_debug: Callback for obtaining a physical address.
* @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
* @write_elf32_note: Callback for writing a CPU-specific ELF note to a
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
* @vmsd: State description for migration.
* @gdb_adjust_breakpoint: Callback for adjusting the address of a
* breakpoint. Used by AVR to handle a gdb mis-feature with
* its Harvard architecture split code and data.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@ -150,34 +133,15 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
const VMStateDescription *vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
@ -190,8 +154,17 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
/* when system emulation is not available, this pointer is NULL */
const struct SysemuCPUOps *sysemu_ops;
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
const struct TCGCPUOps *tcg_ops;
/*
* if not NULL, this is called in order for the CPUClass to initialize
* class data that depends on the accelerator, see accel/accel-common.c.
*/
void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
};
/*
@ -258,6 +231,7 @@ struct KVMState;
struct kvm_run;
struct hax_vcpu_state;
struct hvf_vcpu_state;
#define TB_JMP_CACHE_BITS 12
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
@ -336,6 +310,10 @@ struct qemu_work_item;
* @ignore_memory_transaction_failures: Cached copy of the MachineState
* flag of the same name: allows the board to suppress calling of the
* CPU do_transaction_failed hook function.
* @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty
* ring is enabled.
* @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU
* dirty ring structure.
*
* State of one CPU core or thread.
*/
@ -409,9 +387,12 @@ struct CPUState {
*/
uintptr_t mem_io_pc;
/* Only used in KVM */
int kvm_fd;
struct KVMState *kvm_state;
struct kvm_run *kvm_run;
struct kvm_dirty_gfn *kvm_dirty_gfns;
uint32_t kvm_fetch_index;
/* Used for events with 'vcpu' and *without* the 'disabled' properties */
DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS);
@ -445,7 +426,7 @@ struct CPUState {
struct hax_vcpu_state *hax_vcpu;
int hvf_fd;
struct hvf_vcpu_state *hvf;
/* track IOMMUs whose translations we've cached in the TCG TLB */
GArray *iommu_notifiers;
@ -571,16 +552,6 @@ enum CPUDumpFlags {
*/
void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
/**
* cpu_dump_statistics:
* @cpu: The CPU whose state is to be dumped.
* @flags: Flags what to dump.
*
* Dump CPU statistics to the current monitor if we have one, else to
* stdout.
*/
void cpu_dump_statistics(CPUState *cpu, int flags);
#ifndef CONFIG_USER_ONLY
/**
* cpu_get_phys_page_attrs_debug:
@ -595,18 +566,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->get_phys_page_attrs_debug) {
return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
return cc->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@ -618,12 +579,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
{
MemTxAttrs attrs = {};
return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@ -632,17 +588,16 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
if (cc->asidx_from_attrs) {
ret = cc->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
}
/**
* cpu_virtio_is_big_endian:
* @cpu: CPU
* Returns %true if a CPU which supports runtime configurable endianness
* is currently big-endian.
*/
bool cpu_virtio_is_big_endian(CPUState *cpu);
#endif /* CONFIG_USER_ONLY */
@ -1105,10 +1060,8 @@ bool target_words_bigendian(void);
#ifdef NEED_CPU_H
#ifdef CONFIG_SOFTMMU
extern const VMStateDescription vmstate_cpu_common;
#else
#define vmstate_cpu_common vmstate_dummy
#endif
#define VMSTATE_CPU() { \
.name = "parent_obj", \
@ -1117,6 +1070,7 @@ extern const VMStateDescription vmstate_cpu_common;
.flags = VMS_STRUCT, \
.offset = 0, \
}
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */

92
include/hw/core/sysemu-cpu-ops.h Normal file
View File

@ -0,0 +1,92 @@
/*
* CPU operations specific to system emulation
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef SYSEMU_CPU_OPS_H
#define SYSEMU_CPU_OPS_H
#include "hw/core/cpu.h"
/*
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
/**
* @get_memory_mapping: Callback for obtaining the memory mappings.
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
/**
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
*/
bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
/**
* @get_phys_page_attrs_debug: Callback for obtaining a physical address
* and the associated memory transaction attributes to use for the
* access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
*/
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
*/
int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @write_elf32_note: Callback for writing a CPU-specific ELF note to a
* 32-bit VM coredump.
*/
int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
/**
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
*/
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
/**
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
*/
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
/**
* @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 64-bit VM coredump.
*/
int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
* Non-configurable CPUs can use the default implementation of this method.
* This method should not be used by any callers other than the pre-1.0
* virtio devices.
*/
bool (*virtio_is_big_endian)(CPUState *cpu);
/**
* @legacy_vmsd: Legacy state for migration.
* Do not use in new targets, use #DeviceClass::vmsd instead.
*/
const VMStateDescription *legacy_vmsd;
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */

6
include/hw/core/tcg-cpu-ops.h
View File

@ -88,6 +88,12 @@ struct TCGCPUOps {
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
/**
* @debug_check_breakpoint: return true if the architectural
* breakpoint whose PC has matched should really fire.
*/
bool (*debug_check_breakpoint)(CPUState *cpu);
/**
* @io_recompile_replay_branch: Callback for cpu_io_recompile.
*

12
include/hw/display/edid.h
View File

@ -11,6 +11,7 @@ typedef struct qemu_edid_info {
uint32_t prefy;
uint32_t maxx;
uint32_t maxy;
uint32_t refresh_rate;
} qemu_edid_info;
void qemu_edid_generate(uint8_t *edid, size_t size,
@ -21,10 +22,11 @@ void qemu_edid_region_io(MemoryRegion *region, Object *owner,
uint32_t qemu_edid_dpi_to_mm(uint32_t dpi, uint32_t res);
#define DEFINE_EDID_PROPERTIES(_state, _edid_info) \
DEFINE_PROP_UINT32("xres", _state, _edid_info.prefx, 0), \
DEFINE_PROP_UINT32("yres", _state, _edid_info.prefy, 0), \
DEFINE_PROP_UINT32("xmax", _state, _edid_info.maxx, 0), \
DEFINE_PROP_UINT32("ymax", _state, _edid_info.maxy, 0)
#define DEFINE_EDID_PROPERTIES(_state, _edid_info) \
DEFINE_PROP_UINT32("xres", _state, _edid_info.prefx, 0), \
DEFINE_PROP_UINT32("yres", _state, _edid_info.prefy, 0), \
DEFINE_PROP_UINT32("xmax", _state, _edid_info.maxx, 0), \
DEFINE_PROP_UINT32("ymax", _state, _edid_info.maxy, 0), \
DEFINE_PROP_UINT32("refresh_rate", _state, _edid_info.refresh_rate, 0)
#endif /* EDID_H */

42
include/hw/display/milkymist_tmu2.h
View File

@ -1,42 +0,0 @@
/*
* QEMU model of the Milkymist texture mapping unit.
*
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
* Copyright (c) 2010 Sebastien Bourdeauducq
* <sebastien.bourdeauducq@lekernel.net>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*
* Specification available at:
* http://milkymist.walle.cc/socdoc/tmu2.pdf
*
*/
#ifndef HW_DISPLAY_MILKYMIST_TMU2_H
#define HW_DISPLAY_MILKYMIST_TMU2_H
#include "exec/hwaddr.h"
#include "hw/qdev-core.h"
#if defined(CONFIG_X11) && defined(CONFIG_OPENGL)
DeviceState *milkymist_tmu2_create(hwaddr base, qemu_irq irq);
#else
static inline DeviceState *milkymist_tmu2_create(hwaddr base, qemu_irq irq)
{
return NULL;
}
#endif
#endif /* HW_DISPLAY_MILKYMIST_TMU2_H */

6
include/hw/display/vga.h
View File

@ -11,6 +11,12 @@
#include "exec/hwaddr.h"
/*
* modules can reference this symbol to avoid being loaded
* into system emulators without vga support
*/
extern bool have_vga;
enum vga_retrace_method {
VGA_RETRACE_DUMB,
VGA_RETRACE_PRECISE

8
include/hw/elf_ops.h
View File

@ -368,14 +368,6 @@ static int glue(load_elf, SZ)(const char *name, int fd,
}
}
break;
case EM_MOXIE:
if (ehdr.e_machine != EM_MOXIE) {
if (ehdr.e_machine != EM_MOXIE_OLD) {
ret = ELF_LOAD_WRONG_ARCH;
goto fail;
}
}
break;
case EM_MIPS:
case EM_NANOMIPS:
if ((ehdr.e_machine != EM_MIPS) &&

14
include/hw/firmware/smbios.h
View File

@ -258,6 +258,17 @@ struct smbios_type_32 {
uint8_t boot_status;
} QEMU_PACKED;
/* SMBIOS type 41 - Onboard Devices Extended Information */
struct smbios_type_41 {
struct smbios_structure_header header;
uint8_t reference_designation_str;
uint8_t device_type;
uint8_t device_type_instance;
uint16_t segment_group_number;
uint8_t bus_number;
uint8_t device_number;
} QEMU_PACKED;
/* SMBIOS type 127 -- End-of-table */
struct smbios_type_127 {
struct smbios_structure_header header;
@ -273,5 +284,6 @@ void smbios_get_tables(MachineState *ms,
const struct smbios_phys_mem_area *mem_array,
const unsigned int mem_array_size,
uint8_t **tables, size_t *tables_len,
uint8_t **anchor, size_t *anchor_len);
uint8_t **anchor, size_t *anchor_len,
Error **errp);
#endif /* QEMU_SMBIOS_H */

63
include/hw/i2c/i2c.h
View File

@ -16,6 +16,7 @@ enum i2c_event {
I2C_NACK /* Masker NACKed a receive byte. */
};
typedef struct I2CNodeList I2CNodeList;
#define TYPE_I2C_SLAVE "i2c-slave"
OBJECT_DECLARE_TYPE(I2CSlave, I2CSlaveClass,
@ -39,6 +40,16 @@ struct I2CSlaveClass {
* return code is not used and should be zero.
*/
int (*event)(I2CSlave *s, enum i2c_event event);
/*
* Check if this device matches the address provided. Returns bool of
* true if it matches (or broadcast), and updates the device list, false
* otherwise.
*
* If broadcast is true, match should add the device and return true.
*/
bool (*match_and_add)(I2CSlave *candidate, uint8_t address, bool broadcast,
I2CNodeList *current_devs);
};
struct I2CSlave {
@ -58,22 +69,58 @@ struct I2CNode {
QLIST_ENTRY(I2CNode) next;
};
typedef QLIST_HEAD(I2CNodeList, I2CNode) I2CNodeList;
struct I2CBus {
BusState qbus;
QLIST_HEAD(, I2CNode) current_devs;
I2CNodeList current_devs;
uint8_t saved_address;
bool broadcast;
};
I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
int i2c_bus_busy(I2CBus *bus);
int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv);
/**
* i2c_start_transfer: start a transfer on an I2C bus.
*
* @bus: #I2CBus to be used
* @address: address of the slave
* @is_recv: indicates the transfer direction
*
* When @is_recv is a known boolean constant, use the
* i2c_start_recv() or i2c_start_send() helper instead.
*
* Returns: 0 on success, -1 on error
*/
int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv);
/**
* i2c_start_recv: start a 'receive' transfer on an I2C bus.
*
* @bus: #I2CBus to be used
* @address: address of the slave
*
* Returns: 0 on success, -1 on error
*/
int i2c_start_recv(I2CBus *bus, uint8_t address);
/**
* i2c_start_send: start a 'send' transfer on an I2C bus.
*
* @bus: #I2CBus to be used
* @address: address of the slave
*
* Returns: 0 on success, -1 on error
*/
int i2c_start_send(I2CBus *bus, uint8_t address);
void i2c_end_transfer(I2CBus *bus);
void i2c_nack(I2CBus *bus);
int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send);
int i2c_send(I2CBus *bus, uint8_t data);
uint8_t i2c_recv(I2CBus *bus);
bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
I2CNodeList *current_devs);
/**
* Create an I2C slave device on the heap.
@ -127,8 +174,12 @@ I2CSlave *i2c_slave_create_simple(I2CBus *bus, const char *name, uint8_t addr);
*/
bool i2c_slave_realize_and_unref(I2CSlave *dev, I2CBus *bus, Error **errp);
/* lm832x.c */
void lm832x_key_event(DeviceState *dev, int key, int state);
/**
* Set the I2C bus address of a slave device
* @dev: I2C slave device
* @address: I2C address of the slave when put on a bus
*/
void i2c_slave_set_address(I2CSlave *dev, uint8_t address);
extern const VMStateDescription vmstate_i2c_slave;

19
include/hw/i2c/i2c_mux_pca954x.h Normal file
View File

@ -0,0 +1,19 @@
#ifndef QEMU_I2C_MUX_PCA954X
#define QEMU_I2C_MUX_PCA954X
#include "hw/i2c/i2c.h"
#define TYPE_PCA9546 "pca9546"
#define TYPE_PCA9548 "pca9548"
/**
* Retrieves the i2c bus associated with the specified channel on this i2c
* mux.
* @mux: an i2c mux device.
* @channel: the i2c channel requested
*
* Returns: a pointer to the associated i2c bus.
*/
I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel);
#endif

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/*
* QEMU PMBus device emulation
*
* Copyright 2021 Google LLC
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_PMBUS_DEVICE_H
#define HW_PMBUS_DEVICE_H
#include "qemu/bitops.h"
#include "hw/i2c/smbus_slave.h"
enum pmbus_registers {
PMBUS_PAGE = 0x00, /* R/W byte */
PMBUS_OPERATION = 0x01, /* R/W byte */
PMBUS_ON_OFF_CONFIG = 0x02, /* R/W byte */
PMBUS_CLEAR_FAULTS = 0x03, /* Send Byte */
PMBUS_PHASE = 0x04, /* R/W byte */
PMBUS_PAGE_PLUS_WRITE = 0x05, /* Block Write-only */
PMBUS_PAGE_PLUS_READ = 0x06, /* Block Read-only */
PMBUS_WRITE_PROTECT = 0x10, /* R/W byte */
PMBUS_STORE_DEFAULT_ALL = 0x11, /* Send Byte */
PMBUS_RESTORE_DEFAULT_ALL = 0x12, /* Send Byte */
PMBUS_STORE_DEFAULT_CODE = 0x13, /* Write-only Byte */
PMBUS_RESTORE_DEFAULT_CODE = 0x14, /* Write-only Byte */
PMBUS_STORE_USER_ALL = 0x15, /* Send Byte */
PMBUS_RESTORE_USER_ALL = 0x16, /* Send Byte */
PMBUS_STORE_USER_CODE = 0x17, /* Write-only Byte */
PMBUS_RESTORE_USER_CODE = 0x18, /* Write-only Byte */
PMBUS_CAPABILITY = 0x19, /* Read-Only byte */
PMBUS_QUERY = 0x1A, /* Write-Only */
PMBUS_SMBALERT_MASK = 0x1B, /* Block read, Word write */
PMBUS_VOUT_MODE = 0x20, /* R/W byte */
PMBUS_VOUT_COMMAND = 0x21, /* R/W word */
PMBUS_VOUT_TRIM = 0x22, /* R/W word */
PMBUS_VOUT_CAL_OFFSET = 0x23, /* R/W word */
PMBUS_VOUT_MAX = 0x24, /* R/W word */
PMBUS_VOUT_MARGIN_HIGH = 0x25, /* R/W word */
PMBUS_VOUT_MARGIN_LOW = 0x26, /* R/W word */
PMBUS_VOUT_TRANSITION_RATE = 0x27, /* R/W word */
PMBUS_VOUT_DROOP = 0x28, /* R/W word */
PMBUS_VOUT_SCALE_LOOP = 0x29, /* R/W word */
PMBUS_VOUT_SCALE_MONITOR = 0x2A, /* R/W word */
PMBUS_COEFFICIENTS = 0x30, /* Read-only block 5 bytes */
PMBUS_POUT_MAX = 0x31, /* R/W word */
PMBUS_MAX_DUTY = 0x32, /* R/W word */
PMBUS_FREQUENCY_SWITCH = 0x33, /* R/W word */
PMBUS_VIN_ON = 0x35, /* R/W word */
PMBUS_VIN_OFF = 0x36, /* R/W word */
PMBUS_INTERLEAVE = 0x37, /* R/W word */
PMBUS_IOUT_CAL_GAIN = 0x38, /* R/W word */
PMBUS_IOUT_CAL_OFFSET = 0x39, /* R/W word */
PMBUS_FAN_CONFIG_1_2 = 0x3A, /* R/W byte */
PMBUS_FAN_COMMAND_1 = 0x3B, /* R/W word */
PMBUS_FAN_COMMAND_2 = 0x3C, /* R/W word */
PMBUS_FAN_CONFIG_3_4 = 0x3D, /* R/W byte */
PMBUS_FAN_COMMAND_3 = 0x3E, /* R/W word */
PMBUS_FAN_COMMAND_4 = 0x3F, /* R/W word */
PMBUS_VOUT_OV_FAULT_LIMIT = 0x40, /* R/W word */
PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41, /* R/W byte */
PMBUS_VOUT_OV_WARN_LIMIT = 0x42, /* R/W word */
PMBUS_VOUT_UV_WARN_LIMIT = 0x43, /* R/W word */
PMBUS_VOUT_UV_FAULT_LIMIT = 0x44, /* R/W word */
PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45, /* R/W byte */
PMBUS_IOUT_OC_FAULT_LIMIT = 0x46, /* R/W word */
PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47, /* R/W byte */
PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48, /* R/W word */
PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49, /* R/W byte */
PMBUS_IOUT_OC_WARN_LIMIT = 0x4A, /* R/W word */
PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B, /* R/W word */
PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C, /* R/W byte */
PMBUS_OT_FAULT_LIMIT = 0x4F, /* R/W word */
PMBUS_OT_FAULT_RESPONSE = 0x50, /* R/W byte */
PMBUS_OT_WARN_LIMIT = 0x51, /* R/W word */
PMBUS_UT_WARN_LIMIT = 0x52, /* R/W word */
PMBUS_UT_FAULT_LIMIT = 0x53, /* R/W word */
PMBUS_UT_FAULT_RESPONSE = 0x54, /* R/W byte */
PMBUS_VIN_OV_FAULT_LIMIT = 0x55, /* R/W word */
PMBUS_VIN_OV_FAULT_RESPONSE = 0x56, /* R/W byte */
PMBUS_VIN_OV_WARN_LIMIT = 0x57, /* R/W word */
PMBUS_VIN_UV_WARN_LIMIT = 0x58, /* R/W word */
PMBUS_VIN_UV_FAULT_LIMIT = 0x59, /* R/W word */
PMBUS_VIN_UV_FAULT_RESPONSE = 0x5A, /* R/W byte */
PMBUS_IIN_OC_FAULT_LIMIT = 0x5B, /* R/W word */
PMBUS_IIN_OC_FAULT_RESPONSE = 0x5C, /* R/W byte */
PMBUS_IIN_OC_WARN_LIMIT = 0x5D, /* R/W word */
PMBUS_POWER_GOOD_ON = 0x5E, /* R/W word */
PMBUS_POWER_GOOD_OFF = 0x5F, /* R/W word */
PMBUS_TON_DELAY = 0x60, /* R/W word */
PMBUS_TON_RISE = 0x61, /* R/W word */
PMBUS_TON_MAX_FAULT_LIMIT = 0x62, /* R/W word */
PMBUS_TON_MAX_FAULT_RESPONSE = 0x63, /* R/W byte */
PMBUS_TOFF_DELAY = 0x64, /* R/W word */
PMBUS_TOFF_FALL = 0x65, /* R/W word */
PMBUS_TOFF_MAX_WARN_LIMIT = 0x66, /* R/W word */
PMBUS_POUT_OP_FAULT_LIMIT = 0x68, /* R/W word */
PMBUS_POUT_OP_FAULT_RESPONSE = 0x69, /* R/W byte */
PMBUS_POUT_OP_WARN_LIMIT = 0x6A, /* R/W word */
PMBUS_PIN_OP_WARN_LIMIT = 0x6B, /* R/W word */
PMBUS_STATUS_BYTE = 0x78, /* R/W byte */
PMBUS_STATUS_WORD = 0x79, /* R/W word */
PMBUS_STATUS_VOUT = 0x7A, /* R/W byte */
PMBUS_STATUS_IOUT = 0x7B, /* R/W byte */
PMBUS_STATUS_INPUT = 0x7C, /* R/W byte */
PMBUS_STATUS_TEMPERATURE = 0x7D, /* R/W byte */
PMBUS_STATUS_CML = 0x7E, /* R/W byte */
PMBUS_STATUS_OTHER = 0x7F, /* R/W byte */
PMBUS_STATUS_MFR_SPECIFIC = 0x80, /* R/W byte */
PMBUS_STATUS_FANS_1_2 = 0x81, /* R/W byte */
PMBUS_STATUS_FANS_3_4 = 0x82, /* R/W byte */
PMBUS_READ_EIN = 0x86, /* Read-Only block 5 bytes */
PMBUS_READ_EOUT = 0x87, /* Read-Only block 5 bytes */
PMBUS_READ_VIN = 0x88, /* Read-Only word */
PMBUS_READ_IIN = 0x89, /* Read-Only word */
PMBUS_READ_VCAP = 0x8A, /* Read-Only word */
PMBUS_READ_VOUT = 0x8B, /* Read-Only word */
PMBUS_READ_IOUT = 0x8C, /* Read-Only word */
PMBUS_READ_TEMPERATURE_1 = 0x8D, /* Read-Only word */
PMBUS_READ_TEMPERATURE_2 = 0x8E, /* Read-Only word */
PMBUS_READ_TEMPERATURE_3 = 0x8F, /* Read-Only word */
PMBUS_READ_FAN_SPEED_1 = 0x90, /* Read-Only word */
PMBUS_READ_FAN_SPEED_2 = 0x91, /* Read-Only word */
PMBUS_READ_FAN_SPEED_3 = 0x92, /* Read-Only word */
PMBUS_READ_FAN_SPEED_4 = 0x93, /* Read-Only word */
PMBUS_READ_DUTY_CYCLE = 0x94, /* Read-Only word */
PMBUS_READ_FREQUENCY = 0x95, /* Read-Only word */
PMBUS_READ_POUT = 0x96, /* Read-Only word */
PMBUS_READ_PIN = 0x97, /* Read-Only word */
PMBUS_REVISION = 0x98, /* Read-Only byte */
PMBUS_MFR_ID = 0x99, /* R/W block */
PMBUS_MFR_MODEL = 0x9A, /* R/W block */
PMBUS_MFR_REVISION = 0x9B, /* R/W block */
PMBUS_MFR_LOCATION = 0x9C, /* R/W block */
PMBUS_MFR_DATE = 0x9D, /* R/W block */
PMBUS_MFR_SERIAL = 0x9E, /* R/W block */
PMBUS_APP_PROFILE_SUPPORT = 0x9F, /* Read-Only block-read */
PMBUS_MFR_VIN_MIN = 0xA0, /* Read-Only word */
PMBUS_MFR_VIN_MAX = 0xA1, /* Read-Only word */
PMBUS_MFR_IIN_MAX = 0xA2, /* Read-Only word */
PMBUS_MFR_PIN_MAX = 0xA3, /* Read-Only word */
PMBUS_MFR_VOUT_MIN = 0xA4, /* Read-Only word */
PMBUS_MFR_VOUT_MAX = 0xA5, /* Read-Only word */
PMBUS_MFR_IOUT_MAX = 0xA6, /* Read-Only word */
PMBUS_MFR_POUT_MAX = 0xA7, /* Read-Only word */
PMBUS_MFR_TAMBIENT_MAX = 0xA8, /* Read-Only word */
PMBUS_MFR_TAMBIENT_MIN = 0xA9, /* Read-Only word */
PMBUS_MFR_EFFICIENCY_LL = 0xAA, /* Read-Only block 14 bytes */
PMBUS_MFR_EFFICIENCY_HL = 0xAB, /* Read-Only block 14 bytes */
PMBUS_MFR_PIN_ACCURACY = 0xAC, /* Read-Only byte */
PMBUS_IC_DEVICE_ID = 0xAD, /* Read-Only block-read */
PMBUS_IC_DEVICE_REV = 0xAE, /* Read-Only block-read */
PMBUS_MFR_MAX_TEMP_1 = 0xC0, /* R/W word */
PMBUS_MFR_MAX_TEMP_2 = 0xC1, /* R/W word */
PMBUS_MFR_MAX_TEMP_3 = 0xC2, /* R/W word */
};
/* STATUS_WORD */
#define PB_STATUS_VOUT BIT(15)
#define PB_STATUS_IOUT_POUT BIT(14)
#define PB_STATUS_INPUT BIT(13)
#define PB_STATUS_WORD_MFR BIT(12)
#define PB_STATUS_POWER_GOOD_N BIT(11)
#define PB_STATUS_FAN BIT(10)
#define PB_STATUS_OTHER BIT(9)
#define PB_STATUS_UNKNOWN BIT(8)
/* STATUS_BYTE */
#define PB_STATUS_BUSY BIT(7)
#define PB_STATUS_OFF BIT(6)
#define PB_STATUS_VOUT_OV BIT(5)
#define PB_STATUS_IOUT_OC BIT(4)
#define PB_STATUS_VIN_UV BIT(3)
#define PB_STATUS_TEMPERATURE BIT(2)
#define PB_STATUS_CML BIT(1)
#define PB_STATUS_NONE_ABOVE BIT(0)
/* STATUS_VOUT */
#define PB_STATUS_VOUT_OV_FAULT BIT(7) /* Output Overvoltage Fault */
#define PB_STATUS_VOUT_OV_WARN BIT(6) /* Output Overvoltage Warning */
#define PB_STATUS_VOUT_UV_WARN BIT(5) /* Output Undervoltage Warning */
#define PB_STATUS_VOUT_UV_FAULT BIT(4) /* Output Undervoltage Fault */
#define PB_STATUS_VOUT_MAX BIT(3)
#define PB_STATUS_VOUT_TON_MAX_FAULT BIT(2)
#define PB_STATUS_VOUT_TOFF_MAX_WARN BIT(1)
/* STATUS_IOUT */
#define PB_STATUS_IOUT_OC_FAULT BIT(7) /* Output Overcurrent Fault */
#define PB_STATUS_IOUT_OC_LV_FAULT BIT(6) /* Output OC And Low Voltage Fault */
#define PB_STATUS_IOUT_OC_WARN BIT(5) /* Output Overcurrent Warning */
#define PB_STATUS_IOUT_UC_FAULT BIT(4) /* Output Undercurrent Fault */
#define PB_STATUS_CURR_SHARE BIT(3) /* Current Share Fault */
#define PB_STATUS_PWR_LIM_MODE BIT(2) /* In Power Limiting Mode */
#define PB_STATUS_POUT_OP_FAULT BIT(1) /* Output Overpower Fault */
#define PB_STATUS_POUT_OP_WARN BIT(0) /* Output Overpower Warning */
/* STATUS_INPUT */
#define PB_STATUS_INPUT_VIN_OV_FAULT BIT(7) /* Input Overvoltage Fault */
#define PB_STATUS_INPUT_VIN_OV_WARN BIT(6) /* Input Overvoltage Warning */
#define PB_STATUS_INPUT_VIN_UV_WARN BIT(5) /* Input Undervoltage Warning */
#define PB_STATUS_INPUT_VIN_UV_FAULT BIT(4) /* Input Undervoltage Fault */
#define PB_STATUS_INPUT_IIN_OC_FAULT BIT(2) /* Input Overcurrent Fault */
#define PB_STATUS_INPUT_IIN_OC_WARN BIT(1) /* Input Overcurrent Warning */
#define PB_STATUS_INPUT_PIN_OP_WARN BIT(0) /* Input Overpower Warning */
/* STATUS_TEMPERATURE */
#define PB_STATUS_OT_FAULT BIT(7) /* Overtemperature Fault */
#define PB_STATUS_OT_WARN BIT(6) /* Overtemperature Warning */
#define PB_STATUS_UT_WARN BIT(5) /* Undertemperature Warning */
#define PB_STATUS_UT_FAULT BIT(4) /* Undertemperature Fault */
/* STATUS_CML */
#define PB_CML_FAULT_INVALID_CMD BIT(7) /* Invalid/Unsupported Command */
#define PB_CML_FAULT_INVALID_DATA BIT(6) /* Invalid/Unsupported Data */
#define PB_CML_FAULT_PEC BIT(5) /* Packet Error Check Failed */
#define PB_CML_FAULT_MEMORY BIT(4) /* Memory Fault Detected */
#define PB_CML_FAULT_PROCESSOR BIT(3) /* Processor Fault Detected */
#define PB_CML_FAULT_OTHER_COMM BIT(1) /* Other communication fault */
#define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) /* Other Memory Or Logic Fault */
/* OPERATION*/
#define PB_OP_ON BIT(7) /* PSU is switched on */
#define PB_OP_MARGIN_HIGH BIT(5) /* PSU vout is set to margin high */
#define PB_OP_MARGIN_LOW BIT(4) /* PSU vout is set to margin low */
/* PAGES */
#define PB_MAX_PAGES 0x1F
#define PB_ALL_PAGES 0xFF
#define TYPE_PMBUS_DEVICE "pmbus-device"
OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass,
PMBUS_DEVICE)
/* flags */
#define PB_HAS_COEFFICIENTS BIT_ULL(9)
#define PB_HAS_VIN BIT_ULL(10)
#define PB_HAS_VOUT BIT_ULL(11)
#define PB_HAS_VOUT_MARGIN BIT_ULL(12)
#define PB_HAS_VIN_RATING BIT_ULL(13)
#define PB_HAS_VOUT_RATING BIT_ULL(14)
#define PB_HAS_VOUT_MODE BIT_ULL(15)
#define PB_HAS_IOUT BIT_ULL(21)
#define PB_HAS_IIN BIT_ULL(22)
#define PB_HAS_IOUT_RATING BIT_ULL(23)
#define PB_HAS_IIN_RATING BIT_ULL(24)
#define PB_HAS_IOUT_GAIN BIT_ULL(25)
#define PB_HAS_POUT BIT_ULL(30)
#define PB_HAS_PIN BIT_ULL(31)
#define PB_HAS_EIN BIT_ULL(32)
#define PB_HAS_EOUT BIT_ULL(33)
#define PB_HAS_POUT_RATING BIT_ULL(34)
#define PB_HAS_PIN_RATING BIT_ULL(35)
#define PB_HAS_TEMPERATURE BIT_ULL(40)
#define PB_HAS_TEMP2 BIT_ULL(41)
#define PB_HAS_TEMP3 BIT_ULL(42)
#define PB_HAS_TEMP_RATING BIT_ULL(43)
#define PB_HAS_MFR_INFO BIT_ULL(50)
struct PMBusDeviceClass {
SMBusDeviceClass parent_class;
uint8_t device_num_pages;
/**
* Implement quick_cmd, receive byte, and write_data to support non-standard
* PMBus functionality
*/
void (*quick_cmd)(PMBusDevice *dev, uint8_t read);
int (*write_data)(PMBusDevice *dev, const uint8_t *buf, uint8_t len);
uint8_t (*receive_byte)(PMBusDevice *dev);
};
/*
* According to the spec, each page may offer the full range of PMBus commands
* available for each output or non-PMBus device.
* Therefore, we can't assume that any registers will always be the same across
* all pages.
* The page 0xFF is intended for writes to all pages
*/
typedef struct PMBusPage {
uint64_t page_flags;
uint8_t page; /* R/W byte */
uint8_t operation; /* R/W byte */
uint8_t on_off_config; /* R/W byte */
uint8_t write_protect; /* R/W byte */
uint8_t phase; /* R/W byte */
uint8_t vout_mode; /* R/W byte */
uint16_t vout_command; /* R/W word */
uint16_t vout_trim; /* R/W word */
uint16_t vout_cal_offset; /* R/W word */
uint16_t vout_max; /* R/W word */
uint16_t vout_margin_high; /* R/W word */
uint16_t vout_margin_low; /* R/W word */
uint16_t vout_transition_rate; /* R/W word */
uint16_t vout_droop; /* R/W word */
uint16_t vout_scale_loop; /* R/W word */
uint16_t vout_scale_monitor; /* R/W word */
uint8_t coefficients[5]; /* Read-only block 5 bytes */
uint16_t pout_max; /* R/W word */
uint16_t max_duty; /* R/W word */
uint16_t frequency_switch; /* R/W word */
uint16_t vin_on; /* R/W word */
uint16_t vin_off; /* R/W word */
uint16_t iout_cal_gain; /* R/W word */
uint16_t iout_cal_offset; /* R/W word */
uint8_t fan_config_1_2; /* R/W byte */
uint16_t fan_command_1; /* R/W word */
uint16_t fan_command_2; /* R/W word */
uint8_t fan_config_3_4; /* R/W byte */
uint16_t fan_command_3; /* R/W word */
uint16_t fan_command_4; /* R/W word */
uint16_t vout_ov_fault_limit; /* R/W word */
uint8_t vout_ov_fault_response; /* R/W byte */
uint16_t vout_ov_warn_limit; /* R/W word */
uint16_t vout_uv_warn_limit; /* R/W word */
uint16_t vout_uv_fault_limit; /* R/W word */
uint8_t vout_uv_fault_response; /* R/W byte */
uint16_t iout_oc_fault_limit; /* R/W word */
uint8_t iout_oc_fault_response; /* R/W byte */
uint16_t iout_oc_lv_fault_limit; /* R/W word */
uint8_t iout_oc_lv_fault_response; /* R/W byte */
uint16_t iout_oc_warn_limit; /* R/W word */
uint16_t iout_uc_fault_limit; /* R/W word */
uint8_t iout_uc_fault_response; /* R/W byte */
uint16_t ot_fault_limit; /* R/W word */
uint8_t ot_fault_response; /* R/W byte */
uint16_t ot_warn_limit; /* R/W word */
uint16_t ut_warn_limit; /* R/W word */
uint16_t ut_fault_limit; /* R/W word */
uint8_t ut_fault_response; /* R/W byte */
uint16_t vin_ov_fault_limit; /* R/W word */
uint8_t vin_ov_fault_response; /* R/W byte */
uint16_t vin_ov_warn_limit; /* R/W word */
uint16_t vin_uv_warn_limit; /* R/W word */
uint16_t vin_uv_fault_limit; /* R/W word */
uint8_t vin_uv_fault_response; /* R/W byte */
uint16_t iin_oc_fault_limit; /* R/W word */
uint8_t iin_oc_fault_response; /* R/W byte */
uint16_t iin_oc_warn_limit; /* R/W word */
uint16_t power_good_on; /* R/W word */
uint16_t power_good_off; /* R/W word */
uint16_t ton_delay; /* R/W word */
uint16_t ton_rise; /* R/W word */
uint16_t ton_max_fault_limit; /* R/W word */
uint8_t ton_max_fault_response; /* R/W byte */
uint16_t toff_delay; /* R/W word */
uint16_t toff_fall; /* R/W word */
uint16_t toff_max_warn_limit; /* R/W word */
uint16_t pout_op_fault_limit; /* R/W word */
uint8_t pout_op_fault_response; /* R/W byte */
uint16_t pout_op_warn_limit; /* R/W word */
uint16_t pin_op_warn_limit; /* R/W word */
uint16_t status_word; /* R/W word */
uint8_t status_vout; /* R/W byte */
uint8_t status_iout; /* R/W byte */
uint8_t status_input; /* R/W byte */
uint8_t status_temperature; /* R/W byte */
uint8_t status_cml; /* R/W byte */
uint8_t status_other; /* R/W byte */
uint8_t status_mfr_specific; /* R/W byte */
uint8_t status_fans_1_2; /* R/W byte */
uint8_t status_fans_3_4; /* R/W byte */
uint8_t read_ein[5]; /* Read-Only block 5 bytes */
uint8_t read_eout[5]; /* Read-Only block 5 bytes */
uint16_t read_vin; /* Read-Only word */
uint16_t read_iin; /* Read-Only word */
uint16_t read_vcap; /* Read-Only word */
uint16_t read_vout; /* Read-Only word */
uint16_t read_iout; /* Read-Only word */
uint16_t read_temperature_1; /* Read-Only word */
uint16_t read_temperature_2; /* Read-Only word */
uint16_t read_temperature_3; /* Read-Only word */
uint16_t read_fan_speed_1; /* Read-Only word */
uint16_t read_fan_speed_2; /* Read-Only word */
uint16_t read_fan_speed_3; /* Read-Only word */
uint16_t read_fan_speed_4; /* Read-Only word */
uint16_t read_duty_cycle; /* Read-Only word */
uint16_t read_frequency; /* Read-Only word */
uint16_t read_pout; /* Read-Only word */
uint16_t read_pin; /* Read-Only word */
uint8_t revision; /* Read-Only byte */
const char *mfr_id; /* R/W block */
const char *mfr_model; /* R/W block */
const char *mfr_revision; /* R/W block */
const char *mfr_location; /* R/W block */
const char *mfr_date; /* R/W block */
const char *mfr_serial; /* R/W block */
const char *app_profile_support; /* Read-Only block-read */
uint16_t mfr_vin_min; /* Read-Only word */
uint16_t mfr_vin_max; /* Read-Only word */
uint16_t mfr_iin_max; /* Read-Only word */
uint16_t mfr_pin_max; /* Read-Only word */
uint16_t mfr_vout_min; /* Read-Only word */
uint16_t mfr_vout_max; /* Read-Only word */
uint16_t mfr_iout_max; /* Read-Only word */
uint16_t mfr_pout_max; /* Read-Only word */
uint16_t mfr_tambient_max; /* Read-Only word */
uint16_t mfr_tambient_min; /* Read-Only word */
uint8_t mfr_efficiency_ll[14]; /* Read-Only block 14 bytes */
uint8_t mfr_efficiency_hl[14]; /* Read-Only block 14 bytes */
uint8_t mfr_pin_accuracy; /* Read-Only byte */
uint16_t mfr_max_temp_1; /* R/W word */
uint16_t mfr_max_temp_2; /* R/W word */
uint16_t mfr_max_temp_3; /* R/W word */
} PMBusPage;
/* State */
struct PMBusDevice {
SMBusDevice smb;
uint8_t num_pages;
uint8_t code;
uint8_t page;
/*
* PMBus registers are stored in a PMBusPage structure allocated by
* calling pmbus_pages_alloc()
*/
PMBusPage *pages;
uint8_t capability;
int32_t in_buf_len;
uint8_t *in_buf;
int32_t out_buf_len;
uint8_t out_buf[SMBUS_DATA_MAX_LEN];
};
/**
* Direct mode coefficients
* @var m - mantissa
* @var b - offset
* @var R - exponent
*/
typedef struct PMBusCoefficients {
int32_t m; /* mantissa */
int64_t b; /* offset */
int32_t R; /* exponent */
} PMBusCoefficients;
/**
* Convert sensor values to direct mode format
*
* Y = (m * x - b) * 10^R
*
* @return uint32_t
*/
uint16_t pmbus_data2direct_mode(PMBusCoefficients c, uint32_t value);
/**
* Convert direct mode formatted data into sensor reading
*
* X = (Y * 10^-R - b) / m
*
* @return uint32_t
*/
uint32_t pmbus_direct_mode2data(PMBusCoefficients c, uint16_t value);
/**
* @brief Send a block of data over PMBus
* Assumes that the bytes in the block are already ordered correctly,
* also assumes the length has been prepended to the block if necessary
* | low_byte | ... | high_byte |
* @param state - maintains state of the PMBus device
* @param data - byte array to be sent by device
* @param len - number
*/
void pmbus_send(PMBusDevice *state, const uint8_t *data, uint16_t len);
void pmbus_send8(PMBusDevice *state, uint8_t data);
void pmbus_send16(PMBusDevice *state, uint16_t data);
void pmbus_send32(PMBusDevice *state, uint32_t data);
void pmbus_send64(PMBusDevice *state, uint64_t data);
/**
* @brief Send a string over PMBus with length prepended.
* Length is calculated using str_len()
*/
void pmbus_send_string(PMBusDevice *state, const char *data);
/**
* @brief Receive data over PMBus
* These methods help track how much data is being received over PMBus
* Log to GUEST_ERROR if too much or too little is sent.
*/
uint8_t pmbus_receive8(PMBusDevice *pmdev);
uint16_t pmbus_receive16(PMBusDevice *pmdev);
uint32_t pmbus_receive32(PMBusDevice *pmdev);
uint64_t pmbus_receive64(PMBusDevice *pmdev);
/**
* PMBus page config must be called before any page is first used.
* It will allocate memory for all the pages if needed.
* Passed in flags overwrite existing flags if any.
* @param page_index the page to which the flags are applied, setting page_index
* to 0xFF applies the passed in flags to all pages.
* @param flags
*/
int pmbus_page_config(PMBusDevice *pmdev, uint8_t page_index, uint64_t flags);
/**
* Update the status registers when sensor values change.
* Useful if modifying sensors through qmp, this way status registers get
* updated
*/
void pmbus_check_limits(PMBusDevice *pmdev);
extern const VMStateDescription vmstate_pmbus_device;
#define VMSTATE_PMBUS_DEVICE(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PMBusDevice), \
.vmsd = &vmstate_pmbus_device, \
.flags = VMS_STRUCT, \
.offset = vmstate_offset_value(_state, _field, PMBusDevice), \
}
#endif

8
include/hw/i386/pc.h
View File

@ -19,7 +19,6 @@
* PCMachineState:
* @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
* @boot_cpus: number of present VCPUs
* @smp_dies: number of dies per one package
*/
typedef struct PCMachineState {
/*< private >*/
@ -45,6 +44,7 @@ typedef struct PCMachineState {
bool sata_enabled;
bool pit_enabled;
bool hpet_enabled;
bool default_bus_bypass_iommu;
uint64_t max_fw_size;
/* NUMA information: */
@ -139,8 +139,6 @@ extern int fd_bootchk;
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
void pc_smp_parse(MachineState *ms, QemuOpts *opts);
void pc_guest_info_init(PCMachineState *pcms);
#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
@ -191,12 +189,16 @@ void pc_system_flash_cleanup_unused(PCMachineState *pcms);
void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
bool pc_system_ovmf_table_find(const char *entry, uint8_t **data,
int *data_len);
void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size);
/* acpi-build.c */
void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
const CPUArchIdList *apic_ids, GArray *entry);
extern GlobalProperty pc_compat_6_0[];
extern const size_t pc_compat_6_0_len;
extern GlobalProperty pc_compat_5_2[];
extern const size_t pc_compat_5_2_len;

9
include/hw/i386/x86.h
View File

@ -62,7 +62,6 @@ struct X86MachineState {
unsigned pci_irq_mask;
unsigned apic_id_limit;
uint16_t boot_cpus;
unsigned smp_dies;
OnOffAuto smm;
OnOffAuto acpi;
@ -74,12 +73,20 @@ struct X86MachineState {
* will be translated to MSI messages in the address space.
*/
AddressSpace *ioapic_as;
/*
* Ratelimit enforced on detected bus locks in guest.
* The default value of the bus_lock_ratelimit is 0 per second,
* which means no limitation on the guest's bus locks.
*/
uint64_t bus_lock_ratelimit;
};
#define X86_MACHINE_SMM "smm"
#define X86_MACHINE_ACPI "acpi"
#define X86_MACHINE_OEM_ID "x-oem-id"
#define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id"
#define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit"
#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)

2
include/hw/ide/internal.h
View File

@ -625,7 +625,7 @@ int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
int chs_trans, Error **errp);
void ide_init2(IDEBus *bus, qemu_irq irq);
void ide_exit(IDEState *s);
void ide_init_ioport(IDEBus *bus, ISADevice *isa, int iobase, int iobase2);
int ide_init_ioport(IDEBus *bus, ISADevice *isa, int iobase, int iobase2);
void ide_register_restart_cb(IDEBus *bus);
void ide_exec_cmd(IDEBus *bus, uint32_t val);

28
include/hw/input/lm832x.h Normal file
View File

@ -0,0 +1,28 @@
/*
* National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
*
* Copyright (C) 2008 Nokia Corporation
* Written by Andrzej Zaborowski <andrew@openedhand.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_INPUT_LM832X
#define HW_INPUT_LM832X
#define TYPE_LM8323 "lm8323"
void lm832x_key_event(DeviceState *dev, int key, int state);
#endif

13
include/hw/isa/isa.h
View File

@ -138,12 +138,15 @@ void isa_unregister_ioport(ISADevice *dev, MemoryRegion *io);
* @portio: the ports, sorted by offset.
* @opaque: passed into the portio callbacks.
* @name: passed into memory_region_init_io.
*
* Returns: 0 on success, negative error code otherwise (e.g. if the
* ISA bus is not available)
*/
void isa_register_portio_list(ISADevice *dev,
PortioList *piolist,
uint16_t start,
const MemoryRegionPortio *portio,
void *opaque, const char *name);
int isa_register_portio_list(ISADevice *dev,
PortioList *piolist,
uint16_t start,
const MemoryRegionPortio *portio,
void *opaque, const char *name);
static inline ISABus *isa_bus_from_device(ISADevice *d)
{

2
include/hw/isa/vt82c686.h
View File

@ -2,8 +2,8 @@
#define HW_VT82C686_H
#define TYPE_VT82C686B_ISA "vt82c686b-isa"
#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
#define TYPE_VT82C686B_PM "vt82c686b-pm"
#define TYPE_VT8231_ISA "vt8231-isa"
#define TYPE_VT8231_PM "vt8231-pm"
#define TYPE_VIA_AC97 "via-ac97"
#define TYPE_VIA_MC97 "via-mc97"

10
include/hw/lm32/lm32_pic.h
View File

@ -1,10 +0,0 @@
#ifndef QEMU_HW_LM32_PIC_H
#define QEMU_HW_LM32_PIC_H
uint32_t lm32_pic_get_ip(DeviceState *d);
uint32_t lm32_pic_get_im(DeviceState *d);
void lm32_pic_set_ip(DeviceState *d, uint32_t ip);
void lm32_pic_set_im(DeviceState *d, uint32_t im);
#endif /* QEMU_HW_LM32_PIC_H */

5
include/hw/mem/pc-dimm.h
View File

@ -56,9 +56,6 @@ struct PCDIMMDevice {
* PCDIMMDeviceClass:
* @realize: called after common dimm is realized so that the dimm based
* devices get the chance to do specified operations.
* @get_vmstate_memory_region: returns #MemoryRegion which indicates the
* memory of @dimm should be kept during live migration. Will not fail
* after the device was realized.
*/
struct PCDIMMDeviceClass {
/* private */
@ -66,8 +63,6 @@ struct PCDIMMDeviceClass {
/* public */
void (*realize)(PCDIMMDevice *dimm, Error **errp);
MemoryRegion *(*get_vmstate_memory_region)(PCDIMMDevice *dimm,
Error **errp);
};
void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine,

43
include/hw/misc/aspeed_hace.h Normal file
View File

@ -0,0 +1,43 @@
/*
* ASPEED Hash and Crypto Engine
*
* Copyright (C) 2021 IBM Corp.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ASPEED_HACE_H
#define ASPEED_HACE_H
#include "hw/sysbus.h"
#define TYPE_ASPEED_HACE "aspeed.hace"
#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"
#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
#define ASPEED_HACE_NR_REGS (0x64 >> 2)
struct AspeedHACEState {
SysBusDevice parent;
MemoryRegion iomem;
qemu_irq irq;
uint32_t regs[ASPEED_HACE_NR_REGS];
MemoryRegion *dram_mr;
AddressSpace dram_as;
};
struct AspeedHACEClass {
SysBusDeviceClass parent_class;
uint32_t src_mask;
uint32_t dest_mask;
uint32_t hash_mask;
};
#endif /* _ASPEED_HACE_H_ */

17
include/hw/misc/aspeed_xdma.h
View File

@ -13,7 +13,10 @@
#include "qom/object.h"
#define TYPE_ASPEED_XDMA "aspeed.xdma"
OBJECT_DECLARE_SIMPLE_TYPE(AspeedXDMAState, ASPEED_XDMA)
#define TYPE_ASPEED_2400_XDMA TYPE_ASPEED_XDMA "-ast2400"
#define TYPE_ASPEED_2500_XDMA TYPE_ASPEED_XDMA "-ast2500"
#define TYPE_ASPEED_2600_XDMA TYPE_ASPEED_XDMA "-ast2600"
OBJECT_DECLARE_TYPE(AspeedXDMAState, AspeedXDMAClass, ASPEED_XDMA)
#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t))
#define ASPEED_XDMA_REG_SIZE 0x7C
@ -28,4 +31,16 @@ struct AspeedXDMAState {
uint32_t regs[ASPEED_XDMA_NUM_REGS];
};
struct AspeedXDMAClass {
SysBusDeviceClass parent_class;
uint8_t cmdq_endp;
uint8_t cmdq_wrp;
uint8_t cmdq_rdp;
uint8_t intr_ctrl;
uint32_t intr_ctrl_mask;
uint8_t intr_status;
uint32_t intr_complete;
};
#endif /* ASPEED_XDMA_H */

1
include/hw/misc/avr_power.h
View File

@ -26,7 +26,6 @@
#define HW_MISC_AVR_POWER_H
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "qom/object.h"

29
include/hw/misc/bcm2835_powermgt.h Normal file
View File

@ -0,0 +1,29 @@
/*
* BCM2835 Power Management emulation
*
* Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
* Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef BCM2835_POWERMGT_H
#define BCM2835_POWERMGT_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
struct BCM2835PowerMgtState {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t rstc;
uint32_t rsts;
uint32_t wdog;
};
#endif

21
include/hw/misc/mps2-scc.h
View File

@ -9,6 +9,24 @@
* (at your option) any later version.
*/
/*
* This is a model of the Serial Communication Controller (SCC)
* block found in most MPS FPGA images.
*
* QEMU interface:
* + sysbus MMIO region 0: the register bank
* + QOM property "scc-cfg4": value of the read-only CFG4 register
* + QOM property "scc-aid": value of the read-only SCC_AID register
* + QOM property "scc-id": value of the read-only SCC_ID register
* + QOM property "scc-cfg0": reset value of the CFG0 register
* + QOM property array "oscclk": reset values of the OSCCLK registers
* (which are accessed via the SYS_CFG channel provided by this device)
* + named GPIO output "remap": this tracks the value of CFG0 register
* bit 0. Boards where this bit controls memory remapping should
* connect this GPIO line to a function performing that mapping.
* Boards where bit 0 has no special function should leave the GPIO
* output disconnected.
*/
#ifndef MPS2_SCC_H
#define MPS2_SCC_H
@ -43,6 +61,9 @@ struct MPS2SCC {
uint32_t num_oscclk;
uint32_t *oscclk;
uint32_t *oscclk_reset;
uint32_t cfg0_reset;
qemu_irq remap;
};
#endif

1
include/hw/misc/stm32f4xx_exti.h
View File

@ -26,7 +26,6 @@
#define HW_STM_EXTI_H
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "qom/object.h"
#define EXTI_IMR 0x00

1
include/hw/misc/stm32f4xx_syscfg.h
View File

@ -26,7 +26,6 @@
#define HW_STM_SYSCFG_H
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "qom/object.h"
#define SYSCFG_MEMRMP 0x00

4
include/hw/pci-host/gpex.h
View File

@ -49,8 +49,12 @@ struct GPEXHost {
MemoryRegion io_ioport;
MemoryRegion io_mmio;
MemoryRegion io_ioport_window;
MemoryRegion io_mmio_window;
qemu_irq irq[GPEX_NUM_IRQS];
int irq_num[GPEX_NUM_IRQS];
bool allow_unmapped_accesses;
};
struct GPEXConfig {

1
include/hw/pci-host/i440fx.h
View File

@ -11,7 +11,6 @@
#ifndef HW_PCI_I440FX_H
#define HW_PCI_I440FX_H
#include "hw/hw.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/pam.h"
#include "qom/object.h"

8
include/hw/pci-host/mv64361.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef MV64361_H
#define MV64361_H
#define TYPE_MV64361 "mv64361"
PCIBus *mv64361_get_pci_bus(DeviceState *dev, int n);
#endif

2
include/hw/pci/pci.h
View File

@ -450,6 +450,7 @@ static inline PCIBus *pci_get_bus(const PCIDevice *dev)
return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
}
int pci_bus_num(PCIBus *s);
void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
static inline int pci_dev_bus_num(const PCIDevice *dev)
{
return pci_bus_num(pci_get_bus(dev));
@ -480,6 +481,7 @@ void pci_for_each_bus(PCIBus *bus,
PCIBus *pci_device_root_bus(const PCIDevice *d);
const char *pci_root_bus_path(PCIDevice *dev);
bool pci_bus_bypass_iommu(PCIBus *bus);
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
int pci_qdev_find_device(const char *id, PCIDevice **pdev);
void pci_bus_get_w64_range(PCIBus *bus, Range *range);

1
include/hw/pci/pci_host.h
View File

@ -43,6 +43,7 @@ struct PCIHostState {
uint32_t config_reg;
bool mig_enabled;
PCIBus *bus;
bool bypass_iommu;
QLIST_ENTRY(PCIHostState) next;
};

7
include/hw/pci/pci_ids.h
View File

@ -204,15 +204,17 @@
#define PCI_VENDOR_ID_XILINX 0x10ee
#define PCI_VENDOR_ID_VIA 0x1106
#define PCI_DEVICE_ID_VIA_ISA_BRIDGE 0x0686
#define PCI_DEVICE_ID_VIA_82C686B_ISA 0x0686
#define PCI_DEVICE_ID_VIA_IDE 0x0571
#define PCI_DEVICE_ID_VIA_UHCI 0x3038
#define PCI_DEVICE_ID_VIA_82C686B_PM 0x3057
#define PCI_DEVICE_ID_VIA_AC97 0x3058
#define PCI_DEVICE_ID_VIA_MC97 0x3068
#define PCI_DEVICE_ID_VIA_8231_ISA 0x8231
#define PCI_DEVICE_ID_VIA_8231_PM 0x8235
#define PCI_VENDOR_ID_MARVELL 0x11ab
#define PCI_DEVICE_ID_MARVELL_MV6436X 0x6460
#define PCI_VENDOR_ID_SILICON_MOTION 0x126f
#define PCI_DEVICE_ID_SM501 0x0501
@ -225,6 +227,9 @@
#define PCI_VENDOR_ID_FREESCALE 0x1957
#define PCI_DEVICE_ID_MPC8533E 0x0030
#define PCI_VENDOR_ID_BAIDU 0x1d22
#define PCI_DEVICE_ID_KUNLUN_VF 0x3685
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_82378 0x0484
#define PCI_DEVICE_ID_INTEL_82441 0x1237

5
include/hw/pci/pcie_port.h
View File

@ -57,8 +57,11 @@ struct PCIESlot {
/* Disable ACS (really for a pcie_root_port) */
bool disable_acs;
/* Indicates whether hot-plug is enabled on the slot */
/* Indicates whether any type of hot-plug is allowed on the slot */
bool hotplug;
bool native_hotplug;
QLIST_ENTRY(PCIESlot) next;
};

46
include/hw/ppc/spapr.h
View File

@ -12,6 +12,7 @@
#include "hw/ppc/spapr_xive.h" /* For SpaprXive */
#include "hw/ppc/xics.h" /* For ICSState */
#include "hw/ppc/spapr_tpm_proxy.h"
#include "hw/ppc/vof.h"
struct SpaprVioBus;
struct SpaprPhbState;
@ -74,8 +75,10 @@ typedef enum {
#define SPAPR_CAP_CCF_ASSIST 0x09
/* Implements PAPR FWNMI option */
#define SPAPR_CAP_FWNMI 0x0A
/* Support H_RPT_INVALIDATE */
#define SPAPR_CAP_RPT_INVALIDATE 0x0B
/* Num Caps */
#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1)
#define SPAPR_CAP_NUM (SPAPR_CAP_RPT_INVALIDATE + 1)
/*
* Capability Values
@ -95,7 +98,7 @@ typedef enum {
#define SPAPR_CAP_FIXED_CCD 0x03
#define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
#define FDT_MAX_SIZE 0x100000
#define FDT_MAX_SIZE 0x200000
/*
* NUMA related macros. MAX_DISTANCE_REF_POINTS was taken
@ -180,6 +183,7 @@ struct SpaprMachineState {
uint64_t kernel_addr;
uint32_t initrd_base;
long initrd_size;
Vof *vof;
uint64_t rtc_offset; /* Now used only during incoming migration */
struct PPCTimebase tb;
bool has_graphics;
@ -223,6 +227,9 @@ struct SpaprMachineState {
int fwnmi_machine_check_interlock;
QemuCond fwnmi_machine_check_interlock_cond;
/* Set by -boot */
char *boot_device;
/*< public >*/
char *kvm_type;
char *host_model;
@ -363,7 +370,7 @@ struct SpaprMachineState {
/* Values for 2nd argument to H_SET_MODE */
#define H_SET_MODE_RESOURCE_SET_CIABR 1
#define H_SET_MODE_RESOURCE_SET_DAWR 2
#define H_SET_MODE_RESOURCE_SET_DAWR0 2
#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
#define H_SET_MODE_RESOURCE_LE 4
@ -395,10 +402,13 @@ struct SpaprMachineState {
#define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
#define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
#define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
#define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
#define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
#define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7)
#define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8)
/* Each control block has to be on a 4K boundary */
#define H_CB_ALIGNMENT 4096
@ -538,8 +548,10 @@ struct SpaprMachineState {
#define H_SCM_BIND_MEM 0x3EC
#define H_SCM_UNBIND_MEM 0x3F0
#define H_SCM_UNBIND_ALL 0x3FC
#define H_SCM_HEALTH 0x400
#define H_RPT_INVALIDATE 0x448
#define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL
#define MAX_HCALL_OPCODE H_RPT_INVALIDATE
/* The hcalls above are standardized in PAPR and implemented by pHyp
* as well.
@ -554,7 +566,9 @@ struct SpaprMachineState {
/* Client Architecture support */
#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
#define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
#define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT
/* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */
#define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
#define KVMPPC_HCALL_MAX KVMPPC_H_VOF_CLIENT
/*
* The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
@ -581,6 +595,12 @@ typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args);
target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong shift);
target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong flags, target_ulong shift);
bool is_ram_address(SpaprMachineState *spapr, hwaddr addr);
void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
/* Virtual Processor Area structure constants */
#define VPA_MIN_SIZE 640
@ -760,7 +780,7 @@ void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
#define RTAS_SIZE 2048
#define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */
#define RTAS_ERROR_LOG_MAX 2048
/* Offset from rtas-base where error log is placed */
@ -820,6 +840,7 @@ void spapr_dt_events(SpaprMachineState *sm, void *fdt);
void close_htab_fd(SpaprMachineState *spapr);
void spapr_setup_hpt(SpaprMachineState *spapr);
void spapr_free_hpt(SpaprMachineState *spapr);
void spapr_check_mmu_mode(bool guest_radix);
SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
void spapr_tce_table_enable(SpaprTceTable *tcet,
uint32_t page_shift, uint64_t bus_offset,
@ -921,6 +942,7 @@ extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
extern const VMStateDescription vmstate_spapr_cap_large_decr;
extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
extern const VMStateDescription vmstate_spapr_cap_fwnmi;
extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate;
static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
{
@ -945,4 +967,16 @@ bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
hwaddr spapr_get_rtas_addr(void);
bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr);
void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp);
void spapr_vof_quiesce(MachineState *ms);
bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname,
void *val, int vallen);
target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong opcode, target_ulong *args);
target_ulong spapr_vof_client_architecture_support(MachineState *ms,
CPUState *cs,
target_ulong ovec_addr);
void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt);
#endif /* HW_SPAPR_H */

14
include/hw/ppc/spapr_nvdimm.h
View File

@ -11,19 +11,9 @@
#define HW_SPAPR_NVDIMM_H
#include "hw/mem/nvdimm.h"
#include "hw/ppc/spapr.h"
/*
* The nvdimm size should be aligned to SCM block size.
* The SCM block size should be aligned to SPAPR_MEMORY_BLOCK_SIZE
* inorder to have SCM regions not to overlap with dimm memory regions.
* The SCM devices can have variable block sizes. For now, fixing the
* block size to the minimum value.
*/
#define SPAPR_MINIMUM_SCM_BLOCK_SIZE SPAPR_MEMORY_BLOCK_SIZE
/* Have an explicit check for alignment */
QEMU_BUILD_BUG_ON(SPAPR_MINIMUM_SCM_BLOCK_SIZE % SPAPR_MEMORY_BLOCK_SIZE);
typedef struct SpaprDrc SpaprDrc;
typedef struct SpaprMachineState SpaprMachineState;
int spapr_pmem_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
void *fdt, int *fdt_start_offset, Error **errp);

60
include/hw/ppc/vof.h Normal file
View File

@ -0,0 +1,60 @@
/*
* Virtual Open Firmware
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_VOF_H
#define HW_VOF_H
typedef struct Vof {
uint64_t top_addr; /* copied from rma_size */
GArray *claimed; /* array of SpaprOfClaimed */
uint64_t claimed_base;
GHashTable *of_instances; /* ihandle -> SpaprOfInstance */
uint32_t of_instance_last;
char *bootargs;
long fw_size;
} Vof;
int vof_client_call(MachineState *ms, Vof *vof, void *fdt,
target_ulong args_real);
uint64_t vof_claim(Vof *vof, uint64_t virt, uint64_t size, uint64_t align);
void vof_init(Vof *vof, uint64_t top_addr, Error **errp);
void vof_cleanup(Vof *vof);
void vof_build_dt(void *fdt, Vof *vof);
uint32_t vof_client_open_store(void *fdt, Vof *vof, const char *nodename,
const char *prop, const char *path);
#define TYPE_VOF_MACHINE_IF "vof-machine-if"
typedef struct VofMachineIfClass VofMachineIfClass;
DECLARE_CLASS_CHECKERS(VofMachineIfClass, VOF_MACHINE, TYPE_VOF_MACHINE_IF)
struct VofMachineIfClass {
InterfaceClass parent;
target_ulong (*client_architecture_support)(MachineState *ms, CPUState *cs,
target_ulong vec);
void (*quiesce)(MachineState *ms);
bool (*setprop)(MachineState *ms, const char *path, const char *propname,
void *val, int vallen);
};
/*
* Initial stack size is from
* https://www.devicetree.org/open-firmware/bindings/ppc/release/ppc-2_1.html#REF27292
*
* "Client programs shall be invoked with a valid stack pointer (r1) with
* at least 32K bytes of memory available for stack growth".
*/
#define VOF_STACK_SIZE 0x8000
#define VOF_MEM_READ(pa, buf, size) \
address_space_read(&address_space_memory, \
(pa), MEMTXATTRS_UNSPECIFIED, (buf), (size))
#define VOF_MEM_WRITE(pa, buf, size) \
address_space_write(&address_space_memory, \
(pa), MEMTXATTRS_UNSPECIFIED, (buf), (size))
#define PROM_ERROR (~0U)
#endif /* HW_VOF_H */

5
include/hw/riscv/boot.h
View File

@ -24,6 +24,11 @@
#include "hw/loader.h"
#include "hw/riscv/riscv_hart.h"
#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf"
#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf"
bool riscv_is_32bit(RISCVHartArrayState *harts);
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,

24
include/hw/riscv/opentitan.h
View File

@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@ -35,9 +36,11 @@ struct LowRISCIbexSoCState {
RISCVHartArrayState cpus;
IbexPlicState plic;
IbexUartState uart;
IbexTimerState timer;
MemoryRegion flash_mem;
MemoryRegion rom;
MemoryRegion flash_alias;
};
typedef struct OpenTitanState {
@ -52,12 +55,13 @@ enum {
IBEX_DEV_ROM,
IBEX_DEV_RAM,
IBEX_DEV_FLASH,
IBEX_DEV_FLASH_VIRTUAL,
IBEX_DEV_UART,
IBEX_DEV_GPIO,
IBEX_DEV_SPI,
IBEX_DEV_I2C,
IBEX_DEV_PATTGEN,
IBEX_DEV_RV_TIMER,
IBEX_DEV_TIMER,
IBEX_DEV_SENSOR_CTRL,
IBEX_DEV_OTP_CTRL,
IBEX_DEV_PWRMGR,
@ -79,17 +83,19 @@ enum {
IBEX_DEV_ALERT_HANDLER,
IBEX_DEV_NMI_GEN,
IBEX_DEV_OTBN,
IBEX_DEV_PERI,
};
enum {
IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
IBEX_UART_TX_EMPTY_IRQ = 0x23,
IBEX_UART_RX_WATERMARK_IRQ = 0x22,
IBEX_UART_TX_WATERMARK_IRQ = 0x21,
IBEX_TIMER_TIMEREXPIRED0_0 = 125,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
IBEX_UART0_RX_OVERFLOW_IRQ = 4,
IBEX_UART0_TX_EMPTY_IRQ = 3,
IBEX_UART0_RX_WATERMARK_IRQ = 2,
IBEX_UART0_TX_WATERMARK_IRQ = 1,
};
#endif

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