491a25535c
target/ppc: Implement slbiag
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-12-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
acc130cf1d
target/ppc: Move slbsync to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-11-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
26d02c9d42
target/ppc: Move slbfee to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-10-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
41b60e46b8
target/ppc: Move slbmfee to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-9-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
74a153844e
target/ppc: Move slbmfev to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-8-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
0b0ba40fd2
target/ppc: Move slbmte to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-7-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
2bfcb7a316
target/ppc: Move slbia to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-6-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
a1b05c0625
target/ppc: Move slbieg to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-5-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
43507e47e1
target/ppc: Move slbie to decodetree
...
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Message-Id: <20220701133507.740619-4-lucas.coutinho@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
016b6e1d9c
target/ppc: Move tlbie[l] to decode tree
...
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com >
Message-Id: <20220712193741.59134-2-leandro.lupori@eldorado.org.br >
[danielhb: mark bit 31 in @X_tlbie pattern as ignored]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-18 13:59:43 -03:00
6b924d4afc
target/ppc: implement cdtbcd
...
Implements the Convert Declets To Binary Coded Decimal instruction.
Since libdecnumber doesn't expose the methods for direct conversion
(decDigitsFromDPD, DPD2BCD, etc), a positive decimal32 with zero
exponent is used as an intermediate value to convert the declets.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220629162904.105060-12-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
38d3690bda
target/ppc: implement cbcdtd
...
Implements the Convert Binary Coded Decimal To Declets instruction.
Since libdecnumber doesn't expose the methods for direct conversion
(decDigitsToDPD, BCD2DPD, etc.), the BCD values are converted to
decimal32 format, from which the declets are extracted.
Where the behavior is undefined, we try to match the result observed in
a POWER9 DD2.3.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220629162904.105060-11-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
6addef4d27
target/ppc: implement addg6s
...
Implements the following Power ISA v2.06 instruction:
addg6s: Add and Generate Sixes
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220629162904.105060-10-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
6cef305fe7
target/ppc: Implement mffscdrn[i] instructions
...
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220629162904.105060-7-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
f80d04d548
target/ppc: Move mffs[.] to decodetree
...
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220629162904.105060-6-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
3e5bce70ef
target/ppc: Move mffsl to decodetree
...
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220629162904.105060-5-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
394c2e2fda
target/ppc: Move mffsce to decodetree
...
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220629162904.105060-4-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
bf8adfd88b
target/ppc: Move mffscrn[i] to decodetree
...
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220629162904.105060-3-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
bbecdb22ae
target/ppc: Fix insn32.decode style issues
...
Some lines in insn32.decode have inconsistent alignment when compared
to others.
Fix this by changing the alignment of some lines, making it more
consistent throughout the file.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220629162904.105060-2-victor.colombo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
b7d30fae5b
target/ppc: use int128.h methods in vsubcuq
...
And also move the insn to decodetree and remove the now unused
avr_qw_not, avr_qw_cmpu, and avr_qw_add methods.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220606150037.338931-8-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
e6a5ad43de
target/ppc: use int128.h methods in vsubecuq and vsubeuqm
...
And also move the insns to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220606150037.338931-7-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
b132be53a4
target/ppc: use int128.h methods in vsubuqm
...
And also move the insn to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220606150037.338931-6-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
8290ea509f
target/ppc: use int128.h methods in vaddcuq
...
And also move the insn to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220606150037.338931-5-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
896d92c81d
target/ppc: use int128.h methods in vaddecuq and vaddeuqm
...
And also move the insns to decodetree and remove the now unused
avr_qw_addc method.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220606150037.338931-4-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:38 -03:00
7ca0428687
target/ppc: use int128.h methods in vadduqm
...
And also move the insn to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220606150037.338931-3-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:37 -03:00
e82ca8acdd
target/ppc: use int128.h methods in vpmsumd
...
Also drop VECTOR_FOR_INORDER_I usage since there is no need to access
the elements in any particular order, and move the instruction to
decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Message-Id: <20220606150037.338931-2-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-07-06 10:22:37 -03:00
b80bec3a07
target/ppc: Implemented vector module quadword
...
Implement the following PowerISA v3.1 instructions:
vmodsq: Vector Modulo Signed Quadword
vmoduq: Vector Modulo Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/744
Message-Id: <20220525134954.85056-9-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-06-20 08:38:58 -03:00
5adb27cd8f
target/ppc: Implemented vector module word/doubleword
...
Implement the following PowerISA v3.1 instructions:
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Doubleword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220525134954.85056-8-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-06-20 08:38:58 -03:00
a173ba88be
target/ppc: Implemented remaining vector divide extended
...
Implement the following PowerISA v3.1 instructions:
vdivesd: Vector Divide Extended Signed Doubleword
vdiveud: Vector Divide Extended Unsigned Doubleword
vdivesq: Vector Divide Extended Signed Quadword
vdiveuq: Vector Divide Extended Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220525134954.85056-7-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-06-20 08:38:58 -03:00
9a1f0866a3
target/ppc: Implemented vector divide extended word
...
Implement the following PowerISA v3.1 instructions:
vdivesw: Vector Divide Extended Signed Word
vdiveuw: Vector Divide Extended Unsigned Word
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220525134954.85056-4-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-06-20 08:38:58 -03:00
1700f2bf97
target/ppc: Implemented vector divide quadword
...
Implement the following PowerISA v3.1 instructions:
vdivsq: Vector Divide Signed Quadword
vdivuq: Vector Divide Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220525134954.85056-3-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-06-20 08:38:58 -03:00
61f302615a
target/ppc: Implemented vector divide instructions
...
Implement the following PowerISA v3.1 instructions:
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220525134954.85056-2-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-06-20 08:38:58 -03:00
5724e131ca
target/ppc: Implemented [pm]xvbf16ger2*
...
Implement the following PowerISA v3.1 instructions:
xvbf16ger2: VSX Vector bfloat16 GER (rank-2 update)
xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Negative accumulate
xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Positive accumulate
xvbf16ger2pn: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
Negative accumulate
xvbf16ger2pp: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
Positive accumulate
pmxvbf16ger2: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
pmxvbf16ger2nn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Negative multiply, Negative accumulate
pmxvbf16ger2np: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Negative multiply, Positive accumulate
pmxvbf16ger2pn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Positive multiply, Negative accumulate
pmxvbf16ger2pp: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220524140537.27451-8-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
2d9cba74ef
target/ppc: Implemented xvf16ger*
...
Implement the following PowerISA v3.1 instructions:
xvf16ger2: VSX Vector 16-bit Floating-Point GER (rank-2 update)
xvf16ger2nn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Negative accumulate
xvf16ger2np: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Positive accumulate
xvf16ger2pn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive
multiply, Negative accumulate
xvf16ger2pp: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive
multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220524140537.27451-6-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
c29018cc73
target/ppc: Implemented xvf*ger*
...
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
xvf64ger: VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220524140537.27451-5-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
345531533f
target/ppc: Implemented xvi*ger* instructions
...
Implement the following PowerISA v3.1 instructions:
xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
Positive multiply, Positive accumulate
xvi8ger4: VSX Vector 4-bit Signed Integer GER (rank-8 update)
xvi8ger4pp: VSX Vector 4-bit Signed Integer GER (rank-8 update)
Positive multiply, Positive accumulate
xvi8ger4spp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
with Saturate Positive multiply, Positive accumulate
xvi16ger2: VSX Vector 16-bit Signed Integer GER (rank-2 update)
xvi16ger2pp: VSX Vector 16-bit Signed Integer GER (rank-2 update)
Positive multiply, Positive accumulate
xvi16ger2s: VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation
xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220524140537.27451-3-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
a702c5339e
target/ppc: Implement xxm[tf]acc and xxsetaccz
...
Implement the following PowerISA v3.1 instructions:
xxmfacc: VSX Move From Accumulator
xxmtacc: VSX Move To Accumulator
xxsetaccz: VSX Set Accumulator to Zero
The PowerISA 3.1 mentions that for the current version of the
architecture, "the hardware implementation provides the effect of ACC[i]
and VSRs 4*i to 4*i + 3 logically containing the same data" and "The
Accumulators introduce no new logical state at this time" (page 501).
For now it seems unnecessary to create new structures, so this patch
just uses ACC[i] as VSRs 4*i to 4*i+3 and therefore move to and from
accumulators are no-ops.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220524140537.27451-2-lucas.araujo@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
6f52f731a6
target/ppc: declare vmsumsh[ms] helper with call flags
...
Move vmsumshm and vmsumshs to decodetree, declare vmsumshm helper with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220517123929.284511-13-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
89a5a1aee2
target/ppc: declare vmsumuh[ms] helper with call flags
...
Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220517123929.284511-12-matheus.ferst@eldorado.org.br >
[danielhb: added #undef VMSUMUHM to fix ppc64 build]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
b2dc03a5c3
target/ppc: declare vmsum[um]bm helpers with call flags
...
Move vmsumubm and vmsummbm to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220517123929.284511-11-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:33 -03:00
8f5eeee3f1
target/ppc: declare xxextractuw and xxinsertw helpers with call flags
...
Move xxextractuw and xxinsertw to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220517123929.284511-9-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:32 -03:00
c36ab970ac
target/ppc: declare xvxsigsp helper with call flags
...
Move xvxsigsp to decodetree, declare helper_xvxsigsp with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220517123929.284511-8-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:32 -03:00
cf862bee0e
target/ppc: declare xscvspdpn helper with call flags
...
Move xscvspdpn to decodetree, declare helper_xscvspdpn with
TCG_CALL_NO_RWG_SE and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220517123929.284511-7-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:32 -03:00
eb69a84bb0
target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper
...
fsel doesn't change FPSCR and CR1 is handled by gen_set_cr1_from_fpscr,
so helper_fsel doesn't need the env argument and can be declared with
TCG_CALL_NO_RWG_SE. We also take this opportunity to move the insn to
decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220517123929.284511-6-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-05-26 17:11:32 -03:00
b3d4520585
target/ppc: implement xscvqp[su]qz
...
Implement the following PowerISA v3.1 instructions:
xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to
Signed Quadword
xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to
Unsigned Quadword
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220330175932.6995-9-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-04-20 18:00:30 -03:00
67332e0718
target/ppc: implement xscv[su]qqp
...
Implement the following PowerISA v3.1 instructions:
xscvsqqp: VSX Scalar Convert with round Signed Quadword to
Quad-Precision
xscvuqqp: VSX Scalar Convert with round Unsigned Quadword to
Quad-Precision format
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220330175932.6995-8-matheus.ferst@eldorado.org.br >
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com >
2022-04-20 18:00:30 -03:00
604d00c76f
target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x
...
Implement the following PowerISA v3.1 instuctions:
lxvrbx: Load VSX Vector Rightmost Byte Indexed X-form
lxvrhx: Load VSX Vector Rightmost Halfword Indexed X-form
lxvrwx: Load VSX Vector Rightmost Word Indexed X-form
lxvrdx: Load VSX Vector Rightmost Doubleword Indexed X-form
stxvrbx: Store VSX Vector Rightmost Byte Indexed X-form
stxvrhx: Store VSX Vector Rightmost Halfword Indexed X-form
stxvrwx: Store VSX Vector Rightmost Word Indexed X-form
stxvrdx: Store VSX Vector Rightmost Doubleword Indexed X-form
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br >
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220225210936.1749575-50-matheus.ferst@eldorado.org.br >
Signed-off-by: Cédric Le Goater <clg@kaod.org >
2022-03-02 06:51:38 +01:00
20e2d04e66
target/ppc: implement plxssp/pstxssp
...
Implement instructions plxssp/pstxssp and port lxssp/stxssp to
decode tree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220225210936.1749575-49-matheus.ferst@eldorado.org.br >
Signed-off-by: Cédric Le Goater <clg@kaod.org >
2022-03-02 06:51:38 +01:00
7eec8cbb1b
target/ppc: implement plxsd/pstxsd
...
Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode
tree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br >
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Message-Id: <20220225210936.1749575-48-matheus.ferst@eldorado.org.br >
Signed-off-by: Cédric Le Goater <clg@kaod.org >
2022-03-02 06:51:38 +01:00
3909ff1fac
target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions
...
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br >
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220225210936.1749575-47-matheus.ferst@eldorado.org.br >
Signed-off-by: Cédric Le Goater <clg@kaod.org >
2022-03-02 06:51:38 +01:00
