3a2752179a
target/loongarch: Implement xvsigncov
...
This patch includes:
- XVSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-32-gaosong@loongson.cn >
2023-09-20 11:43:14 +08:00
790acb2a43
target/loongarch: Implement vext2xv
...
This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-31-gaosong@loongson.cn >
2023-09-20 11:43:13 +08:00
f0db0beb80
target/loongarch: Implement xvexth
...
This patch includes:
- XVEXTH.{H.B/W.H/D.W/Q.D};
- XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-30-gaosong@loongson.cn >
2023-09-20 11:43:13 +08:00
e5c7f0315e
target/loongarch: Implement xvsat
...
This patch includes:
- XVSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-29-gaosong@loongson.cn >
2023-09-20 11:43:13 +08:00
abb693de0a
target/loongarch; Implement xvdiv/xvmod
...
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-28-gaosong@loongson.cn >
2023-09-20 11:43:13 +08:00
3f450c17d0
target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
...
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-27-gaosong@loongson.cn >
2023-09-20 11:43:13 +08:00
342dc1cfcb
target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
...
This patch includes:
- XVMUL.{B/H/W/D};
- XVMUH.{B/H/W/D}[U];
- XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-26-gaosong@loongson.cn >
2023-09-20 11:43:13 +08:00
c09360faad
target/loongarch: Implement xvmax/xvmin
...
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-25-gaosong@loongson.cn >
2023-09-20 11:43:13 +08:00
27f5485d95
target/loongarch: Implement xvadda
...
This patch includes:
- XVADDA.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-24-gaosong@loongson.cn >
2023-09-20 11:43:12 +08:00
ccc9fa2605
target/loongarch: Implement xvabsd
...
This patch includes:
- XVABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-23-gaosong@loongson.cn >
2023-09-20 11:43:12 +08:00
ee7250d091
target/loongarch: Implement xavg/xvagr
...
This patch includes:
- XVAVG.{B/H/W/D/}[U];
- XVAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-22-gaosong@loongson.cn >
2023-09-20 11:43:12 +08:00
85995f076a
target/loongarch: Implement xvaddw/xvsubw
...
This patch includes:
- XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-21-gaosong@loongson.cn >
2023-09-20 11:43:12 +08:00
64cf6b99d7
target/loongarch: Implement xvhaddw/xvhsubw
...
This patch includes:
- XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-20-gaosong@loongson.cn >
2023-09-20 11:43:12 +08:00
d2df46d9a4
target/loongarch: Implement xvsadd/xvssub
...
This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-19-gaosong@loongson.cn >
2023-09-20 11:43:12 +08:00
760f964717
target/loongarch: Implement xvneg
...
This patch includes:
- XVNEG.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-18-gaosong@loongson.cn >
2023-09-20 11:43:12 +08:00
342004214b
target/loongarch: Implement xvaddi/xvsubi
...
This patch includes:
- XVADDI.{B/H/W/D}U;
- XVSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-17-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
73123406f3
target/loongarch: Implement xvreplgr2vr
...
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-16-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
269ca39a7d
target/loongarch: Implement xvadd/xvsub
...
This patch includes:
- XVADD.{B/H/W/D/Q};
- XVSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-15-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
cf61aef308
target/loongarch: Add avail_LASX to check LASX instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-14-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
b8f1bdf3d1
target/loongarch: check_vec support check LASX instructions
...
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Song Gao <gaosong@loongson.cn >
Message-Id: <20230914022645.1151356-13-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
008a3b1662
target/loongarch: Add LASX data support
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-12-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
cd1006176b
target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)
...
Introduce a new function check_vec to replace CHECK_SXE
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-11-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
329517d518
target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-10-gaosong@loongson.cn >
2023-09-20 11:43:11 +08:00
ff27e335fc
target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-9-gaosong@loongson.cn >
2023-09-20 11:43:10 +08:00
226bf88174
target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-8-gaosong@loongson.cn >
2023-09-20 11:43:10 +08:00
04711da1a6
target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-7-gaosong@loongson.cn >
2023-09-20 11:43:10 +08:00
3b286753c9
target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-6-gaosong@loongson.cn >
2023-09-20 11:43:10 +08:00
eb48ab2256
target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-5-gaosong@loongson.cn >
2023-09-20 11:43:10 +08:00
e2600dad02
target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions
...
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-4-gaosong@loongson.cn >
2023-09-20 11:43:10 +08:00
b630aeaae7
target/loongarch: Implement gvec_*_vl functions
...
Create gvec_*_vl functions in order to hide oprsz.
This is used by gvec_v* functions for oprsz 16,
and will be used by gvec_x* functions for oprsz 32.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-3-gaosong@loongson.cn >
2023-09-20 11:43:10 +08:00
1dc33f2653
target/loongarch: Renamed lsx*.c to vec* .c
...
Renamed lsx_helper.c to vec_helper.c and trans_lsx.c.inc to trans_vec.c.inc
So LASX can used them.
Signed-off-by: Song Gao <gaosong@loongson.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230914022645.1151356-2-gaosong@loongson.cn >
2023-09-20 11:43:06 +08:00
cf6b28d41b
target/hppa: Wire up diag instruction to support BTLB
...
Wire up the hppa diag instruction to support Block-TLBs
when called with the 0x100 value.
The diag_btlb() helper function does all necessary steps
to emulate the PDC BTLB firmware function, which includes
providing BTLB info, adding a new BTLB, deleting a BTLB
and removing all BTLBs.
Signed-off-by: Helge Deller <deller@gmx.de >
2023-09-19 21:12:18 +02:00
d7754940d7
Merge tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu into staging
...
*: Delete checks for old host definitions
tcg/loongarch64: Generate LSX instructions
fpu: Add conversions between bfloat16 and [u]int8
fpu: Handle m68k extended precision denormals properly
accel/tcg: Improve cputlb i/o organization
accel/tcg: Simplify tlb_plugin_lookup
accel/tcg: Remove false-negative halted assertion
tcg: Add gvec compare with immediate and scalar operand
tcg/aarch64: Emit BTI insns at jump landing pads
[Resolved conflict between CPUINFO_PMULL and CPUINFO_BTI.
--Stefan]
* tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu : (39 commits)
tcg: Map code_gen_buffer with PROT_BTI
tcg/aarch64: Emit BTI insns at jump landing pads
util/cpuinfo-aarch64: Add CPUINFO_BTI
tcg: Add tcg_out_tb_start backend hook
fpu: Handle m68k extended precision denormals properly
fpu: Add conversions between bfloat16 and [u]int8
accel/tcg: Introduce do_st16_mmio_leN
accel/tcg: Introduce do_ld16_mmio_beN
accel/tcg: Merge io_writex into do_st_mmio_leN
accel/tcg: Merge io_readx into do_ld_mmio_beN
accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1
accel/tcg: Merge cpu_transaction_failed into io_failed
plugin: Simplify struct qemu_plugin_hwaddr
accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed
accel/tcg: Split out io_prepare and io_failed
accel/tcg: Simplify tlb_plugin_lookup
target/arm: Use tcg_gen_gvec_cmpi for compare vs 0
tcg: Add gvec compare with immediate and scalar operand
tcg/loongarch64: Implement 128-bit load & store
tcg/loongarch64: Lower rotli_vec to vrotri
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com >
2023-09-19 13:20:54 -04:00
e8967b6152
target/arm: Use tcg_gen_gvec_cmpi for compare vs 0
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Song Gao <gaosong@loongson.cn >
Message-Id: <20230831030904.1194667-3-richard.henderson@linaro.org >
2023-09-16 14:57:15 +00:00
a64b8842f1
target/hppa: Extract diagnose immediate value
...
Extract the immediate value given by the diagnose CPU instruction.
This is needed to distinguish the various diagnose calls.
Signed-off-by: Helge Deller <deller@gmx.de >
2023-09-15 17:34:38 +02:00
fa824d99f9
target/hppa: Add BTLB support to hppa TLB functions
...
Change the TLB code to store the Block-TLBs at the beginning
of the TLB table. New 4k TLB entries which are added later
shall not overwrite any of the BTLB entries.
Make sure that when the TLB is cleared by the OS via the ptlbe
instruction, the Block-TLBs will not be dropped.
Signed-off-by: Helge Deller <deller@gmx.de >
2023-09-15 17:34:38 +02:00
7bdbf233d9
target/ppc: Use clmul_64
...
Use generic routine for 64-bit carry-less multiply.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
ef73fe7cf1
target/s390x: Use clmul_64
...
Use the generic routine for 64-bit carry-less multiply.
Remove our local version of galois_multiply64.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
7fcb505455
target/i386: Use clmul_64
...
Use generic routine for 64-bit carry-less multiply.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
a50cfdf0be
target/arm: Use clmul_64
...
Use generic routine for 64-bit carry-less multiply.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
f56d3c1a14
target/ppc: Use clmul_32* routines
...
Use generic routines for 32-bit carry-less multiply.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
653aab27ba
target/s390x: Use clmul_32* routines
...
Use generic routines for 32-bit carry-less multiply.
Remove our local version of galois_multiply32.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
bae25f648e
target/arm: Use clmul_32* routines
...
Use generic routines for 32-bit carry-less multiply.
Remove our local version of pmull_d.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
a2c67342ee
target/ppc: Use clmul_16* routines
...
Use generic routines for 16-bit carry-less multiply.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
25c304e936
target/s390x: Use clmul_16* routines
...
Use generic routines for 16-bit carry-less multiply.
Remove our local version of galois_multiply16.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
c6f0dcb1fd
target/arm: Use clmul_16* routines
...
Use generic routines for 16-bit carry-less multiply.
Remove our local version of pmull_w.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
cec4090d94
target/ppc: Use clmul_8* routines
...
Use generic routines for 8-bit carry-less multiply.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
2d8bc6815e
target/s390x: Use clmul_8* routines
...
Use generic routines for 8-bit carry-less multiply.
Remove our local version of galois_multiply8.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:57:00 +00:00
8e3da4c716
target/arm: Use clmul_8* routines
...
Use generic routines for 8-bit carry-less multiply.
Remove our local version of pmull_h.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-09-15 13:56:59 +00:00
6a2557c238
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
...
* target/i386: fix non-optimized compilation on clang
* fix detection of Solaris/IllumOS
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 13 Sep 2023 06:32:39 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com "
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org >" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com >" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu :
target/i386: Call accel-agnostic x86_cpu_get_supported_cpuid()
target/i386: Drop accel_uses_host_cpuid before x86_cpu_get_supported_cpuid
target/i386: Check kvm_hyperv_expand_features() return value
meson: Fix targetos match for illumos and Solaris.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com >
2023-09-13 13:41:27 -04:00