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242376e872
On RISC-V to StoreStore barrier corresponds `fence w, w` not `fence r, r` Cc: qemu-stable@nongnu.org Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com> Signed-off-by: Roman Artemev <roman.artemev@syntacore.com> Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> (cherry picked from commit b438362a142527b97b638b7f0f35ebe11911a8d5) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>