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Fourth RISC-V PR for 6.1 release - Code cleanups - Documentation improvements - Hypervisor extension improvements with hideleg and hedeleg - sifive_u fixes - OpenTitan register layout updates - Fix coverity issue # gpg: Signature made Thu 15 Jul 2021 08:14:00 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210715: hw/riscv/boot: Check the error of fdt_pack() hw/riscv: opentitan: Add the flash alias hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri char: ibex_uart: Update the register layout hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned hw/riscv: sifive_u: Correct the CLINT timebase frequency docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot target/riscv: hardwire bits in hideleg and hedeleg docs/system: riscv: Add documentation for virt machine docs/system: riscv: Fix CLINT name in the sifive_u doc target/riscv: csr: Remove redundant check in fp csr read/write routines target/riscv: pmp: Fix some typos Signed-off-by: Peter Maydell <peter.maydell@linaro.org>