Emilio G. Cota 86e1eff8bc tcg: introduce dynamic TLB sizing ...

Disabled in all TCG backends for now.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <20190116170114.26802-3-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2019-01-28 07:03:34 -08:00

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user

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address-spaces.h

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cpu_ldst_template.h

cputlb: read CPUTLBEntry.addr_write atomically

2018-10-18 19:46:53 -07:00

cpu_ldst_useronly_template.h

linux-user: fix 32bit g2h()/h2g()

2018-08-17 13:56:33 +02:00

cpu_ldst.h

tcg: introduce dynamic TLB sizing

2019-01-28 07:03:34 -08:00

cpu-all.h

tcg: Define and use new tlb_hit() and tlb_hit_page() functions

2018-07-02 08:02:20 -07:00

cpu-common.h

Rename cpu_physical_memory_write_rom() to address_space_write_rom()

2018-12-14 13:30:48 +00:00

cpu-defs.h

tcg: introduce dynamic TLB sizing

2019-01-28 07:03:34 -08:00

cputlb.h

cputlb: Count "partial" and "elided" tlb flushes

2018-10-31 12:16:30 +00:00

exec-all.h

exec: introduce tlb_init

2018-10-18 18:58:10 -07:00

gdbstub.h

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gen-icount.h

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helper-gen.h

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helper-head.h

tcg: Add TCG_CALL_NO_RETURN

2018-12-26 06:40:24 +11:00

helper-proto.h

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helper-tcg.h

tcg: Add TCG_CALL_NO_RETURN

2018-12-26 06:40:24 +11:00

hwaddr.h

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ioport.h

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log.h

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memattrs.h

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memory_ldst_cached.inc.h

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memory_ldst_phys.inc.h

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memory_ldst.inc.h

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memory-internal.h

tcg: remove tb_lock

2018-06-15 08:18:48 -10:00

memory.h

qemu/queue.h: simplify reverse access to QTAILQ

2019-01-11 15:46:55 +01:00

poison.h

exec: Add RISC-V GCC poison macro

2018-12-26 06:40:02 +11:00

ram_addr.h

COLO: Load dirty pages into SVM's RAM cache firstly

2018-10-19 11:15:03 +08:00

ramlist.h

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semihost.h

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softmmu-semi.h

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target_page.h

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tb-context.h

tcg: remove tb_lock

2018-06-15 08:18:48 -10:00

tb-hash.h

include: move exec/tb-hash-xx.h to qemu/xxhash.h

2018-12-17 06:04:44 +03:00

tb-lookup.h

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translator.h

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