Vijai Kumar K 6ddc7069f5 target/riscv: Add Shakti C class CPU ...

C-Class is a member of the SHAKTI family of processors from IIT-M.

It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-05-11 20:01:10 +10:00

..

alpha

target/alpha: fix icount handling for timer instructions

2021-04-05 07:32:56 -07:00

arm

target/arm: Make WFI a NOP for userspace emulators

2021-05-10 13:24:09 +01:00

avr

target/avr: Fix interrupt execution

2021-03-15 00:39:52 +01:00

cris

target/cris: Plug leakage of TCG temporaries

2021-02-22 09:04:58 +01:00

hexagon

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging

2021-05-05 13:52:00 +01:00

hppa

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i386

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

2021-05-06 18:56:17 +01:00

lm32

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

m68k

Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging

2021-03-12 18:56:56 +00:00

microblaze

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mips

target/mips: Move TCG source files under tcg/ sub directory

2021-05-02 16:49:35 +02:00

moxie

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nios2

semihosting: Move include/hw/semihosting/ -> include/semihosting/

2021-03-10 15:34:12 +00:00

openrisc

Do not include sysemu/sysemu.h if it's not really necessary

2021-05-02 17:24:50 +02:00

ppc

target/ppc: removed VSCR from SPR registration

2021-05-04 13:12:59 +10:00

riscv

target/riscv: Add Shakti C class CPU

2021-05-11 20:01:10 +10:00

rx

Do not include sysemu/sysemu.h if it's not really necessary

2021-05-02 17:24:50 +02:00

s390x

Do not include exec/address-spaces.h if it's not really necessary

2021-05-02 17:24:51 +02:00

sh4

target/sh4: Remove unused definitions

2021-03-06 16:18:42 +01:00

sparc

hw/sparc*: Move cpu_check_irqs() to target/sparc/

2021-05-04 22:45:53 +01:00

tricore

target/tricore: Fix OPC2_32_RRPW_EXTR for width=0

2021-03-14 14:49:01 +01:00

unicore32

semihosting: Move include/hw/semihosting/ -> include/semihosting/

2021-03-10 15:34:12 +00:00

xtensa

Do not include exec/address-spaces.h if it's not really necessary

2021-05-02 17:24:51 +02:00

meson.build

Remove deprecated target tilegx

2021-03-09 11:26:32 +01:00