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https://github.com/pj64team/Project64-Legacy.git
synced 2026-04-24 23:43:38 +00:00
Handle TLB miss on writes.
This commit is contained in:
@ -680,6 +680,18 @@ void CompileExit (DWORD TargetPC, REG_INFO ExitRegSet, int reason, int CompileNo
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if (CPU_Type == CPU_SyncCores) { Call_Direct(SyncToPC, "SyncToPC"); }
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Ret();
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break;
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case TLBWriteMiss:
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MoveVariableToX86reg(&TLBLoadAddress, "TLBLoadAddress", x86_EDX);
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MoveX86RegToX86Reg(x86_EDX, x86_ECX);
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ShiftRightSignImmed(x86_ECX, 31);
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Push(x86_ECX);
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Push(x86_EDX);
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MoveConstToX86reg(NextInstruction == JUMP || NextInstruction == DELAY_SLOT, x86_ECX);
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MoveConstToX86reg(0, x86_EDX);
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Call_Direct(DoTLBMiss, "DoTLBMiss");
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if (CPU_Type == CPU_SyncCores) { Call_Direct(SyncToPC, "SyncToPC"); }
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Ret();
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break;
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default:
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if (ShowDebugMessages)
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DisplayError("how did you want to exit on reason (%d) ???",reason);
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@ -46,6 +46,7 @@
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#define DoBreak 7
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#define DoIlleaglOp 8
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#define DoTrap 9
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#define TLBWriteMiss 10
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#define STATE_KNOWN_VALUE 1
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//#define STATE_UNKNOW_VALUE
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@ -38,6 +38,12 @@ void CompileReadTLBMiss (BLOCK_SECTION * Section, int AddressReg, int LookUpReg
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CompileExit(Section->CompilePC,Section->RegWorking,TLBReadMiss,FALSE,JeLabel32);
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}
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void CompileWriteTLBMiss(BLOCK_SECTION* Section, int AddressReg, int LookUpReg) {
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MoveX86regToVariable(AddressReg, &TLBLoadAddress, "TLBLoadAddress");
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TestX86RegToX86Reg(LookUpReg, LookUpReg);
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CompileExit(Section->CompilePC, Section->RegWorking, TLBWriteMiss, FALSE, JeLabel32);
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}
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/************************** Branch functions ************************/
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void Compile_R4300i_Branch (BLOCK_SECTION * Section, void (*CompareFunc)(BLOCK_SECTION * Section), int BranchType, BOOL Link) {
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MIPS_DWORD CompilePC;
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@ -2142,6 +2148,7 @@ void Compile_R4300i_SB (BLOCK_SECTION * Section){
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MoveX86RegToX86Reg(TempReg1, TempReg2);
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ShiftRightUnsignImmed(TempReg2,12);
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MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
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CompileWriteTLBMiss(Section, TempReg1, TempReg2);
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//For tlb miss
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//0041C522 85 C0 test eax,eax
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//0041C524 75 01 jne 0041C527
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@ -2224,6 +2231,7 @@ void Compile_R4300i_SH (BLOCK_SECTION * Section){
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MoveX86RegToX86Reg(TempReg1, TempReg2);
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ShiftRightUnsignImmed(TempReg2,12);
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MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
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CompileWriteTLBMiss(Section, TempReg1, TempReg2);
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//For tlb miss
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//0041C522 85 C0 test eax,eax
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//0041C524 75 01 jne 0041C527
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@ -2339,6 +2347,7 @@ void Compile_R4300i_SWL (BLOCK_SECTION * Section) {
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MoveX86RegToX86Reg(TempReg1, TempReg2);
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ShiftRightUnsignImmed(TempReg2,12);
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MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
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CompileWriteTLBMiss(Section, TempReg1, TempReg2);
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MoveX86regToX86regPointer(Value,TempReg1, TempReg2);
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} else {
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@ -2404,6 +2413,7 @@ void Compile_R4300i_SW (BLOCK_SECTION * Section){
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MoveX86RegToX86Reg(TempReg1, TempReg2);
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ShiftRightUnsignImmed(TempReg2,12);
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MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
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CompileWriteTLBMiss(Section, TempReg1, TempReg2);
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//For tlb miss
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//0041C522 85 C0 test eax,eax
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//0041C524 75 01 jne 0041C527
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@ -2518,6 +2528,7 @@ void Compile_R4300i_SWR (BLOCK_SECTION * Section) {
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MoveX86RegToX86Reg(TempReg1, TempReg2);
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ShiftRightUnsignImmed(TempReg2,12);
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MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
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CompileWriteTLBMiss(Section, TempReg1, TempReg2);
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MoveX86regToX86regPointer(Value,TempReg1, TempReg2);
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} else {
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@ -2757,6 +2768,7 @@ void Compile_R4300i_SC (BLOCK_SECTION * Section){
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MoveX86RegToX86Reg(TempReg1, TempReg2);
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ShiftRightUnsignImmed(TempReg2,12);
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MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
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CompileWriteTLBMiss(Section, TempReg1, TempReg2);
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//For tlb miss
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//0041C522 85 C0 test eax,eax
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//0041C524 75 01 jne 0041C527
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@ -2916,6 +2928,7 @@ void Compile_R4300i_SD (BLOCK_SECTION * Section){
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MoveX86RegToX86Reg(TempReg1, TempReg2);
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ShiftRightUnsignImmed(TempReg2,12);
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MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
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CompileWriteTLBMiss(Section, TempReg1, TempReg2);
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//For tlb miss
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//0041C522 85 C0 test eax,eax
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//0041C524 75 01 jne 0041C527
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