Handle TLB miss on writes.

This commit is contained in:
hacktarux
2024-02-20 01:34:23 +01:00
parent c8282a630b
commit ef9264af4d
3 changed files with 26 additions and 0 deletions

View File

@ -680,6 +680,18 @@ void CompileExit (DWORD TargetPC, REG_INFO ExitRegSet, int reason, int CompileNo
if (CPU_Type == CPU_SyncCores) { Call_Direct(SyncToPC, "SyncToPC"); }
Ret();
break;
case TLBWriteMiss:
MoveVariableToX86reg(&TLBLoadAddress, "TLBLoadAddress", x86_EDX);
MoveX86RegToX86Reg(x86_EDX, x86_ECX);
ShiftRightSignImmed(x86_ECX, 31);
Push(x86_ECX);
Push(x86_EDX);
MoveConstToX86reg(NextInstruction == JUMP || NextInstruction == DELAY_SLOT, x86_ECX);
MoveConstToX86reg(0, x86_EDX);
Call_Direct(DoTLBMiss, "DoTLBMiss");
if (CPU_Type == CPU_SyncCores) { Call_Direct(SyncToPC, "SyncToPC"); }
Ret();
break;
default:
if (ShowDebugMessages)
DisplayError("how did you want to exit on reason (%d) ???",reason);

View File

@ -46,6 +46,7 @@
#define DoBreak 7
#define DoIlleaglOp 8
#define DoTrap 9
#define TLBWriteMiss 10
#define STATE_KNOWN_VALUE 1
//#define STATE_UNKNOW_VALUE

View File

@ -38,6 +38,12 @@ void CompileReadTLBMiss (BLOCK_SECTION * Section, int AddressReg, int LookUpReg
CompileExit(Section->CompilePC,Section->RegWorking,TLBReadMiss,FALSE,JeLabel32);
}
void CompileWriteTLBMiss(BLOCK_SECTION* Section, int AddressReg, int LookUpReg) {
MoveX86regToVariable(AddressReg, &TLBLoadAddress, "TLBLoadAddress");
TestX86RegToX86Reg(LookUpReg, LookUpReg);
CompileExit(Section->CompilePC, Section->RegWorking, TLBWriteMiss, FALSE, JeLabel32);
}
/************************** Branch functions ************************/
void Compile_R4300i_Branch (BLOCK_SECTION * Section, void (*CompareFunc)(BLOCK_SECTION * Section), int BranchType, BOOL Link) {
MIPS_DWORD CompilePC;
@ -2142,6 +2148,7 @@ void Compile_R4300i_SB (BLOCK_SECTION * Section){
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2,12);
MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
CompileWriteTLBMiss(Section, TempReg1, TempReg2);
//For tlb miss
//0041C522 85 C0 test eax,eax
//0041C524 75 01 jne 0041C527
@ -2224,6 +2231,7 @@ void Compile_R4300i_SH (BLOCK_SECTION * Section){
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2,12);
MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
CompileWriteTLBMiss(Section, TempReg1, TempReg2);
//For tlb miss
//0041C522 85 C0 test eax,eax
//0041C524 75 01 jne 0041C527
@ -2339,6 +2347,7 @@ void Compile_R4300i_SWL (BLOCK_SECTION * Section) {
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2,12);
MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
CompileWriteTLBMiss(Section, TempReg1, TempReg2);
MoveX86regToX86regPointer(Value,TempReg1, TempReg2);
} else {
@ -2404,6 +2413,7 @@ void Compile_R4300i_SW (BLOCK_SECTION * Section){
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2,12);
MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
CompileWriteTLBMiss(Section, TempReg1, TempReg2);
//For tlb miss
//0041C522 85 C0 test eax,eax
//0041C524 75 01 jne 0041C527
@ -2518,6 +2528,7 @@ void Compile_R4300i_SWR (BLOCK_SECTION * Section) {
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2,12);
MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
CompileWriteTLBMiss(Section, TempReg1, TempReg2);
MoveX86regToX86regPointer(Value,TempReg1, TempReg2);
} else {
@ -2757,6 +2768,7 @@ void Compile_R4300i_SC (BLOCK_SECTION * Section){
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2,12);
MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
CompileWriteTLBMiss(Section, TempReg1, TempReg2);
//For tlb miss
//0041C522 85 C0 test eax,eax
//0041C524 75 01 jne 0041C527
@ -2916,6 +2928,7 @@ void Compile_R4300i_SD (BLOCK_SECTION * Section){
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2,12);
MoveVariableDispToX86Reg(TLB_WriteMap,"TLB_WriteMap",TempReg2,TempReg2,4);
CompileWriteTLBMiss(Section, TempReg1, TempReg2);
//For tlb miss
//0041C522 85 C0 test eax,eax
//0041C524 75 01 jne 0041C527