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dt-bindings: clock: qcom: Update the clocks for GCC/GPUCC/DISPCC

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Update the clock ids to be used by clients from GCC, GPUCC and DISPCC.

Change-Id: I31fd8f8872f5e0c17fe97de9fdd70d13a17c349c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das
2019-08-14 13:42:19 +05:30
parent e56fe93841
commit 68e8b42ae5
3 changed files with 105 additions and 135 deletions
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4
include/dt-bindings/clock/qcom,dispcc-bengal.h
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@ -32,8 +32,4 @@
#define DISP_CC_XO_CLK 22
#define DISP_CC_XO_CLK_SRC 23
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_RSCC_BCR 1
#endif

212
include/dt-bindings/clock/qcom,gcc-bengal.h
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@ -65,8 +65,6 @@
#define GCC_CAMSS_TOP_AHB_CLK_SRC 55
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 56
#define GCC_CPUSS_AHB_CLK 57
#define GCC_CPUSS_AHB_CLK_SRC 58
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 59
#define GCC_CPUSS_GNOC_CLK 60
#define GCC_CPUSS_THROTTLE_CORE_CLK 61
#define GCC_CPUSS_THROTTLE_XO_CLK 62
@ -89,123 +87,101 @@
#define GCC_GPU_SNOC_DVM_GFX_CLK 79
#define GCC_GPU_THROTTLE_CORE_CLK 80
#define GCC_GPU_THROTTLE_XO_CLK 81
#define GCC_MSS_VS_CLK 82
#define GCC_PDM2_CLK 83
#define GCC_PDM2_CLK_SRC 84
#define GCC_PDM_AHB_CLK 85
#define GCC_PDM_XO4_CLK 86
#define GCC_PRNG_AHB_CLK 87
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 88
#define GCC_QMIP_CAMERA_RT_AHB_CLK 89
#define GCC_QMIP_CPUSS_CFG_AHB_CLK 90
#define GCC_QMIP_DISP_AHB_CLK 91
#define GCC_QMIP_GPU_CFG_AHB_CLK 92
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 93
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 94
#define GCC_QUPV3_WRAP0_CORE_CLK 95
#define GCC_QUPV3_WRAP0_S0_CLK 96
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 97
#define GCC_QUPV3_WRAP0_S1_CLK 98
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 99
#define GCC_QUPV3_WRAP0_S2_CLK 100
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 101
#define GCC_QUPV3_WRAP0_S3_CLK 102
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 103
#define GCC_QUPV3_WRAP0_S4_CLK 104
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 105
#define GCC_QUPV3_WRAP0_S5_CLK 106
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 107
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 108
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 109
#define GCC_SDCC1_AHB_CLK 110
#define GCC_SDCC1_APPS_CLK 111
#define GCC_SDCC1_APPS_CLK_SRC 112
#define GCC_SDCC1_ICE_CORE_CLK 113
#define GCC_SDCC1_ICE_CORE_CLK_SRC 114
#define GCC_SDCC2_AHB_CLK 115
#define GCC_SDCC2_APPS_CLK 116
#define GCC_SDCC2_APPS_CLK_SRC 117
#define GCC_SYS_NOC_CPUSS_AHB_CLK 118
#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 119
#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 120
#define GCC_UFS_PHY_AHB_CLK 121
#define GCC_UFS_PHY_AXI_CLK 122
#define GCC_UFS_PHY_AXI_CLK_SRC 123
#define GCC_UFS_PHY_ICE_CORE_CLK 124
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 125
#define GCC_UFS_PHY_PHY_AUX_CLK 126
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 127
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 128
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 129
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 130
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 131
#define GCC_USB30_PRIM_MASTER_CLK 132
#define GCC_USB30_PRIM_MASTER_CLK_SRC 133
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 134
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 135
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 136
#define GCC_USB30_PRIM_SLEEP_CLK 137
#define GCC_USB3_PRIM_CLKREF_CLK 138
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 139
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 140
#define GCC_USB3_PRIM_PHY_PIPE_CLK 141
#define GCC_VCODEC0_AXI_CLK 142
#define GCC_VDDA_VS_CLK 143
#define GCC_VDDCX_VS_CLK 144
#define GCC_VDDMX_VS_CLK 145
#define GCC_VENUS_AHB_CLK 146
#define GCC_VENUS_CTL_AXI_CLK 147
#define GCC_VIDEO_AHB_CLK 148
#define GCC_VIDEO_AXI0_CLK 149
#define GCC_VIDEO_THROTTLE_CORE_CLK 150
#define GCC_VIDEO_VCODEC0_SYS_CLK 151
#define GCC_VIDEO_VENUS_CLK_SRC 152
#define GCC_VIDEO_VENUS_CTL_CLK 153
#define GCC_VIDEO_XO_CLK 154
#define GCC_VS_CTRL_AHB_CLK 155
#define GCC_VS_CTRL_CLK 156
#define GCC_VS_CTRL_CLK_SRC 157
#define GCC_VSENSOR_CLK_SRC 158
#define GCC_WCSS_VS_CLK 159
#define GCC_AHB2PHY_CSI_CLK 160
#define GCC_AHB2PHY_USB_CLK 161
#define GCC_APC_VS_CLK 162
#define GCC_BIMC_GPU_AXI_CLK 163
#define GCC_BOOT_ROM_AHB_CLK 164
#define GCC_CAM_THROTTLE_NRT_CLK 165
#define GCC_CAM_THROTTLE_RT_CLK 166
#define GCC_CAMERA_AHB_CLK 167
#define GCC_CAMERA_XO_CLK 168
#define GCC_CAMSS_AXI_CLK 169
#define GCC_CAMSS_AXI_CLK_SRC 170
#define GCC_CAMSS_CAMNOC_ATB_CLK 171
#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 172
#define GCC_CAMSS_CCI_0_CLK 173
#define GCC_CAMSS_CCI_CLK_SRC 174
#define GCC_CAMSS_CPHY_0_CLK 175
#define GCC_CAMSS_CPHY_1_CLK 176
#define GCC_CAMSS_CPHY_2_CLK 177
#define GCC_PDM2_CLK 82
#define GCC_PDM2_CLK_SRC 83
#define GCC_PDM_AHB_CLK 84
#define GCC_PDM_XO4_CLK 85
#define GCC_PRNG_AHB_CLK 86
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 87
#define GCC_QMIP_CAMERA_RT_AHB_CLK 88
#define GCC_QMIP_CPUSS_CFG_AHB_CLK 89
#define GCC_QMIP_DISP_AHB_CLK 90
#define GCC_QMIP_GPU_CFG_AHB_CLK 91
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 92
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 93
#define GCC_QUPV3_WRAP0_CORE_CLK 94
#define GCC_QUPV3_WRAP0_S0_CLK 95
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 96
#define GCC_QUPV3_WRAP0_S1_CLK 97
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 98
#define GCC_QUPV3_WRAP0_S2_CLK 99
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 100
#define GCC_QUPV3_WRAP0_S3_CLK 101
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 102
#define GCC_QUPV3_WRAP0_S4_CLK 103
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 104
#define GCC_QUPV3_WRAP0_S5_CLK 105
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 106
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 107
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 108
#define GCC_SDCC1_AHB_CLK 109
#define GCC_SDCC1_APPS_CLK 110
#define GCC_SDCC1_APPS_CLK_SRC 111
#define GCC_SDCC1_ICE_CORE_CLK 112
#define GCC_SDCC1_ICE_CORE_CLK_SRC 113
#define GCC_SDCC2_AHB_CLK 114
#define GCC_SDCC2_APPS_CLK 115
#define GCC_SDCC2_APPS_CLK_SRC 116
#define GCC_SYS_NOC_CPUSS_AHB_CLK 117
#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 118
#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 119
#define GCC_UFS_PHY_AHB_CLK 120
#define GCC_UFS_PHY_AXI_CLK 121
#define GCC_UFS_PHY_AXI_CLK_SRC 122
#define GCC_UFS_PHY_ICE_CORE_CLK 123
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 124
#define GCC_UFS_PHY_PHY_AUX_CLK 125
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 126
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 127
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 128
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 129
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 130
#define GCC_USB30_PRIM_MASTER_CLK 131
#define GCC_USB30_PRIM_MASTER_CLK_SRC 132
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 133
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 134
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 135
#define GCC_USB30_PRIM_SLEEP_CLK 136
#define GCC_USB3_PRIM_CLKREF_CLK 137
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 138
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 139
#define GCC_USB3_PRIM_PHY_PIPE_CLK 140
#define GCC_VCODEC0_AXI_CLK 141
#define GCC_VENUS_AHB_CLK 142
#define GCC_VENUS_CTL_AXI_CLK 143
#define GCC_VIDEO_AHB_CLK 144
#define GCC_VIDEO_AXI0_CLK 145
#define GCC_VIDEO_THROTTLE_CORE_CLK 146
#define GCC_VIDEO_VCODEC0_SYS_CLK 147
#define GCC_VIDEO_VENUS_CLK_SRC 148
#define GCC_VIDEO_VENUS_CTL_CLK 149
#define GCC_VIDEO_XO_CLK 150
#define GCC_AHB2PHY_CSI_CLK 151
#define GCC_AHB2PHY_USB_CLK 152
#define GCC_BIMC_GPU_AXI_CLK 153
#define GCC_BOOT_ROM_AHB_CLK 154
#define GCC_CAM_THROTTLE_NRT_CLK 155
#define GCC_CAM_THROTTLE_RT_CLK 156
#define GCC_CAMERA_AHB_CLK 157
#define GCC_CAMERA_XO_CLK 158
#define GCC_CAMSS_AXI_CLK 159
#define GCC_CAMSS_AXI_CLK_SRC 160
#define GCC_CAMSS_CAMNOC_ATB_CLK 161
#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 162
#define GCC_CAMSS_CCI_0_CLK 163
#define GCC_CAMSS_CCI_CLK_SRC 164
#define GCC_CAMSS_CPHY_0_CLK 165
#define GCC_CAMSS_CPHY_1_CLK 166
#define GCC_CAMSS_CPHY_2_CLK 167
/* GCC resets */
#define GCC_CAMSS_OPE_BCR 0
#define GCC_CAMSS_TFE_BCR 1
#define GCC_CAMSS_TOP_BCR 2
#define GCC_GPU_BCR 3
#define GCC_MMSS_BCR 4
#define GCC_PDM_BCR 5
#define GCC_PRNG_BCR 6
#define GCC_QUPV3_WRAPPER_0_BCR 7
#define GCC_QUPV3_WRAPPER_1_BCR 8
#define GCC_QUSB2PHY_PRIM_BCR 9
#define GCC_QUSB2PHY_SEC_BCR 10
#define GCC_SDCC1_BCR 11
#define GCC_SDCC2_BCR 12
#define GCC_UFS_PHY_BCR 13
#define GCC_USB30_PRIM_BCR 14
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15
#define GCC_VCODEC0_BCR 16
#define GCC_VENUS_BCR 17
#define GCC_VIDEO_INTERFACE_BCR 18
#define GCC_VS_BCR 19
#define GCC_QUSB2PHY_PRIM_BCR 0
#define GCC_QUSB2PHY_SEC_BCR 2
#define GCC_UFS_PHY_BCR 3
#define GCC_USB30_PRIM_BCR 4
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 5
#define GCC_VCODEC0_BCR 6
#define GCC_VENUS_BCR 7
#define GCC_VIDEO_INTERFACE_BCR 8
#endif

24
include/dt-bindings/clock/qcom,gpucc-bengal.h
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@ -7,25 +7,23 @@
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BENGAL_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CRC_AHB_CLK 1
#define GPU_CC_CX_APB_CLK 2
#define GPU_CC_CX_GFX3D_CLK 3
#define GPU_CC_CX_GFX3D_SLV_CLK 4
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_PLL0 0
#define GPU_CC_PLL0_OUT_AUX2 1
#define GPU_CC_PLL1 2
#define GPU_CC_PLL1_OUT_AUX 3
#define GPU_CC_AHB_CLK 4
#define GPU_CC_CRC_AHB_CLK 5
#define GPU_CC_CX_GFX3D_CLK 6
#define GPU_CC_CX_GFX3D_SLV_CLK 7
#define GPU_CC_CX_GMU_CLK 8
#define GPU_CC_CX_SNOC_DVM_CLK 9
#define GPU_CC_CXO_AON_CLK 10
#define GPU_CC_CXO_CLK 11
#define GPU_CC_GMU_CLK_SRC 12
#define GPU_CC_GX_CXO_CLK 13
#define GPU_CC_GX_GFX3D_CLK 14
#define GPU_CC_GX_GFX3D_CLK_SRC 15
#define GPU_CC_SLEEP_CLK 16
/* GPU_CC resets */
#define GPUCC_GPU_CC_CX_BCR 0
#define GPUCC_GPU_CC_GFX3D_AON_BCR 1
#define GPUCC_GPU_CC_GMU_BCR 2
#define GPUCC_GPU_CC_GX_BCR 3
#define GPUCC_GPU_CC_XO_BCR 4
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17
#endif