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Merge "coresight-etm4x: enable ETM driver on SDM845"

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qctecmdr Service
2018-10-03 08:44:18 -07:00
committed by Gerrit - the friendly Code Review server
parent d82f734bc4 c992c8473d
commit aa810ad47c
3 changed files with 9 additions and 9 deletions
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10
drivers/hwtracing/coresight/coresight-etm4x.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
* Copyright (c) 2014,2016, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
@ -55,7 +55,7 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
static bool etm4_arch_supported(u8 arch)
{
switch (arch) {
case ETM_ARCH_V4:
case ETM_ARCH_MAJOR_V4:
break;
default:
return false;
@ -483,7 +483,7 @@ static void etm4_init_arch_data(void *info)
* TRCARCHMIN, bits[7:4] architecture the minor version number
* TRCARCHMAJ, bits[11:8] architecture major versin number
*/
drvdata->arch = BMVAL(etmidr1, 4, 11);
drvdata->arch = BMVAL(etmidr1, 8, 11);
/* maximum size of resources */
etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
@ -529,8 +529,8 @@ static void etm4_init_arch_data(void *info)
else
drvdata->sysstall = false;
/* NUMPROC, bits[30:28] the number of PEs available for tracing */
drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
/* NUMPROC, bits[13:12, 30:28] the number of PEs available for trace */
drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
/* NOOVERFLOW, bit[31] is trace overflow prevention supported */
if (BMVAL(etmidr3, 31, 31))

4
drivers/hwtracing/coresight/coresight-etm4x.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*/
#ifndef _CORESIGHT_CORESIGHT_ETM_H
@ -136,7 +136,7 @@
#define ETM_MAX_RES_SEL 16
#define ETM_MAX_SS_CMP 8
#define ETM_ARCH_V4 0x40
#define ETM_ARCH_MAJOR_V4 0x4
#define ETMv4_SYNC_MASK 0x1F
#define ETM_CYC_THRESHOLD_MASK 0xFFF
#define ETM_CYC_THRESHOLD_DEFAULT 0x100

4
include/linux/coresight-pmu.h
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@ -8,7 +8,7 @@
#define _LINUX_CORESIGHT_PMU_H
#define CORESIGHT_ETM_PMU_NAME "cs_etm"
#define CORESIGHT_ETM_PMU_SEED 0x10
#define CORESIGHT_ETM_PMU_SEED 0x01
/* ETMv3.5/PTM's ETMCR config bit */
#define ETM_OPT_CYCACC 12
@ -28,7 +28,7 @@ static inline int coresight_get_trace_id(int cpu)
* the common convention is to have data trace IDs be I(N) + 1,
* set instruction trace IDs as a function of the CPU number.
*/
return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
return (CORESIGHT_ETM_PMU_SEED + cpu);
}
#endif