mirror of
https://github.com/hathach/tinyusb.git
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rename FSDEV_PMA_SIZE CFG_TUSB_FSDEV_PMA_SIZE
This commit is contained in:
hathach
@ -179,12 +179,12 @@
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#elif TU_CHECK_MCU(OPT_MCU_STM32C0)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 2048u
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#define CFG_TUSB_FSDEV_PMA_SIZE 2048u
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#elif TU_CHECK_MCU(OPT_MCU_STM32F0)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 1024u
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#define CFG_TUSB_FSDEV_PMA_SIZE 1024u
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#elif TU_CHECK_MCU(OPT_MCU_STM32F1)
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// - F102, F103 use fsdev
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@ -200,7 +200,7 @@
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defined(STM32F103xE) || defined(STM32F103xG)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 512u
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#define CFG_TUSB_FSDEV_PMA_SIZE 512u
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#else
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#error "Unsupported STM32F1 mcu"
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#endif
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@ -218,10 +218,10 @@
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#if defined(STM32F302xB) || defined(STM32F302xC) || defined(STM32F303xB) || defined(STM32F303xC) || \
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defined(STM32F373xC)
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#define FSDEV_PMA_SIZE 512u
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#define CFG_TUSB_FSDEV_PMA_SIZE 512u
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#elif defined(STM32F302x6) || defined(STM32F302x8) || defined(STM32F302xD) || defined(STM32F302xE) || \
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defined(STM32F303xD) || defined(STM32F303xE)
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#define FSDEV_PMA_SIZE 1024u
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#define CFG_TUSB_FSDEV_PMA_SIZE 1024u
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#else
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#error "Unsupported STM32F3 mcu"
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#endif
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@ -253,13 +253,13 @@
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#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 2048u
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#define CFG_TUSB_FSDEV_PMA_SIZE 2048u
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#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
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// Device controller
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 1024u
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#define CFG_TUSB_FSDEV_PMA_SIZE 1024u
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// TypeC controller
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#define TUP_USBIP_TYPEC_STM32
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@ -268,7 +268,7 @@
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#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 2048u
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#define CFG_TUSB_FSDEV_PMA_SIZE 2048u
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#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
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#include "stm32h7xx.h"
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@ -302,12 +302,12 @@
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#elif TU_CHECK_MCU(OPT_MCU_STM32L0)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 1024u
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#define CFG_TUSB_FSDEV_PMA_SIZE 1024u
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#elif TU_CHECK_MCU(OPT_MCU_STM32L1)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 512u
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#define CFG_TUSB_FSDEV_PMA_SIZE 512u
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#elif TU_CHECK_MCU(OPT_MCU_STM32L4)
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// - L4x2, L4x3 use fsdev
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@ -324,7 +324,7 @@
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defined(STM32L442xx) || defined(STM32L443xx) || defined(STM32L452xx) || defined(STM32L462xx)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 1024u
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#define CFG_TUSB_FSDEV_PMA_SIZE 1024u
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#else
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#error "Unsupported STM32L4 mcu"
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#endif
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@ -332,24 +332,24 @@
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#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE (1024u)
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#define CFG_TUSB_FSDEV_PMA_SIZE (1024u)
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#elif TU_CHECK_MCU(OPT_MCU_STM32U0)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 1024u
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#define CFG_TUSB_FSDEV_PMA_SIZE 1024u
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#elif TU_CHECK_MCU(OPT_MCU_STM32U3)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 2048u
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#define CFG_TUSB_FSDEV_PMA_SIZE 2048u
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#elif TU_CHECK_MCU(OPT_MCU_STM32U5)
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// U535/545 use fsdev
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#if defined(STM32U535xx) || defined(STM32U545xx)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 2048u
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#define CFG_TUSB_FSDEV_PMA_SIZE 2048u
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#else
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#define TUP_USBIP_DWC2
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#define TUP_USBIP_DWC2_STM32
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@ -367,7 +367,7 @@
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#elif TU_CHECK_MCU(OPT_MCU_STM32WB)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_STM32
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#define FSDEV_PMA_SIZE 1024u
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#define CFG_TUSB_FSDEV_PMA_SIZE 1024u
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#elif TU_CHECK_MCU(OPT_MCU_STM32WBA)
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#define TUP_USBIP_DWC2
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@ -572,7 +572,7 @@
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_CH32
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#define FSDEV_PMA_SIZE 512u
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#define CFG_TUSB_FSDEV_PMA_SIZE 512u
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// default to FSDEV for device
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#if !defined(CFG_TUD_WCH_USBIP_USBFS)
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@ -621,7 +621,7 @@
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#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407, OPT_MCU_AT32F413)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_AT32
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#define FSDEV_PMA_SIZE 512u
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#define CFG_TUSB_FSDEV_PMA_SIZE 512u
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#elif TU_CHECK_MCU(OPT_MCU_AT32F415)
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#define TUP_USBIP_DWC2
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@ -108,11 +108,10 @@
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#include "tusb_option.h"
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#if CFG_TUD_ENABLED && defined(TUP_USBIP_FSDEV) && \
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!(defined(TUP_USBIP_FSDEV_CH32) && CFG_TUD_WCH_USBIP_FSDEV == 0)
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#if CFG_TUD_ENABLED && defined(TUP_USBIP_FSDEV) && !(defined(TUP_USBIP_FSDEV_CH32) && CFG_TUD_WCH_USBIP_FSDEV == 0)
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#include "device/dcd.h"
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#include "fsdev_common.h"
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#include "device/dcd.h"
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#include "fsdev_common.h"
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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@ -120,25 +119,25 @@
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// One of these for every EP IN & OUT, uses a bit of RAM....
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typedef struct {
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uint8_t *buffer;
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uint8_t *buffer;
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tu_fifo_t *ff;
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uint16_t total_len;
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uint16_t queued_len;
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uint16_t max_packet_size;
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uint8_t ep_idx; // index for USB_EPnR register
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bool iso_in_sending; // Workaround for ISO IN EP doesn't have interrupt mask
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uint16_t total_len;
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uint16_t queued_len;
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uint16_t max_packet_size;
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uint8_t ep_idx; // index for USB_EPnR register
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bool iso_in_sending; // Workaround for ISO IN EP doesn't have interrupt mask
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} xfer_ctl_t;
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// EP allocator
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typedef struct {
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uint8_t ep_num;
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uint8_t ep_type;
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bool allocated[2];
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bool allocated[2];
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} ep_alloc_t;
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static xfer_ctl_t xfer_status[CFG_TUD_ENDPPOINT_MAX][2];
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static ep_alloc_t ep_alloc_status[FSDEV_EP_COUNT];
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static uint8_t remoteWakeCountdown; // When wake is requested
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static uint8_t remoteWakeCountdown; // When wake is requested
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//--------------------------------------------------------------------+
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// Prototypes
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@ -152,12 +151,12 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir);
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// PMA allocation/access
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static uint16_t ep_buf_ptr; ///< Points to first free memory location
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static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf);
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static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
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static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
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static void edpt0_open(uint8_t rhport);
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TU_ATTR_ALWAYS_INLINE static inline void edpt0_prepare_setup(void) {
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btable_set_rx_bufsize(0, BTABLE_BUF_RX, 8);
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btable_set_rx_bufsize(0, BTABLE_BUF_RX, 8);
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}
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//--------------------------------------------------------------------+
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@ -171,21 +170,21 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint8_t epnum, uint
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
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bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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(void) rh_init;
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bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
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(void)rh_init;
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fsdev_core_reset();
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FSDEV_REG->CNTR = 0; // Enable USB
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#if !defined(FSDEV_BUS_32BIT)
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#if !defined(FSDEV_BUS_32BIT)
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// BTABLE register does not exist any more on 32-bit bus devices
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FSDEV_REG->BTABLE = FSDEV_BTABLE_BASE;
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#endif
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#endif
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// Enable interrupts for device mode
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FSDEV_REG->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM |
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USB_CNTR_SUSPM | USB_CNTR_WKUPM | USB_CNTR_PMAOVRM;
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FSDEV_REG->CNTR |=
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USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM | USB_CNTR_PMAOVRM;
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handle_bus_reset(rhport);
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@ -236,8 +235,8 @@ static void handle_bus_reset(uint8_t rhport) {
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for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {
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// Clear EP allocation status
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ep_alloc_status[i].ep_num = 0xFF;
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ep_alloc_status[i].ep_type = 0xFF;
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ep_alloc_status[i].ep_num = 0xFF;
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ep_alloc_status[i].ep_type = 0xFF;
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ep_alloc_status[i].allocated[0] = false;
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ep_alloc_status[i].allocated[1] = false;
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}
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@ -245,7 +244,7 @@ static void handle_bus_reset(uint8_t rhport) {
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// Reset PMA allocation
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ep_buf_ptr = FSDEV_BTABLE_BASE + 8 * FSDEV_EP_COUNT;
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edpt0_open(rhport); // open control endpoint (both IN & OUT)
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edpt0_open(rhport); // open control endpoint (both IN & OUT)
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FSDEV_REG->DADDR = USB_DADDR_EF; // Enable USB Function
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}
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@ -254,8 +253,8 @@ static void handle_bus_reset(uint8_t rhport) {
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static void handle_ctr_tx(uint32_t ep_id) {
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uint32_t ep_reg = ep_read(ep_id) | USB_EP_CTR_TX | USB_EP_CTR_RX;
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uint8_t const ep_num = ep_reg & USB_EPADDR_FIELD;
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xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_IN);
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const uint8_t ep_num = ep_reg & USB_EPADDR_FIELD;
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xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_IN);
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if (ep_is_iso(ep_reg)) {
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// Ignore spurious interrupts that we don't schedule
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@ -265,11 +264,11 @@ static void handle_ctr_tx(uint32_t ep_id) {
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return;
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}
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xfer->iso_in_sending = false;
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#if FSDEV_USE_SBUF_ISO == 0
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#if FSDEV_USE_SBUF_ISO == 0
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uint8_t buf_id = (ep_reg & USB_EP_DTOG_TX) ? 0 : 1;
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#else
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#else
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uint8_t buf_id = BTABLE_BUF_TX;
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#endif
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#endif
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btable_set_count(ep_id, buf_id, 0);
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}
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@ -282,8 +281,8 @@ static void handle_ctr_tx(uint32_t ep_id) {
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static void handle_ctr_setup(uint32_t ep_id) {
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uint16_t rx_count = btable_get_count(ep_id, BTABLE_BUF_RX);
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uint16_t rx_addr = btable_get_addr(ep_id, BTABLE_BUF_RX);
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uint8_t setup_packet[8] TU_ATTR_ALIGNED(4);
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uint16_t rx_addr = btable_get_addr(ep_id, BTABLE_BUF_RX);
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uint8_t setup_packet[8] TU_ATTR_ALIGNED(4);
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tu_hwfifo_read(PMA_BUF_AT(rx_addr), setup_packet, rx_count, NULL);
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@ -292,7 +291,7 @@ static void handle_ctr_setup(uint32_t ep_id) {
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// Setup packet should always be 8 bytes. If not, we probably missed the packet
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if (rx_count == 8) {
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dcd_event_setup_received(0, (uint8_t*) setup_packet, true);
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dcd_event_setup_received(0, (uint8_t *)setup_packet, true);
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// Hardware should reset EP0 RX/TX to NAK and both toggle to 1
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} else {
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// Missed setup packet !!!
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@ -303,24 +302,24 @@ static void handle_ctr_setup(uint32_t ep_id) {
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// Handle CTR interrupt for the RX/OUT direction
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static void handle_ctr_rx(uint32_t ep_id) {
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uint32_t ep_reg = ep_read(ep_id) | USB_EP_CTR_TX | USB_EP_CTR_RX;
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uint8_t const ep_num = ep_reg & USB_EPADDR_FIELD;
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bool const is_iso = ep_is_iso(ep_reg);
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xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_OUT);
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uint32_t ep_reg = ep_read(ep_id) | USB_EP_CTR_TX | USB_EP_CTR_RX;
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const uint8_t ep_num = ep_reg & USB_EPADDR_FIELD;
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const bool is_iso = ep_is_iso(ep_reg);
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xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_OUT);
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uint8_t buf_id;
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#if FSDEV_USE_SBUF_ISO == 0
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#if FSDEV_USE_SBUF_ISO == 0
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bool const dbl_buf = is_iso;
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#else
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#else
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bool const dbl_buf = false;
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#endif
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#endif
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if (dbl_buf) {
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buf_id = (ep_reg & USB_EP_DTOG_RX) ? 0 : 1;
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} else {
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buf_id = BTABLE_BUF_RX;
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}
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const uint16_t rx_count = btable_get_count(ep_id, buf_id);
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uint16_t pma_addr = (uint16_t) btable_get_addr(ep_id, buf_id);
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const uint16_t rx_count = btable_get_count(ep_id, buf_id);
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uint16_t pma_addr = (uint16_t)btable_get_addr(ep_id, buf_id);
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fsdev_pma_buf_t *pma_buf = PMA_BUF_AT(pma_addr);
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if (xfer->ff) {
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@ -344,7 +343,7 @@ static void handle_ctr_rx(uint32_t ep_id) {
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} else {
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// Set endpoint active again for receiving more data. Note that isochronous endpoints stay active always
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if (!is_iso) {
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uint16_t const cnt = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
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const uint16_t cnt = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
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btable_set_rx_bufsize(ep_id, BTABLE_BUF_RX, cnt);
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}
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ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(TUSB_DIR_OUT); // will change RX Status, reserved other toggle bits
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@ -404,18 +403,18 @@ void dcd_int_handler(uint8_t rhport) {
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// loop to handle all pending CTR interrupts
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while (FSDEV_REG->ISTR & USB_ISTR_CTR) {
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// skip DIR bit, and use CTR TX/RX instead, since there is chance we have both TX/RX completed in one interrupt
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uint32_t const ep_id = FSDEV_REG->ISTR & USB_ISTR_EP_ID;
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uint32_t const ep_reg = ep_read(ep_id);
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const uint32_t ep_id = FSDEV_REG->ISTR & USB_ISTR_EP_ID;
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const uint32_t ep_reg = ep_read(ep_id);
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if (ep_reg & USB_EP_CTR_RX) {
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#ifdef FSDEV_BUS_32BIT
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#ifdef FSDEV_BUS_32BIT
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/* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf
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* https://www.st.com/resource/en/errata_sheet/es0587-stm32u535xx-and-stm32u545xx-device-errata-stmicroelectronics.pdf
|
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* From H503/U535 errata: Buffer description table update completes after CTR interrupt triggers
|
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* Description:
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* - During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
|
||||
* have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
|
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* Workaround:
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* - During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM
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* accesses have completed. If the software responds quickly to the interrupt, the full buffer contents may not be
|
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* correct. Workaround:
|
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* - Software should ensure that a small delay is included before accessing the SRAM contents. This delay
|
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* should be 800 ns in Full Speed mode and 6.4 μs in Low Speed mode
|
||||
* - Since H5 can run up to 250Mhz -> 1 cycle = 4ns. Per errata, we need to wait 200 cycles. Though executing code
|
||||
@ -426,9 +425,9 @@ void dcd_int_handler(uint8_t rhport) {
|
||||
*/
|
||||
volatile uint32_t cycle_count = 20; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
|
||||
while (cycle_count > 0U) {
|
||||
cycle_count--; // each count take 3 cycles (1 for sub, jump, and compare)
|
||||
cycle_count--; // each count take 3 cycles (1 for sub, jump, and compare)
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (ep_reg & USB_EP_SETUP) {
|
||||
handle_ctr_setup(ep_id); // CTR will be clear after copied setup packet
|
||||
@ -456,14 +455,13 @@ void dcd_int_handler(uint8_t rhport) {
|
||||
|
||||
// Invoked when a control transfer's status stage is complete.
|
||||
// May help DCD to prepare for next control transfer, this API is optional.
|
||||
void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
|
||||
void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_request_t *request) {
|
||||
(void)rhport;
|
||||
|
||||
if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
|
||||
request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
|
||||
request->bRequest == TUSB_REQ_SET_ADDRESS) {
|
||||
uint8_t const dev_addr = (uint8_t)request->wValue;
|
||||
FSDEV_REG->DADDR = (USB_DADDR_EF | dev_addr);
|
||||
request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_ADDRESS) {
|
||||
const uint8_t dev_addr = (uint8_t)request->wValue;
|
||||
FSDEV_REG->DADDR = (USB_DADDR_EF | dev_addr);
|
||||
}
|
||||
|
||||
edpt0_prepare_setup();
|
||||
@ -474,15 +472,14 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *req
|
||||
* In case of double buffering, high 16bit is the address of 2nd buffer
|
||||
* During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
|
||||
*/
|
||||
static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf)
|
||||
{
|
||||
uint8_t blsize, num_block;
|
||||
static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf) {
|
||||
uint8_t blsize, num_block;
|
||||
uint16_t aligned_len = pma_align_buffer_size(len, &blsize, &num_block);
|
||||
(void) blsize;
|
||||
(void) num_block;
|
||||
(void)blsize;
|
||||
(void)num_block;
|
||||
|
||||
uint32_t addr = ep_buf_ptr;
|
||||
ep_buf_ptr = (uint16_t)(ep_buf_ptr + aligned_len); // increment buffer pointer
|
||||
ep_buf_ptr = (uint16_t)(ep_buf_ptr + aligned_len); // increment buffer pointer
|
||||
|
||||
if (dbuf) {
|
||||
addr |= ((uint32_t)ep_buf_ptr) << 16;
|
||||
@ -490,7 +487,7 @@ static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf)
|
||||
}
|
||||
|
||||
// Verify packet buffer is not overflowed
|
||||
TU_ASSERT(ep_buf_ptr <= FSDEV_PMA_SIZE, 0xFFFF);
|
||||
TU_ASSERT(ep_buf_ptr <= CFG_TUSB_FSDEV_PMA_SIZE, 0xFFFF);
|
||||
|
||||
return addr;
|
||||
}
|
||||
@ -498,35 +495,32 @@ static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf)
|
||||
/***
|
||||
* Allocate hardware endpoint
|
||||
*/
|
||||
static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
|
||||
{
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type) {
|
||||
const uint8_t epnum = tu_edpt_number(ep_addr);
|
||||
const uint8_t dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
for (uint8_t i = 0; i < FSDEV_EP_COUNT; i++) {
|
||||
// Check if already allocated
|
||||
if (ep_alloc_status[i].allocated[dir] &&
|
||||
ep_alloc_status[i].ep_type == ep_type &&
|
||||
if (ep_alloc_status[i].allocated[dir] && ep_alloc_status[i].ep_type == ep_type &&
|
||||
ep_alloc_status[i].ep_num == epnum) {
|
||||
return i;
|
||||
}
|
||||
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
bool const dbl_buf = ep_type == TUSB_XFER_ISOCHRONOUS;
|
||||
#else
|
||||
#else
|
||||
bool const dbl_buf = false;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// If EP of current direction is not allocated
|
||||
// For double-buffered mode both directions needs to be free
|
||||
if (!ep_alloc_status[i].allocated[dir] &&
|
||||
(!dbl_buf || !ep_alloc_status[i].allocated[dir ^ 1])) {
|
||||
if (!ep_alloc_status[i].allocated[dir] && (!dbl_buf || !ep_alloc_status[i].allocated[dir ^ 1])) {
|
||||
// Check if EP number is the same
|
||||
if (ep_alloc_status[i].ep_num == 0xFF || ep_alloc_status[i].ep_num == epnum) {
|
||||
// One EP pair has to be the same type
|
||||
if (ep_alloc_status[i].ep_type == 0xFF || ep_alloc_status[i].ep_type == ep_type) {
|
||||
ep_alloc_status[i].ep_num = epnum;
|
||||
ep_alloc_status[i].ep_type = ep_type;
|
||||
ep_alloc_status[i].ep_num = epnum;
|
||||
ep_alloc_status[i].ep_type = ep_type;
|
||||
ep_alloc_status[i].allocated[dir] = true;
|
||||
|
||||
return i;
|
||||
@ -540,16 +534,16 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
|
||||
}
|
||||
|
||||
void edpt0_open(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
(void)rhport;
|
||||
|
||||
dcd_ep_alloc(0x0, TUSB_XFER_CONTROL);
|
||||
dcd_ep_alloc(0x80, TUSB_XFER_CONTROL);
|
||||
|
||||
xfer_status[0][0].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
|
||||
xfer_status[0][0].ep_idx = 0;
|
||||
xfer_status[0][0].ep_idx = 0;
|
||||
|
||||
xfer_status[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
|
||||
xfer_status[0][1].ep_idx = 0;
|
||||
xfer_status[0][1].ep_idx = 0;
|
||||
|
||||
uint16_t pma_addr0 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
|
||||
uint16_t pma_addr1 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
|
||||
@ -567,13 +561,13 @@ void edpt0_open(uint8_t rhport) {
|
||||
ep_write(0, ep_reg, false);
|
||||
}
|
||||
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
|
||||
bool dcd_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *desc_ep) {
|
||||
(void)rhport;
|
||||
uint8_t const ep_addr = desc_ep->bEndpointAddress;
|
||||
uint8_t const ep_num = tu_edpt_number(ep_addr);
|
||||
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
|
||||
const uint16_t packet_size = tu_edpt_packet_size(desc_ep);
|
||||
uint8_t const ep_idx = dcd_ep_alloc(ep_addr, desc_ep->bmAttributes.xfer);
|
||||
const uint8_t ep_addr = desc_ep->bEndpointAddress;
|
||||
const uint8_t ep_num = tu_edpt_number(ep_addr);
|
||||
const tusb_dir_t dir = tu_edpt_dir(ep_addr);
|
||||
const uint16_t packet_size = tu_edpt_packet_size(desc_ep);
|
||||
const uint8_t ep_idx = dcd_ep_alloc(ep_addr, desc_ep->bmAttributes.xfer);
|
||||
TU_ASSERT(ep_idx < FSDEV_EP_COUNT);
|
||||
|
||||
uint32_t ep_reg = ep_read(ep_idx) & ~USB_EPREG_MASK;
|
||||
@ -597,9 +591,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
|
||||
uint16_t pma_addr = dcd_pma_alloc(packet_size, false);
|
||||
btable_set_addr(ep_idx, dir == TUSB_DIR_IN ? BTABLE_BUF_TX : BTABLE_BUF_RX, pma_addr);
|
||||
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
xfer->max_packet_size = packet_size;
|
||||
xfer->ep_idx = ep_idx;
|
||||
xfer->ep_idx = ep_idx;
|
||||
|
||||
ep_change_status(&ep_reg, dir, EP_STAT_NAK);
|
||||
ep_change_dtog(&ep_reg, dir, 0);
|
||||
@ -623,8 +617,8 @@ void dcd_edpt_close_all(uint8_t rhport) {
|
||||
// Reset endpoint
|
||||
ep_write(i, 0, false);
|
||||
// Clear EP allocation status
|
||||
ep_alloc_status[i].ep_num = 0xFF;
|
||||
ep_alloc_status[i].ep_type = 0xFF;
|
||||
ep_alloc_status[i].ep_num = 0xFF;
|
||||
ep_alloc_status[i].ep_type = 0xFF;
|
||||
ep_alloc_status[i].allocated[0] = false;
|
||||
ep_alloc_status[i].allocated[1] = false;
|
||||
}
|
||||
@ -638,46 +632,46 @@ void dcd_edpt_close_all(uint8_t rhport) {
|
||||
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
|
||||
(void)rhport;
|
||||
|
||||
uint8_t const ep_num = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
|
||||
const uint8_t ep_num = tu_edpt_number(ep_addr);
|
||||
const uint8_t dir = tu_edpt_dir(ep_addr);
|
||||
const uint8_t ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
|
||||
|
||||
#if CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP != 0
|
||||
uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, true);
|
||||
#if CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP != 0
|
||||
uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, true);
|
||||
uint16_t pma_addr2 = pma_addr >> 16;
|
||||
#else
|
||||
uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, false);
|
||||
#else
|
||||
uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, false);
|
||||
uint16_t pma_addr2 = pma_addr;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
btable_set_addr(ep_idx, 0, pma_addr);
|
||||
btable_set_addr(ep_idx, 1, pma_addr2);
|
||||
#else
|
||||
#else
|
||||
btable_set_addr(ep_idx, dir == TUSB_DIR_IN ? BTABLE_BUF_TX : BTABLE_BUF_RX, pma_addr);
|
||||
(void) pma_addr2;
|
||||
#endif
|
||||
(void)pma_addr2;
|
||||
#endif
|
||||
|
||||
xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
xfer->ep_idx = ep_idx;
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
xfer->ep_idx = ep_idx;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
|
||||
bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *desc_ep) {
|
||||
(void)rhport;
|
||||
uint8_t const ep_addr = desc_ep->bEndpointAddress;
|
||||
uint8_t const ep_num = tu_edpt_number(ep_addr);
|
||||
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
const uint8_t ep_addr = desc_ep->bEndpointAddress;
|
||||
const uint8_t ep_num = tu_edpt_number(ep_addr);
|
||||
const tusb_dir_t dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
|
||||
uint8_t const ep_idx = xfer->ep_idx;
|
||||
const uint8_t ep_idx = xfer->ep_idx;
|
||||
|
||||
xfer->max_packet_size = tu_edpt_packet_size(desc_ep);
|
||||
|
||||
uint32_t ep_reg = ep_read(ep_idx) & ~USB_EPREG_MASK;
|
||||
ep_reg |= tu_edpt_number(ep_addr) | USB_EP_ISOCHRONOUS | USB_EP_CTR_TX | USB_EP_CTR_RX;
|
||||
#if FSDEV_USE_SBUF_ISO != 0
|
||||
#if FSDEV_USE_SBUF_ISO != 0
|
||||
ep_reg |= USB_EP_KIND;
|
||||
|
||||
ep_change_status(&ep_reg, dir, EP_STAT_DISABLED);
|
||||
@ -688,12 +682,12 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep)
|
||||
} else {
|
||||
ep_reg &= ~(USB_EPTX_STAT | USB_EP_DTOG_TX);
|
||||
}
|
||||
#else
|
||||
#else
|
||||
ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_DISABLED);
|
||||
ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_DISABLED);
|
||||
ep_change_dtog(&ep_reg, dir, 0);
|
||||
ep_change_dtog(&ep_reg, (tusb_dir_t)(1 - dir), 1);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
ep_write(ep_idx, ep_reg, true);
|
||||
|
||||
@ -702,17 +696,17 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep)
|
||||
|
||||
// Currently, single-buffered, and only 64 bytes at a time (max)
|
||||
static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
|
||||
uint16_t len = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
|
||||
uint16_t len = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
|
||||
uint32_t ep_reg = ep_read(ep_ix) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR
|
||||
|
||||
bool const is_iso = ep_is_iso(ep_reg);
|
||||
const bool is_iso = ep_is_iso(ep_reg);
|
||||
|
||||
uint8_t buf_id;
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
bool const dbl_buf = is_iso;
|
||||
#else
|
||||
#else
|
||||
bool const dbl_buf = false;
|
||||
#endif
|
||||
#endif
|
||||
if (dbl_buf) {
|
||||
buf_id = (ep_reg & USB_EP_DTOG_TX) ? 1 : 0;
|
||||
} else {
|
||||
@ -739,9 +733,9 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
|
||||
}
|
||||
|
||||
static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir) {
|
||||
(void) rhport;
|
||||
(void)rhport;
|
||||
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
const uint8_t ep_idx = xfer->ep_idx;
|
||||
|
||||
if (dir == TUSB_DIR_IN) {
|
||||
@ -752,11 +746,11 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir) {
|
||||
|
||||
uint16_t cnt = tu_min16(xfer->total_len, xfer->max_packet_size);
|
||||
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
#if FSDEV_USE_SBUF_ISO == 0
|
||||
bool const dbl_buf = ep_is_iso(ep_reg);
|
||||
#else
|
||||
#else
|
||||
bool const dbl_buf = false;
|
||||
#endif
|
||||
#endif
|
||||
if (dbl_buf) {
|
||||
btable_set_rx_bufsize(ep_idx, 0, cnt);
|
||||
btable_set_rx_bufsize(ep_idx, 1, cnt);
|
||||
@ -771,29 +765,29 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, bool is_isr) {
|
||||
(void) is_isr;
|
||||
uint8_t const ep_num = tu_edpt_number(ep_addr);
|
||||
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes, bool is_isr) {
|
||||
(void)is_isr;
|
||||
const uint8_t ep_num = tu_edpt_number(ep_addr);
|
||||
const tusb_dir_t dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
|
||||
xfer->buffer = buffer;
|
||||
xfer->ff = NULL;
|
||||
xfer->total_len = total_bytes;
|
||||
xfer->buffer = buffer;
|
||||
xfer->ff = NULL;
|
||||
xfer->total_len = total_bytes;
|
||||
xfer->queued_len = 0;
|
||||
|
||||
return edpt_xfer(rhport, ep_num, dir);
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes, bool is_isr) {
|
||||
(void) is_isr;
|
||||
uint8_t const ep_num = tu_edpt_number(ep_addr);
|
||||
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes, bool is_isr) {
|
||||
(void)is_isr;
|
||||
const uint8_t ep_num = tu_edpt_number(ep_addr);
|
||||
const tusb_dir_t dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
|
||||
xfer->buffer = NULL;
|
||||
xfer->ff = ff;
|
||||
xfer->total_len = total_bytes;
|
||||
xfer->buffer = NULL;
|
||||
xfer->ff = ff;
|
||||
xfer->total_len = total_bytes;
|
||||
xfer->queued_len = 0;
|
||||
|
||||
return edpt_xfer(rhport, ep_num, dir);
|
||||
@ -801,10 +795,10 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
|
||||
|
||||
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
|
||||
(void)rhport;
|
||||
uint8_t const ep_num = tu_edpt_number(ep_addr);
|
||||
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
uint8_t const ep_idx = xfer->ep_idx;
|
||||
const uint8_t ep_num = tu_edpt_number(ep_addr);
|
||||
const tusb_dir_t dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
const uint8_t ep_idx = xfer->ep_idx;
|
||||
|
||||
uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR bits
|
||||
ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir);
|
||||
@ -816,10 +810,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
|
||||
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
|
||||
(void)rhport;
|
||||
|
||||
uint8_t const ep_num = tu_edpt_number(ep_addr);
|
||||
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
uint8_t const ep_idx = xfer->ep_idx;
|
||||
const uint8_t ep_num = tu_edpt_number(ep_addr);
|
||||
const tusb_dir_t dir = tu_edpt_dir(ep_addr);
|
||||
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
|
||||
const uint8_t ep_idx = xfer->ep_idx;
|
||||
|
||||
uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR bits
|
||||
ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir) | EP_DTOG_MASK(dir);
|
||||
@ -839,7 +833,7 @@ void dcd_int_disable(uint8_t rhport) {
|
||||
fsdev_int_disable(rhport);
|
||||
}
|
||||
|
||||
#if defined(USB_BCDR_DPPU) || defined(SYSCFG_PMC_USB_PU)
|
||||
#if defined(USB_BCDR_DPPU) || defined(SYSCFG_PMC_USB_PU)
|
||||
void dcd_connect(uint8_t rhport) {
|
||||
fsdev_connect(rhport);
|
||||
}
|
||||
@ -847,6 +841,6 @@ void dcd_connect(uint8_t rhport) {
|
||||
void dcd_disconnect(uint8_t rhport) {
|
||||
fsdev_disconnect(rhport);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -32,11 +32,11 @@
|
||||
#include "common/tusb_common.h"
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
#include "device/dcd.h"
|
||||
#include "device/dcd.h"
|
||||
#endif
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
#include "host/hcd.h"
|
||||
#include "host/hcd.h"
|
||||
#endif
|
||||
|
||||
#if defined(TUP_USBIP_FSDEV_STM32)
|
||||
@ -56,41 +56,37 @@ extern "C" {
|
||||
// If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
|
||||
// Both of these MUST be a multiple of 2, and are in byte units.
|
||||
#ifndef FSDEV_BTABLE_BASE
|
||||
#define FSDEV_BTABLE_BASE 0U
|
||||
#define FSDEV_BTABLE_BASE 0U
|
||||
#endif
|
||||
|
||||
TU_VERIFY_STATIC(FSDEV_BTABLE_BASE % 8 == 0, "BTABLE base must be aligned to 8 bytes");
|
||||
|
||||
// FSDEV_PMA_SIZE is PMA buffer size in bytes.
|
||||
// CFG_TUSB_FSDEV_PMA_SIZE is PMA buffer size in bytes.
|
||||
// - 512-byte devices, access with a stride of two words (use every other 16-bit address)
|
||||
// - 1024-byte devices, access with a stride of one word (use every 16-bit address)
|
||||
// - 2048-byte devices, access with 32-bit address
|
||||
|
||||
// For purposes of accessing the packet
|
||||
#if FSDEV_PMA_SIZE == 512
|
||||
#if CFG_TUSB_FSDEV_PMA_SIZE == 512
|
||||
// 1x16 bit / word access scheme
|
||||
#define FSDEV_PMA_STRIDE 2
|
||||
#define pma_access_scheme TU_ATTR_ALIGNED(4)
|
||||
#elif FSDEV_PMA_SIZE == 1024
|
||||
#elif CFG_TUSB_FSDEV_PMA_SIZE == 1024
|
||||
// 2x16 bit / word access scheme
|
||||
#define FSDEV_PMA_STRIDE 1
|
||||
#define FSDEV_PMA_STRIDE 1
|
||||
#define pma_access_scheme
|
||||
#elif FSDEV_PMA_SIZE == 2048
|
||||
#elif CFG_TUSB_FSDEV_PMA_SIZE == 2048
|
||||
// 32 bit access scheme
|
||||
#define FSDEV_BUS_32BIT
|
||||
#define FSDEV_PMA_STRIDE 1
|
||||
#define FSDEV_PMA_STRIDE 1
|
||||
#define pma_access_scheme
|
||||
#endif
|
||||
|
||||
// The fsdev_bus_t type can be used for both register and PMA access necessities
|
||||
#ifdef FSDEV_BUS_32BIT
|
||||
typedef uint32_t fsdev_bus_t;
|
||||
#define fsdevbus_unaligned_read(_addr) tu_unaligned_read32(_addr)
|
||||
#define fsdevbus_unaligned_write(_addr, _value) tu_unaligned_write32(_addr, _value)
|
||||
typedef uint32_t fsdev_bus_t;
|
||||
#else
|
||||
typedef uint16_t fsdev_bus_t;
|
||||
#define fsdevbus_unaligned_read(_addr) tu_unaligned_read16(_addr)
|
||||
#define fsdevbus_unaligned_write(_addr, _value) tu_unaligned_write16(_addr, _value)
|
||||
typedef uint16_t fsdev_bus_t;
|
||||
#endif
|
||||
|
||||
enum {
|
||||
@ -124,77 +120,77 @@ typedef union {
|
||||
} ep32[FSDEV_EP_COUNT][2];
|
||||
} fsdev_btable_t;
|
||||
|
||||
TU_VERIFY_STATIC(sizeof(fsdev_btable_t) == FSDEV_EP_COUNT*8*FSDEV_PMA_STRIDE, "size is not correct");
|
||||
TU_VERIFY_STATIC(FSDEV_BTABLE_BASE + FSDEV_EP_COUNT*8 <= FSDEV_PMA_SIZE, "BTABLE does not fit in PMA RAM");
|
||||
TU_VERIFY_STATIC(sizeof(fsdev_btable_t) == FSDEV_EP_COUNT * 8 * FSDEV_PMA_STRIDE, "size is not correct");
|
||||
TU_VERIFY_STATIC(FSDEV_BTABLE_BASE + FSDEV_EP_COUNT * 8 <= CFG_TUSB_FSDEV_PMA_SIZE, "BTABLE does not fit in PMA RAM");
|
||||
|
||||
#define FSDEV_BTABLE ((volatile fsdev_btable_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(FSDEV_BTABLE_BASE)))
|
||||
#define FSDEV_BTABLE ((volatile fsdev_btable_t *)(FSDEV_PMA_BASE + FSDEV_PMA_STRIDE * (FSDEV_BTABLE_BASE)))
|
||||
|
||||
typedef struct {
|
||||
volatile pma_access_scheme fsdev_bus_t value;
|
||||
} fsdev_pma_buf_t;
|
||||
|
||||
#define PMA_BUF_AT(_addr) ((fsdev_pma_buf_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(_addr)))
|
||||
#define PMA_BUF_AT(_addr) ((fsdev_pma_buf_t *)(FSDEV_PMA_BASE + FSDEV_PMA_STRIDE * (_addr)))
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Registers Typedef
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// volatile 32-bit aligned
|
||||
#define _va32 volatile TU_ATTR_ALIGNED(4)
|
||||
#define _va32 volatile TU_ATTR_ALIGNED(4)
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
_va32 fsdev_bus_t reg;
|
||||
}ep[FSDEV_EP_COUNT];
|
||||
} ep[FSDEV_EP_COUNT];
|
||||
|
||||
_va32 uint32_t RESERVED7[8]; // Reserved
|
||||
_va32 fsdev_bus_t CNTR; // 40: Control register
|
||||
_va32 fsdev_bus_t ISTR; // 44: Interrupt status register
|
||||
_va32 fsdev_bus_t FNR; // 48: Frame number register
|
||||
_va32 fsdev_bus_t DADDR; // 4C: Device address register
|
||||
_va32 fsdev_bus_t BTABLE; // 50: Buffer Table address register (16-bit only)
|
||||
_va32 fsdev_bus_t LPMCSR; // 54: LPM Control and Status Register (32-bit only)
|
||||
_va32 fsdev_bus_t BCDR; // 58: Battery Charging Detector Register (32-bit only)
|
||||
_va32 uint32_t RESERVED7[8]; // Reserved
|
||||
_va32 fsdev_bus_t CNTR; // 40: Control register
|
||||
_va32 fsdev_bus_t ISTR; // 44: Interrupt status register
|
||||
_va32 fsdev_bus_t FNR; // 48: Frame number register
|
||||
_va32 fsdev_bus_t DADDR; // 4C: Device address register
|
||||
_va32 fsdev_bus_t BTABLE; // 50: Buffer Table address register (16-bit only)
|
||||
_va32 fsdev_bus_t LPMCSR; // 54: LPM Control and Status Register (32-bit only)
|
||||
_va32 fsdev_bus_t BCDR; // 58: Battery Charging Detector Register (32-bit only)
|
||||
} fsdev_regs_t;
|
||||
|
||||
TU_VERIFY_STATIC(offsetof(fsdev_regs_t, CNTR) == 0x40, "Wrong offset");
|
||||
TU_VERIFY_STATIC(sizeof(fsdev_regs_t) == 0x5C, "Size is not correct");
|
||||
|
||||
#define FSDEV_REG ((fsdev_regs_t*) FSDEV_REG_BASE)
|
||||
#define FSDEV_REG ((fsdev_regs_t *)FSDEV_REG_BASE)
|
||||
|
||||
|
||||
#ifndef USB_EPTX_STAT
|
||||
#define USB_EPTX_STAT 0x0030U
|
||||
#define USB_EPTX_STAT 0x0030U
|
||||
#endif
|
||||
|
||||
#ifndef USB_EPRX_STAT
|
||||
#define USB_EPRX_STAT 0x3000U
|
||||
#define USB_EPRX_STAT 0x3000U
|
||||
#endif
|
||||
|
||||
#ifndef USB_EPTX_STAT_Pos
|
||||
#define USB_EPTX_STAT_Pos 4u
|
||||
#define USB_EPTX_STAT_Pos 4u
|
||||
#endif
|
||||
|
||||
#ifndef USB_EP_DTOG_TX_Pos
|
||||
#define USB_EP_DTOG_TX_Pos 6u
|
||||
#define USB_EP_DTOG_TX_Pos 6u
|
||||
#endif
|
||||
|
||||
#ifndef USB_EP_CTR_TX_Pos
|
||||
#define USB_EP_CTR_TX_Pos 7u
|
||||
#define USB_EP_CTR_TX_Pos 7u
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
EP_STAT_DISABLED = 0,
|
||||
EP_STAT_STALL = 1,
|
||||
EP_STAT_NAK = 2,
|
||||
EP_STAT_VALID = 3
|
||||
}ep_stat_t;
|
||||
EP_STAT_STALL = 1,
|
||||
EP_STAT_NAK = 2,
|
||||
EP_STAT_VALID = 3
|
||||
} ep_stat_t;
|
||||
|
||||
#define EP_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
|
||||
#define EP_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
|
||||
#define EP_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
|
||||
#define EP_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
|
||||
|
||||
#define CH_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 8 : 0)))
|
||||
#define CH_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 8 : 0)))
|
||||
#define CH_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 8 : 0)))
|
||||
#define CH_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 8 : 0)))
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoint Helper
|
||||
@ -211,7 +207,7 @@ TU_ATTR_ALWAYS_INLINE static inline void ep_write(uint32_t ep_id, uint32_t value
|
||||
fsdev_int_disable(0);
|
||||
}
|
||||
|
||||
FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
|
||||
FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t)value;
|
||||
|
||||
if (need_exclusive) {
|
||||
fsdev_int_enable(0);
|
||||
@ -226,11 +222,11 @@ TU_ATTR_ALWAYS_INLINE static inline void ep_write_clear_ctr(uint32_t ep_id, tusb
|
||||
ep_write(ep_id, reg, false);
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ep_change_status(uint32_t* reg, tusb_dir_t dir, ep_stat_t state) {
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ep_change_status(uint32_t *reg, tusb_dir_t dir, ep_stat_t state) {
|
||||
*reg ^= (state << (USB_EPTX_STAT_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ep_change_dtog(uint32_t* reg, tusb_dir_t dir, uint8_t state) {
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ep_change_dtog(uint32_t *reg, tusb_dir_t dir, uint8_t state) {
|
||||
*reg ^= (state << (USB_EP_DTOG_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
|
||||
}
|
||||
|
||||
@ -259,11 +255,11 @@ TU_ATTR_ALWAYS_INLINE static inline void ch_write_clear_ctr(uint32_t ch_id, tusb
|
||||
ep_write(ch_id, reg, false);
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ch_change_status(uint32_t* reg, tusb_dir_t dir, ep_stat_t state) {
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ch_change_status(uint32_t *reg, tusb_dir_t dir, ep_stat_t state) {
|
||||
*reg ^= (state << (USB_EPTX_STAT_Pos + (dir == TUSB_DIR_IN ? 8 : 0)));
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ch_change_dtog(uint32_t* reg, tusb_dir_t dir, uint8_t state) {
|
||||
TU_ATTR_ALWAYS_INLINE static inline void ch_change_dtog(uint32_t *reg, tusb_dir_t dir, uint8_t state) {
|
||||
*reg ^= (state << (USB_EP_DTOG_TX_Pos + (dir == TUSB_DIR_IN ? 8 : 0)));
|
||||
}
|
||||
|
||||
@ -281,8 +277,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t btable_get_addr(uint32_t ep_id, uin
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void btable_set_addr(uint32_t ep_id, uint8_t buf_id, uint16_t addr) {
|
||||
#ifdef FSDEV_BUS_32BIT
|
||||
uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
|
||||
count_addr = (count_addr & 0xFFFF0000u) | (addr & 0x0000FFFCu);
|
||||
uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
|
||||
count_addr = (count_addr & 0xFFFF0000u) | (addr & 0x0000FFFCu);
|
||||
FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
|
||||
#else
|
||||
FSDEV_BTABLE->ep16[ep_id][buf_id].addr = addr;
|
||||
@ -301,12 +297,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t btable_get_count(uint32_t ep_id, ui
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void btable_set_count(uint32_t ep_id, uint8_t buf_id, uint16_t byte_count) {
|
||||
#ifdef FSDEV_BUS_32BIT
|
||||
uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
|
||||
count_addr = (count_addr & ~0x03FF0000u) | ((byte_count & 0x3FFu) << 16);
|
||||
uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
|
||||
count_addr = (count_addr & ~0x03FF0000u) | ((byte_count & 0x3FFu) << 16);
|
||||
FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
|
||||
#else
|
||||
uint16_t cnt = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
|
||||
cnt = (cnt & ~0x3FFU) | (byte_count & 0x3FFU);
|
||||
uint16_t cnt = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
|
||||
cnt = (cnt & ~0x3FFU) | (byte_count & 0x3FFU);
|
||||
FSDEV_BTABLE->ep16[ep_id][buf_id].count = cnt;
|
||||
#endif
|
||||
}
|
||||
@ -318,7 +314,7 @@ void fsdev_core_reset(void);
|
||||
void fsdev_deinit(void);
|
||||
|
||||
// Aligned buffer size according to hardware
|
||||
uint16_t pma_align_buffer_size(uint16_t size, uint8_t* blsize, uint8_t* num_block);
|
||||
uint16_t pma_align_buffer_size(uint16_t size, uint8_t *blsize, uint8_t *num_block);
|
||||
|
||||
// Set RX buffer size
|
||||
void btable_set_rx_bufsize(uint32_t ep_id, uint8_t buf_id, uint16_t wCount);
|
||||
|
||||
@ -281,7 +281,7 @@
|
||||
// - Enable double buffering on devices with >1KB Packet Memory Area (PMA)
|
||||
// to improve isochronous transfer reliability and performance
|
||||
// - Disable on devices with limited PMA to conserve memory space
|
||||
#if FSDEV_PMA_SIZE > 1024u
|
||||
#if CFG_TUSB_FSDEV_PMA_SIZE > 1024u
|
||||
#define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 1
|
||||
#else
|
||||
#define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 0
|
||||
|
||||
@ -741,7 +741,7 @@ static uint32_t hcd_pma_alloc(uint8_t channel, tusb_dir_t dir, uint16_t len) {
|
||||
uint16_t addr = FSDEV_BTABLE_BASE + 8 * FSDEV_EP_COUNT;
|
||||
addr += channel * TUSB_EPSIZE_BULK_FS * 2 + (dir == TUSB_DIR_IN ? TUSB_EPSIZE_BULK_FS : 0);
|
||||
|
||||
TU_ASSERT(addr <= FSDEV_PMA_SIZE, 0xFFFF);
|
||||
TU_ASSERT(addr <= CFG_TUSB_FSDEV_PMA_SIZE, 0xFFFF);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
@ -856,8 +856,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
|
||||
hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
|
||||
|
||||
if (byte_count > 0) {
|
||||
const tu_hwfifo_access_t access_mode = {.data_stride = CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE};
|
||||
tu_hwfifo_read(dwc2->fifo[0], edpt->buffer + xfer->xferred_bytes, byte_count, &access_mode);
|
||||
tu_hwfifo_read(dwc2->fifo[0], edpt->buffer + xfer->xferred_bytes, byte_count, NULL);
|
||||
xfer->xferred_bytes += byte_count;
|
||||
xfer->fifo_bytes = byte_count;
|
||||
}
|
||||
@ -908,8 +907,7 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) {
|
||||
return true;
|
||||
}
|
||||
|
||||
const tu_hwfifo_access_t access_mode = {.data_stride = CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE};
|
||||
tu_hwfifo_write(dwc2->fifo[ch_id], edpt->buffer + xfer->fifo_bytes, xact_bytes, &access_mode);
|
||||
tu_hwfifo_write(dwc2->fifo[ch_id], edpt->buffer + xfer->fifo_bytes, xact_bytes, NULL);
|
||||
xfer->fifo_bytes += xact_bytes;
|
||||
}
|
||||
}
|
||||
|
||||
@ -351,13 +351,13 @@
|
||||
#if defined(TUP_USBIP_FSDEV)
|
||||
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
|
||||
|
||||
#if FSDEV_PMA_SIZE == 512
|
||||
#if CFG_TUSB_FSDEV_PMA_SIZE == 512
|
||||
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 2 // 16-bit data
|
||||
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 4 // 32-bit address increase
|
||||
#elif FSDEV_PMA_SIZE == 1024
|
||||
#elif CFG_TUSB_FSDEV_PMA_SIZE == 1024
|
||||
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 2 // 16-bit data
|
||||
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 2 // 16-bit address increase
|
||||
#elif FSDEV_PMA_SIZE == 2048
|
||||
#elif CFG_TUSB_FSDEV_PMA_SIZE == 2048
|
||||
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 4 // 32-bit data
|
||||
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 4 // 32-bit address increase
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user