add hs_phy_type parameter to dwc2_phy_deinit for selective PHY deinitialization across all MCUs

src/portable/synopsys/dwc2/dwc2_at32.h

@@ -113,7 +113,8 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_
 }
 
 // MCU specific PHY deinit, disable PHY power
-TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t *dwc2) {
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void) hs_phy_type;
   dwc2->stm32_gccfg &= ~(STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN);
 }
 

src/portable/synopsys/dwc2/dwc2_bcm.h

@@ -74,8 +74,9 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 }
 
 // MCU specific PHY deinit, disable PHY power
-static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2) {
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
   (void) dwc2;
+  (void) hs_phy_type;
   // nothing to do
 }
 

src/portable/synopsys/dwc2/dwc2_common.c

@@ -256,7 +256,9 @@ void dwc2_core_deinit(uint8_t rhport) {
   dwc2->pcgcctl |= PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK;
 
   // MCU-specific PHY deinit (disable PHY power)
-  dwc2_phy_deinit(dwc2);
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+  const uint8_t hs_phy_type = (dwc2->gusbcfg & GUSBCFG_PHYSEL) ? GHWCFG2_HSPHY_NOT_SUPPORTED : ghwcfg2.hs_phy_type;
+  dwc2_phy_deinit(dwc2, hs_phy_type);
 }
 
 // void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) {

src/portable/synopsys/dwc2/dwc2_common.h

@@ -42,7 +42,7 @@
 // - _dwc2_controller[]: array of controllers
 // - DWC2_EP_MAX: largest EP counts of all controllers
 // - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
-// - dwc2_phy_deinit: phy deinit to disable PHY power
+// - dwc2_phy_deinit(dwc2, hs_phy_type): phy deinit to disable PHY power, only deinit the phy used by core
 // - dwc2_dcd_int_enable/dwc2_dcd_int_disable
 // - dwc2_remote_wakeup_delay
 

src/portable/synopsys/dwc2/dwc2_efm32.h

@@ -73,9 +73,9 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 }
 
 // MCU specific PHY deinit, disable PHY power
-static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2) {
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
   (void) dwc2;
-
+  (void) hs_phy_type;
   // Disable PHY pin
   USB->ROUTE = 0;
 }

src/portable/synopsys/dwc2/dwc2_esp32.h

@@ -122,8 +122,9 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
 }
 
 // MCU specific PHY deinit, disable PHY power
-TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2) {
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   (void)dwc2;
+  (void)hs_phy_type;
   // PHY managed by ESP-IDF
 }
 

src/portable/synopsys/dwc2/dwc2_gd32.h

@@ -86,8 +86,9 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 }
 
 // MCU specific PHY deinit, disable PHY power
-static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2) {
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
   (void) dwc2;
+  (void) hs_phy_type;
   // nothing to do
 }
 

src/portable/synopsys/dwc2/dwc2_nrf.h

@@ -53,8 +53,9 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
 }
 
 // MCU specific PHY deinit, disable PHY power
-TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2) {
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   (void)dwc2;
+  (void)hs_phy_type;
 }
 
 // MCU specific PHY update, it is called AFTER init() and core reset

src/portable/synopsys/dwc2/dwc2_stm32.h

@@ -265,17 +265,19 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
 }
 
 // MCU specific PHY deinit, disable PHY power
-static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2) {
-  // Disable on-chip FS PHY
-  dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
-
-  // Disable HS PHY if present
-  #ifdef USB_HS_PHYC
-  dwc2->stm32_gccfg &= ~STM32_GCCFG_PHYHSEN;
-  // Disable PLL and LDO
-  USB_HS_PHYC->USB_HS_PHYC_PLL &= ~USB_HS_PHYC_PLL_PLLEN;
-  USB_HS_PHYC->USB_HS_PHYC_LDO &= ~USB_HS_PHYC_LDO_ENABLE;
-  #endif
+static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
+    // Disable on-chip FS PHY
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+  } else {
+    // Disable HS PHY
+    #ifdef USB_HS_PHYC
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PHYHSEN;
+    // Disable PLL and LDO
+    USB_HS_PHYC->USB_HS_PHYC_PLL &= ~USB_HS_PHYC_PLL_PLLEN;
+    USB_HS_PHYC->USB_HS_PHYC_LDO &= ~USB_HS_PHYC_LDO_ENABLE;
+    #endif
+  }
 }
 
 // MCU specific PHY update, it is called AFTER init() and core reset

src/portable/synopsys/dwc2/dwc2_xmc.h

@@ -72,9 +72,9 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 }
 
 // MCU specific PHY deinit, disable PHY power
-static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2) {
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
   (void) dwc2;
-
+  (void) hs_phy_type;
   // nothing to do
 }