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enable dedicated hwfifo for rp2

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hathach
2026-01-09 18:40:55 +07:00
parent 085ec06874
commit 4c86cbdc82
6 changed files with 169 additions and 90 deletions
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76
src/common/tusb_fifo.c
View File

@ -33,7 +33,7 @@
// Suppress IAR warning
// Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
#if defined(__ICCARM__)
#pragma diag_suppress = Pa082
#pragma diag_suppress = Pa082
#endif
#if OSAL_MUTEX_REQUIRED
@ -110,8 +110,9 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
}
//--------------------------------------------------------------------+
// Pull & Push
// copy data to/from fifo without updating read/write pointers
// Hardware FIFO API
// Support different data access width and address increment scheme
// Can support multiple i.e both 16 and 32-bit data access if needed
//--------------------------------------------------------------------+
#if CFG_TUSB_FIFO_HWFIFO_API
#if CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE
@ -122,18 +123,31 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
#define HWFIFO_ADDR_NEXT(_hwfifo, _const) HWFIFO_ADDR_NEXT_N(_hwfifo, _const, CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE)
//------------- Write -------------//
#ifndef CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE
static inline void stride_write(volatile void *hwfifo, const void *src, uint8_t data_stride) {
TU_ATTR_ALWAYS_INLINE static inline void stride_write(volatile void *hwfifo, const void *src, uint8_t data_stride) {
(void)data_stride; // possible unused
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 4
if (data_stride == 4) {
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 4
if (data_stride == 4)
#endif
{
*((volatile uint32_t *)hwfifo) = tu_unaligned_read32(src);
}
#endif
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 2
if (data_stride == 2) {
#endif
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 2
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 2
if (data_stride == 2)
#endif
{
*((volatile uint16_t *)hwfifo) = tu_unaligned_read16(src);
}
#endif
#endif
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
*((volatile uint8_t *)hwfifo) = *(const uint8_t *)src;
#endif
}
// Copy from fifo to fixed address buffer (usually a tx register) with TU_FIFO_FIXED_ADDR_RW32 mode
@ -147,7 +161,8 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
HWFIFO_ADDR_NEXT(hwfifo, );
}
#ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE > 1
#ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
// 16-bit access is allowed for odd bytes
if (len >= 2) {
*((volatile uint16_t *)hwfifo) = tu_unaligned_read16(src);
@ -155,16 +170,16 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
len -= 2;
HWFIFO_ADDR_NEXT_N(hwfifo, , 2);
}
#endif
#endif
#ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS
#ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS
// 8-bit access is allowed for odd bytes
while (len > 0) {
*((volatile uint8_t *)hwfifo) = *src++;
len--;
HWFIFO_ADDR_NEXT_N(hwfifo, , 1);
}
#else
#else
// Write odd bytes i.e 1 byte for 16 bit or 1-3 bytes for 32 bit
if (len > 0) {
@ -173,13 +188,16 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
stride_write(hwfifo, &tmp, data_stride);
HWFIFO_ADDR_NEXT(hwfifo, );
}
#endif
#endif
}
#endif
//------------- Read -------------//
#ifndef CFG_TUSB_FIFO_HWFIFO_CUSTOM_READ
static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t data_stride) {
TU_ATTR_ALWAYS_INLINE static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t data_stride) {
(void)data_stride; // possible unused
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 4
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 4
if (data_stride == 4)
@ -197,6 +215,10 @@ static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t
tu_unaligned_write16(dest, *((const volatile uint16_t *)hwfifo));
}
#endif
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
*(uint8_t *)dest = *((const volatile uint8_t *)hwfifo);
#endif
}
void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, const tu_hwfifo_access_t *access_mode) {
@ -209,7 +231,8 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co
HWFIFO_ADDR_NEXT(hwfifo, const);
}
#ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE > 1
#ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
// 16-bit access is allowed for odd bytes
if (len >= 2) {
tu_unaligned_write16(dest, *((const volatile uint16_t *)hwfifo));
@ -235,6 +258,7 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co
HWFIFO_ADDR_NEXT(hwfifo, const);
}
#endif
#endif
}
#endif
@ -251,7 +275,11 @@ static void hwff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uin
tu_hwfifo_read(hwfifo, ff_buf, n, access_mode);
} else {
// Wrap around case
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
tu_hwfifo_read(hwfifo, ff_buf, lin_bytes, access_mode); // linear part
HWFIFO_ADDR_NEXT_N(hwfifo, const, lin_bytes);
tu_hwfifo_read(hwfifo, f->buffer, wrap_bytes, access_mode); // wrapped part
#else
// Write full words to linear part of buffer
const uint8_t data_stride = access_mode->data_stride;
const uint32_t odd_mask = data_stride - 1;
@ -286,6 +314,7 @@ static void hwff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uin
if (wrap_bytes > 0) {
tu_hwfifo_read(hwfifo, ff_buf, wrap_bytes, access_mode);
}
#endif
}
}
@ -303,11 +332,15 @@ static void hwff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t
tu_hwfifo_write(hwfifo, ff_buf, n, access_mode);
} else {
// Wrap around case
#if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
tu_hwfifo_write(hwfifo, ff_buf, lin_bytes, access_mode); // linear part
HWFIFO_ADDR_NEXT_N(hwfifo, , lin_bytes);
tu_hwfifo_write(hwfifo, f->buffer, wrap_bytes, access_mode); // wrapped part
#else
// Read full words from linear part
const uint8_t data_stride = access_mode->data_stride;
const uint32_t odd_mask = data_stride - 1;
uint16_t lin_even = lin_bytes & ~odd_mask;
uint16_t lin_even = lin_bytes & ~odd_mask;
tu_hwfifo_write(hwfifo, ff_buf, lin_even, access_mode);
HWFIFO_ADDR_NEXT_N(hwfifo, , lin_even);
ff_buf += lin_even;
@ -338,10 +371,15 @@ static void hwff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t
if (wrap_bytes > 0) {
tu_hwfifo_write(hwfifo, ff_buf, wrap_bytes, access_mode);
}
#endif
}
}
#endif
//--------------------------------------------------------------------+
// Pull & Push
// copy data to/from fifo without updating read/write pointers
//--------------------------------------------------------------------+
// send n items to fifo WITHOUT updating write pointer
static void ff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uint16_t wr_ptr) {
uint16_t lin_bytes = f->depth - wr_ptr;
@ -787,6 +825,6 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) {
} else {
info->linear.len = f->depth - wr_ptr;
info->wrapped.len = remain - info->linear.len; // Remaining length - n already was limited to remain or FIFO depth
info->wrapped.ptr = f->buffer; // Always start of buffer
info->wrapped.ptr = f->buffer; // Always start of buffer
}
}

10
src/portable/raspberrypi/rp2040/dcd_rp2040.c
View File

@ -502,7 +502,15 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
(void)rhport;
(void)is_isr;
hw_endpoint_t *ep = hw_endpoint_get_by_addr(ep_addr);
hw_endpoint_xfer_start(ep, buffer, total_bytes);
hw_endpoint_xfer_start(ep, buffer, NULL, total_bytes);
return true;
}
bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes, bool is_isr) {
(void)rhport;
(void)is_isr;
hw_endpoint_t *ep = hw_endpoint_get_by_addr(ep_addr);
hw_endpoint_xfer_start(ep, NULL, ff, total_bytes);
return true;
}

4
src/portable/raspberrypi/rp2040/hcd_rp2040.c
View File

@ -511,7 +511,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
// sie ctrl registers. Otherwise, interrupt ep registers should
// already be configured
if (ep == &epx) {
hw_endpoint_xfer_start(ep, buffer, buflen);
hw_endpoint_xfer_start(ep, buffer, NULL, buflen);
// That has set up buffer control, endpoint control etc
// for host we have to initiate the transfer
@ -527,7 +527,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
busy_wait_at_least_cycles(12);
usb_hw->sie_ctrl = flags;
} else {
hw_endpoint_xfer_start(ep, buffer, buflen);
hw_endpoint_xfer_start(ep, buffer, NULL, buflen);
}
return true;

55
src/portable/raspberrypi/rp2040/rp2040_usb.c
View File

@ -35,7 +35,7 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF PROTOTYPE
//--------------------------------------------------------------------+
static void hwep_xfer_sync(hw_endpoint_t *ep);
static void sync_xfer(hw_endpoint_t *ep);
#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
static bool e15_is_critical_frame_period(struct hw_endpoint *ep);
@ -55,6 +55,16 @@ static void unaligned_memcpy(void *dst, const void *src, size_t n) {
}
}
void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, const tu_hwfifo_access_t *access_mode) {
(void)access_mode;
unaligned_memcpy((void *)(uintptr_t)hwfifo, src, len);
}
void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, const tu_hwfifo_access_t *access_mode) {
(void)access_mode;
unaligned_memcpy(dest, (const void *)(uintptr_t)hwfifo, len);
}
void rp2usb_init(void) {
// Reset usb controller
reset_block(RESETS_RESET_USBCTRL_BITS);
@ -127,9 +137,16 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
ep->next_pid ^= 1u;
if (!is_rx) {
// Copy data from user buffer to hw buffer
unaligned_memcpy(ep->hw_data_buf + buf_id * 64, ep->user_buf, buflen);
ep->user_buf += buflen;
if (buflen) {
// Copy data from user buffer/fifo to hw buffer
uint8_t *hw_buf = ep->hw_data_buf + buf_id * 64;
if (ep->is_xfer_fifo) {
tu_hwfifo_write_from_fifo(hw_buf, ep->user_fifo, buflen, NULL);
} else {
unaligned_memcpy(hw_buf, ep->user_buf, buflen);
ep->user_buf += buflen;
}
}
// Mark as full
buf_ctrl |= USB_BUF_CTRL_FULL;
@ -152,7 +169,6 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
// Prepare buffer control register value
void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint* ep) {
const tusb_dir_t dir = tu_edpt_dir(ep->ep_addr);
bool is_rx;
bool is_host = false;
io_rw_32 *ep_ctrl_reg;
@ -211,7 +227,7 @@ void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint* ep)
hwbuf_ctrl_set(buf_ctrl_reg, buf_ctrl);
}
void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t total_len) {
void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, tu_fifo_t *ff, uint16_t total_len) {
hw_endpoint_lock_update(ep, 1);
if (ep->active) {
@ -224,7 +240,14 @@ void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t to
ep->remaining_len = total_len;
ep->xferred_len = 0;
ep->active = true;
ep->user_buf = buffer;
if (ff != NULL) {
ep->user_fifo = ff;
ep->is_xfer_fifo = true;
} else {
ep->user_buf = buffer;
ep->is_xfer_fifo = false;
}
#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
if (ep->e15_bulk_in) {
@ -256,17 +279,20 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(hw_endpoint_t *ep, io_rw_32
// We are continuing a transfer here. If we are TX, we have successfully
// sent some data can increase the length we have sent
assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
} else {
// If we have received some data, so can increase the length
// we have received AFTER we have copied it to the user buffer at the appropriate offset
assert(buf_ctrl & USB_BUF_CTRL_FULL);
unaligned_memcpy(ep->user_buf, ep->hw_data_buf + buf_id * 64, xferred_bytes);
ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
ep->user_buf += xferred_bytes;
uint8_t *hw_buf = ep->hw_data_buf + buf_id * 64;
if (ep->is_xfer_fifo) {
tu_hwfifo_read_to_fifo(hw_buf, ep->user_fifo, xferred_bytes, NULL);
} else {
unaligned_memcpy(ep->user_buf, hw_buf, xferred_bytes);
ep->user_buf += xferred_bytes;
}
}
ep->xferred_len += xferred_bytes;
// Short packet
if (xferred_bytes < ep->wMaxPacketSize) {
@ -278,7 +304,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(hw_endpoint_t *ep, io_rw_32
}
// Update hw endpoint struct with info from hardware after a buff status interrupt
static void __tusb_irq_path_func(hwep_xfer_sync)(hw_endpoint_t *ep) {
static void __tusb_irq_path_func(sync_xfer)(hw_endpoint_t *ep) {
// const uint8_t ep_num = tu_edpt_number(ep->ep_addr);
const tusb_dir_t dir = tu_edpt_dir(ep->ep_addr);
@ -350,8 +376,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
panic("Can't continue xfer on inactive ep %02X", ep->ep_addr);
}
// Update EP struct from hardware state
hwep_xfer_sync(ep);
sync_xfer(ep); // Update EP struct from hardware state
// Now we have synced our state with the hardware. Is there more data to transfer?
// If we are done then notify tinyusb

35
src/portable/raspberrypi/rp2040/rp2040_usb.h
View File

@ -1,14 +1,16 @@
#ifndef RP2040_COMMON_H_
#define RP2040_COMMON_H_
#include "common/tusb_common.h"
#include "pico.h"
#include "hardware/structs/usb.h"
#include "hardware/irq.h"
#include "hardware/resets.h"
#include "hardware/timer.h"
#include "common/tusb_common.h"
#include "osal/osal.h"
#include "common/tusb_fifo.h"
#if defined(RP2040_USB_HOST_MODE) && defined(RP2040_USB_DEVICE_MODE)
#error TinyUSB device and host mode not supported at the same time
#endif
@ -63,32 +65,31 @@ typedef struct hw_endpoint {
uint8_t ep_addr;
uint8_t next_pid;
uint8_t transfer_type;
bool active; // transferring data
bool active; // transferring data
bool is_xfer_fifo; // transfer using fifo
#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
bool e15_bulk_in; // Errata15 device bulk in
uint8_t pending; // Transfer scheduled but not active
#endif
#if CFG_TUH_ENABLED
bool configured; // Is this a valid struct
uint8_t dev_addr;
uint8_t interrupt_num; // for host interrupt endpoints
#endif
uint16_t wMaxPacketSize;
uint8_t *hw_data_buf; // Buffer pointer in usb dpram
// Current transfer information
uint8_t *user_buf; // User buffer in main memory
// transfer info
union {
uint8_t *user_buf; // User buffer in main memory
tu_fifo_t *user_fifo;
};
uint16_t remaining_len;
uint16_t xferred_len;
#if CFG_TUH_ENABLED
// Is this a valid struct
bool configured;
// Only needed for host
uint8_t dev_addr;
// If interrupt endpoint
uint8_t interrupt_num;
#endif
} hw_endpoint_t;
#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
@ -102,7 +103,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool rp2usb_is_host_mode(void) {
return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
}
void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, tu_fifo_t *ff, uint16_t total_len);
bool hw_endpoint_xfer_continue(struct hw_endpoint *ep);
void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
void hw_endpoint_start_next_buffer(struct hw_endpoint *ep);

79
src/tusb_option.h
View File

@ -272,6 +272,25 @@
// USBIP
//--------------------------------------------------------------------+
//------------- ChipIdea -------------//
// Enable CI_HS VBUS Charge. Set this to 1 if the USB_VBUS pin is not connected to 5V VBUS (note: 3.3V is
// insufficient).
#ifndef CFG_TUD_CI_HS_VBUS_CHARGE
#ifndef CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
#define CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT 0
#endif
#define CFG_TUD_CI_HS_VBUS_CHARGE CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
#endif
// CI_HS support FIFO transfer if endpoint buffer is 4k aligned and size is multiple of 4k, also DCACHE is disabled
#ifndef CFG_TUD_CI_HS_EPBUF_4K_ALIGNED
#define CFG_TUD_CI_HS_EPBUF_4K_ALIGNED 0
#endif
#if CFG_TUD_CI_HS_EPBUF_4K_ALIGNED && !CFG_TUD_MEM_DCACHE_ENABLE
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
#endif
//------------- DWC2 -------------//
// DMA mode for device
#ifndef CFG_TUD_DWC2_DMA_ENABLE
@ -317,41 +336,6 @@
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 0 // fixed hwfifo address
#endif
//------------- ChipIdea -------------//
// Enable CI_HS VBUS Charge. Set this to 1 if the USB_VBUS pin is not connected to 5V VBUS (note: 3.3V is
// insufficient).
#ifndef CFG_TUD_CI_HS_VBUS_CHARGE
#ifndef CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
#define CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT 0
#endif
#define CFG_TUD_CI_HS_VBUS_CHARGE CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
#endif
// CI_HS support FIFO transfer if endpoint buffer is 4k aligned and size is multiple of 4k, also DCACHE is disabled
#ifndef CFG_TUD_CI_HS_EPBUF_4K_ALIGNED
#define CFG_TUD_CI_HS_EPBUF_4K_ALIGNED 0
#endif
#if CFG_TUD_CI_HS_EPBUF_4K_ALIGNED && !CFG_TUD_MEM_DCACHE_ENABLE
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
#endif
//------------- Raspberry Pi -------------//
// Enable PIO-USB software host controller
#ifndef CFG_TUH_RPI_PIO_USB
#define CFG_TUH_RPI_PIO_USB 0
#endif
#ifndef CFG_TUD_RPI_PIO_USB
#define CFG_TUD_RPI_PIO_USB 0
#endif
//------------ MAX3421 -------------//
// Enable MAX3421 USB host controller
#ifndef CFG_TUH_MAX3421
#define CFG_TUH_MAX3421 0
#endif
//------------ FSDEV --------------//
#if defined(TUP_USBIP_FSDEV)
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
@ -368,6 +352,12 @@
#endif
#endif
//------------ MAX3421 -------------//
// Enable MAX3421 USB host controller
#ifndef CFG_TUH_MAX3421
#define CFG_TUH_MAX3421 0
#endif
//------------ MUSB --------------//
#if defined(TUP_USBIP_MUSB)
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
@ -375,13 +365,30 @@
#define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS // allow odd 16bit access
#define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS // allow odd 8bit access
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 0 // fixed hwfifo
#endif
//------------- Raspberry Pi -------------//
// Enable PIO-USB software host controller
#ifndef CFG_TUH_RPI_PIO_USB
#define CFG_TUH_RPI_PIO_USB 0
#endif
#ifndef CFG_TUD_RPI_PIO_USB
#define CFG_TUD_RPI_PIO_USB 0
#endif
#if (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUD_RPI_PIO_USB
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 1
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 1
#define CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE
#define CFG_TUSB_FIFO_HWFIFO_CUSTOM_READ
#endif
//------------ RUSB2 --------------//
#if defined(TUP_USBIP_RUSB2)
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE (2 | (TUD_OPT_HIGH_SPEED ? 4 : 0)) // 16 bit and 32 bit data if highspeed
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE (2 | (TUD_OPT_HIGH_SPEED ? 4 : 0)) // 16 bit and 32 bit if highspeed
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 0
#define CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE // custom write since rusb2 can change access width 32 -> 16 and can write
// odd byte with byte access