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extract core reset

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Signed-off-by: Zixun LI <admin@hifiphile.com>
This commit is contained in:
Zixun LI
2025-11-27 11:02:49 +01:00
parent 270e149276
commit 5d56828e43
4 changed files with 38 additions and 37 deletions
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18
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
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@ -173,23 +173,9 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint8_t epnum, uint
//--------------------------------------------------------------------+
bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rh_init;
// Follow the RM mentions to use a special ordering of PDWN and FRES
for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
// Perform USB peripheral reset
FSDEV_REG->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
fsdev_core_reset();
FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
// Wait startup time, for F042 and F070, this is <= 1 us.
for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
FSDEV_REG->CNTR = 0; // Enable USB
#if !defined(FSDEV_BUS_32BIT)
@ -197,8 +183,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
FSDEV_REG->BTABLE = FSDEV_BTABLE_BASE;
#endif
FSDEV_REG->ISTR = 0; // Clear pending interrupts
// Reset endpoints to disabled
for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {
// This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.

32
src/portable/st/stm32_fsdev/fsdev_common.c
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@ -31,6 +31,35 @@
#include "fsdev_common.h"
//--------------------------------------------------------------------+
// Global
//--------------------------------------------------------------------+
// Reset the USB Core
void fsdev_core_reset(void) {
// Follow the RM mentions to use a special ordering of PDWN and FRES
for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
// Perform USB peripheral reset
FSDEV_REG->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
// Wait startup time, for F042 and F070, this is <= 1 us.
for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
// Clear pending interrupts
FSDEV_REG->ISTR = 0;
}
//--------------------------------------------------------------------+
// PMA read/write
//--------------------------------------------------------------------+
@ -199,7 +228,7 @@ bool fsdev_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes)
// BTable Helper
//--------------------------------------------------------------------+
/* Aligned buffer size according to hardware */
// Aligned buffer size according to hardware
uint16_t pma_align_buffer_size(uint16_t size, uint8_t* blsize, uint8_t* num_block) {
/* The STM32 full speed USB peripheral supports only a limited set of
* buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
@ -217,6 +246,7 @@ uint16_t pma_align_buffer_size(uint16_t size, uint8_t* blsize, uint8_t* num_bloc
return (*num_block) * block_in_bytes;
}
// Set RX buffer size
void btable_set_rx_bufsize(uint32_t ep_id, uint8_t buf_id, uint16_t wCount) {
uint8_t blsize, num_block;
(void) pma_align_buffer_size(wCount, &blsize, &num_block);

6
src/portable/st/stm32_fsdev/fsdev_common.h
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@ -311,9 +311,13 @@ TU_ATTR_ALWAYS_INLINE static inline void btable_set_count(uint32_t ep_id, uint8_
#endif
}
/* Aligned buffer size according to hardware */
// Reset the USB Core
void fsdev_core_reset(void);
// Aligned buffer size according to hardware
uint16_t pma_align_buffer_size(uint16_t size, uint8_t* blsize, uint8_t* num_block);
// Set RX buffer size
void btable_set_rx_bufsize(uint32_t ep_id, uint8_t buf_id, uint16_t wCount);
//--------------------------------------------------------------------+

19
src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c
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@ -203,26 +203,9 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rh_init;
// Follow the RM mentions to use a special ordering of PDWN and FRES
for (volatile uint32_t i = 0; i < 200; i++) {
asm("NOP");
}
// Perform USB peripheral reset
FSDEV_REG->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
for (volatile uint32_t i = 0; i < 200; i++) {
asm("NOP");
}
FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
// Wait startup time
for (volatile uint32_t i = 0; i < 200; i++) {
asm("NOP");
}
fsdev_core_reset();
FSDEV_REG->CNTR = USB_CNTR_HOST; // Enable USB in Host mode
FSDEV_REG->ISTR = 0; // Clear pending interrupts
// Reset channels to disabled
for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {