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stm32n6: TRACE_ETM support and stm32n657nucleo reference

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M55 flashless RAM image: Development boot (JP2/BOOT1=1) REQUIRED - flash
boot parks the chip un-attachable. 300 MHz core (TRACE_ETM selects IC1/4;
600 MHz kills the stream in the startup burst), 18.75 MHz TRACECLK
(cpu/16) width 4; N6 trace components are ROM-table-discoverable, no
J-Link script.
This commit is contained in:
hathach
2026-07-24 15:28:52 +07:00
parent 93443d3b46
commit 63bccf47c6
3 changed files with 122 additions and 0 deletions
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6
hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
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@ -152,7 +152,13 @@ static void SystemClock_Config(void) {
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5);
RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;
RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
#ifdef TRACE_ETM
// 300 MHz CPU -> 37.5 MHz TPIU clock (fixed cpu/8): at 600 MHz the trace
// stream dies with unknown-packet decode errors in the startup burst
RCC_ClkInitStruct.IC1Selection.ClockDivider = 4;
#else
RCC_ClkInitStruct.IC1Selection.ClockDivider = 2;
#endif
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
RCC_ClkInitStruct.IC2Selection.ClockDivider = 3;

94
hw/bsp/stm32n6/boards/stm32n657nucleo/ozone/stm32n657.jdebug Normal file
View File

@ -0,0 +1,94 @@
/*********************************************************************
*
* OnProjectLoad
*
* Function description
* Project load routine. Required.
*
* Notes
* Nucleo-N657X0-Q wires 4-bit trace to the CN1 MIPI20 natively (SB36/38/
* 39/40/41 fitted by default): TRACE_CLK = PB3, D0/D1/D2/D3 =
* PE3/PB0/PB6/PB7 (MB1940 Table 5). No J-Link script needed - the N6
* trace components sit behind a ROM table J-Link discovers natively.
*
* BOOT1 (JP2) must select Development boot (BOOT1 = 1): the N657 is
* flashless, the app is a RAM image (AXISRAM2) loaded by the debugger,
* and in flash boot the bootROM parks the chip un-attachable.
* Firmware must be built with TRACE_ETM=1 (pin mux + DBGMCU
* DBGCLKEN/TRACECLKEN). Trace clock = cpu/8. TRACE_ETM builds run a 300 MHz core (board.h) ->
* 37.5 MHz TPIU clock: 600 MHz kills the stream in the startup burst.
*
**********************************************************************
*/
void OnProjectLoad (void) {
Project.SetTraceSource ("Trace Pins");
Project.SetTracePortWidth (4);
Project.SetSWO (0);
Edit.SysVar (VAR_TRACE_CORE_CLOCK, 300000000);
Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M55F.svd");
Project.SetDevice ("STM32N657X0");
Project.SetHostIF ("USB", "");
Project.SetTargetIF ("SWD");
Project.SetTIFSpeed ("4 MHz");
File.Open ("../../../../../../examples/cmake-build-stm32n657nucleo/device/cdc_msc/cdc_msc.elf");
}
/*********************************************************************
*
* AfterTargetReset
*
* Function description
* Event handler routine.
* - Sets the PC register to program reset value.
* - Sets the SP register to program reset value on Cortex-M.
*
**********************************************************************
*/
void AfterTargetReset (void) {
unsigned int SP;
unsigned int PC;
unsigned int VectorTableAddr;
VectorTableAddr = Elf.GetBaseAddr();
if (VectorTableAddr == 0xFFFFFFFF) {
Util.Log("Project file error: failed to get program base");
} else {
SP = Target.ReadU32(VectorTableAddr);
Target.SetReg("SP", SP);
PC = Target.ReadU32(VectorTableAddr + 4);
Target.SetReg("PC", PC);
}
}
/*********************************************************************
*
* AfterTargetDownload
*
* Function description
* Event handler routine.
* - Sets the PC register to program reset value.
* - Sets the SP register to program reset value on Cortex-M.
*
**********************************************************************
*/
void AfterTargetDownload (void) {
unsigned int SP;
unsigned int PC;
unsigned int VectorTableAddr;
VectorTableAddr = Elf.GetBaseAddr();
if (VectorTableAddr == 0xFFFFFFFF) {
Util.Log("Project file error: failed to get program base");
} else {
SP = Target.ReadU32(VectorTableAddr);
Target.SetReg("SP", SP);
PC = Target.ReadU32(VectorTableAddr + 4);
Target.SetReg("PC", PC);
}
}

22
hw/bsp/stm32n6/family.c
View File

@ -110,6 +110,27 @@ void USB1_OTG_HS_IRQHandler(void) {
tusb_int_handler(0, true);
}
#ifdef TRACE_ETM
static void trace_etm_init(void) {
// Nucleo-N657X0-Q routes 4-bit trace to the CN1 MIPI20 natively:
// TRACE_CLK = PB3, D0 = PE3, D1 = PB0, D2 = PB6, D3 = PB7 (MB1940 Table 5)
GPIO_InitTypeDef gpio_init;
gpio_init.Mode = GPIO_MODE_AF_PP;
gpio_init.Pull = GPIO_NOPULL;
gpio_init.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
gpio_init.Alternate = GPIO_AF0_TRACE;
gpio_init.Pin = GPIO_PIN_0 | GPIO_PIN_3 | GPIO_PIN_6 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOB, &gpio_init);
gpio_init.Pin = GPIO_PIN_3;
HAL_GPIO_Init(GPIOE, &gpio_init);
// trace clock (ck_cpu_tpiu) is a fixed cpu/8 - just enable it
DBGMCU->CR |= DBGMCU_CR_DBGCLKEN | DBGMCU_CR_TRACECLKEN;
}
#else
#define trace_etm_init()
#endif
void board_init(void) {
/* Enable BusFault and SecureFault handlers (HardFault is default) */
SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
@ -148,6 +169,7 @@ void board_init(void) {
for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
}
trace_etm_init();
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
NVIC_EnableIRQ(UCPD1_IRQn);