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update risc-v march for gcc and clang toolchains

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- add `zifencei` option

Signed-off-by: Zhihong Chen <zhihong.chen@hpmicro.com>
This commit is contained in:
Zhihong Chen
2025-12-08 17:14:12 +08:00
parent ba3319d90d
commit 6b73d786b3
2 changed files with 4 additions and 4 deletions
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4
examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
View File

@ -1,13 +1,13 @@
if (TOOLCHAIN STREQUAL "gcc")
set(TOOLCHAIN_COMMON_FLAGS
-march=rv32imac_zicsr
-march=rv32imac_zicsr_zifencei
-mabi=ilp32
)
set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
elseif (TOOLCHAIN STREQUAL "clang")
set(TOOLCHAIN_COMMON_FLAGS
-march=rv32imac_zicsr
-march=rv32imac_zicsr_zifencei
-mabi=ilp32
)
set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")

4
examples/build_system/make/cpu/rv32imac-ilp32.mk
View File

@ -1,11 +1,11 @@
ifeq ($(TOOLCHAIN),gcc)
CFLAGS += \
-march=rv32imac_zicsr \
-march=rv32imac_zicsr_zifencei \
-mabi=ilp32 \
else ifeq ($(TOOLCHAIN),clang)
CFLAGS += \
-march=rv32imac_zicsr \
-march=rv32imac_zicsr_zifencei \
-mabi=ilp32 \
else ifeq ($(TOOLCHAIN),iar)