ch32h417: register in CI matrix, lwIP throughput, docs and presets

Final integration for the CH32H417 port.

- .github/workflows/ci_set_matrix.py: add ch32h417 (riscv-gcc) so CI builds it.
- examples/device/net_lwip_webserver: enable LWIP_HIGH_THROUGHPUT for the H417
  (SuperSpeed iperf).
- docs/reference/{boards,dependencies}.rst + hw/bsp/BoardPresets.json: regenerated
  for the new board and dependency.

usbtest quirks intentionally left at 0 for the H417: its endpoint engine fixes the
two CH569 5 Gbps silicon limitations (RB_EP_TX/RX_HALT gives a repeatable STALL for
case 13; the reworked EP0/chain path is expected free of the wLength%4==1 ctrl_out
drop), so the H417 targets a full 30/30 at SuperSpeed rather than 27/27.

The HIL entry (test/hil/tinyusb.json) is deliberately deferred: it needs the chip's
ESIG unique id read from the board on first flash, which is pending hardware access.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm
This commit is contained in:
hathach
2026-07-12 05:02:59 +07:00
parent fbdbcd092e
commit 741776311b
5 changed files with 26 additions and 0 deletions

View File

@ -30,6 +30,7 @@ family_list = {
"ch32v10x": ["riscv-gcc"],
"ch32v20x": ["riscv-gcc"],
"ch32v30x": ["riscv-gcc"],
"ch32h417": ["riscv-gcc"],
"ch569": ["riscv-gcc"],
"ch583": ["riscv-gcc"],
"da1469x": ["arm-gcc"],

View File

@ -367,6 +367,7 @@ WCH
Board Name Family URL Note
================== ============================= ======== ===================================================================== ======
ch32f205r-r0 CH32F205r-r0 ch32f20x https://github.com/openwch/ch32f20x
nanoch32h417 nanoCH32H417 ch32h417 https://github.com/wuxx/nanoCH32H417
ch32v103c_bluepill CH32V103C8T6-Bluepill ch32v10x https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill
ch32v103r_r1_1v0 CH32V103R-R1-1v1 ch32v10x https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1
ch32v203c_r0_1v0 CH32V203C-R0-1v0 ch32v20x https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0

View File

@ -87,6 +87,7 @@ hw/mcu/st/stm32wbaxx_hal_driver https://github.com/STMicroelectronics/
hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git d60dd46996876506f1d2e9abd6b1cc110c8004cd stm32wb
hw/mcu/ti https://github.com/hathach/ti_driver.git 083944907e7d08fcb1f614b47598ce45935b8da1 msp430 msp432e4 tm4c
hw/mcu/wch/ch32f20x https://github.com/openwch/ch32f20x.git 77c4095087e5ed2c548ec9058e655d0b8757663b ch32f20x
hw/mcu/wch/ch32h417 https://github.com/openwch/ch32h417.git a0a56fa830b860297a64a72315a731b71c841329 ch32h417
hw/mcu/wch/ch32v103 https://github.com/openwch/ch32v103.git 7578cae0b21f86dd053a1f781b2fc6ab99d0ec17 ch32v10x
hw/mcu/wch/ch32v20x https://github.com/openwch/ch32v20x.git c4c38f507e258a4e69b059ccc2dc27dde33cea1b ch32v20x
hw/mcu/wch/ch32v307 https://github.com/openwch/ch32v307.git 184f21b852cb95eed58e86e901837bc9fff68775 ch32v30x

View File

@ -104,6 +104,7 @@ extern "C" {
TU_CHECK_MCU(OPT_MCU_STM32H5, OPT_MCU_STM32H7, OPT_MCU_STM32H7RS) || \
TU_CHECK_MCU(OPT_MCU_STM32C5, OPT_MCU_STM32U5, OPT_MCU_STM32N6) || \
TU_CHECK_MCU(OPT_MCU_RP2040, OPT_MCU_CH32V307, OPT_MCU_CH569) || \
TU_CHECK_MCU(OPT_MCU_CH32H417) || \
TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX) || \
TU_CHECK_MCU(OPT_MCU_NRF5X)
#define LWIP_HIGH_THROUGHPUT 1

View File

@ -454,6 +454,10 @@
"name": "msp_exp432e401y",
"inherits": "default"
},
{
"name": "nanoch32h417",
"inherits": "default"
},
{
"name": "nanoch32v203",
"inherits": "default"
@ -1571,6 +1575,11 @@
"description": "Build preset for the msp_exp432e401y board",
"configurePreset": "msp_exp432e401y"
},
{
"name": "nanoch32h417",
"description": "Build preset for the nanoch32h417 board",
"configurePreset": "nanoch32h417"
},
{
"name": "nanoch32v203",
"description": "Build preset for the nanoch32v203 board",
@ -3722,6 +3731,19 @@
}
]
},
{
"name": "nanoch32h417",
"steps": [
{
"type": "configure",
"name": "nanoch32h417"
},
{
"type": "build",
"name": "nanoch32h417"
}
]
},
{
"name": "nanoch32v203",
"steps": [