ci_hs: add deinit support

Signed-off-by: Zixun LI <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
This commit is contained in:
Zixun LI
2025-12-03 16:26:56 +01:00
committed by HiFiPhile
parent d9f369ed68
commit 8ae01eac64
6 changed files with 43 additions and 10 deletions

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@ -1,4 +1,6 @@
family:espressif
mcu:LPC43XX
mcu:MIMXRT1XXX
mcu:STM32C0
mcu:STM32G0
mcu:STM32H5

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@ -185,8 +185,10 @@ void board_init(void)
*/
Chip_USB1_Init();
#ifdef _BOARD_EA4357_H
// USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
#endif
#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
// P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.

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@ -285,6 +285,23 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
return true;
}
bool dcd_deinit(uint8_t rhport) {
ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
// disable all interrupt
dcd_reg->USBINTR = 0;
// unattach from bus
dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
// flush all endpoints
while (dcd_reg->ENDPTPRIME) {}
dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
while (dcd_reg->ENDPTFLUSH) {}
return true;
}
void dcd_int_enable(uint8_t rhport) {
CI_DCD_INT_ENABLE(rhport);
}

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@ -93,21 +93,25 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
hcd_reg->USBCMD |= USBCMD_RESET;
while (hcd_reg->USBCMD & USBCMD_RESET) {}
// Set mode to device, must be set immediately after reset
#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
// Set mode to host, must be set immediately after reset
#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
// LPC18XX/43XX need to set VBUS Power Select to HIGH
// RHPORT1 is fullspeed only (need external PHY for Highspeed)
hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
if (rhport == 1) {
hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
}
#else
hcd_reg->USBMODE = USBMODE_CM_HOST;
#if !TUH_OPT_HIGH_SPEED
hcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
#endif
#else
hcd_reg->USBMODE = USBMODE_CM_HOST;
#endif
return ehci_init(rhport, (uint32_t)&hcd_reg->CAPLENGTH, (uint32_t)&hcd_reg->USBCMD);
}
bool hcd_deinit(uint8_t rhport) {
return ehci_deinit(rhport);
}
void hcd_int_enable(uint8_t rhport) {
CI_HCD_INT_ENABLE(rhport);
}

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@ -411,17 +411,22 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
return true;
}
#if 0
static void ehci_stop(uint8_t rhport) {
bool ehci_deinit(uint8_t rhport) {
(void) rhport;
ehci_registers_t* regs = ehci_data.regs;
// Disable all the interrupt
regs->inten = 0;
// Disable schedules
regs->command_bm.run_stop = 0;
// USB Spec: controller has to stop within 16 uframe = 2 frames
while( regs->status_bm.hc_halted == 0 ) {}
return true;
}
#endif
//--------------------------------------------------------------------+
// Endpoint API

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@ -38,6 +38,9 @@
// Initialize EHCI driver
bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg);
// De-initialize EHCI driver
bool ehci_deinit(uint8_t rhport);
#ifdef __cplusplus
}
#endif