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portable/chipidea: name SBUSCFG in ci_hs_regs_t, unify AHB burst hook

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Replace the duplicated per-MCU dispatch in dcd_init/hcd_init and the two
helper flavors (USB_Type access on iMX RT, raw offset 0x90 on LPC18/43)
with one SBUSCFG register field plus a per-header CI_HS_SET_AHB_BURST()
hook, compiled only where defined. The LPC USB0-only policy is now
visible at the macro definition.
This commit is contained in:
hathach
2026-08-13 14:35:01 +07:00
parent 6271842ea8
commit 8ccd0d5497
5 changed files with 18 additions and 31 deletions
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11
src/portable/chipidea/ci_hs/ci_hs_imxrt.h
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@ -36,15 +36,8 @@ static const ci_hs_controller_t _ci_controller[] =
#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
enum {
// INCR16/8/4 followed by an unspecified-length burst for the remainder.
CI_HS_IMXRT_AHBBRST_INCR16_UNSPEC = 0x07u,
};
TU_ATTR_ALWAYS_INLINE static inline void ci_hs_imxrt_set_ahb_burst(uint8_t rhport) {
USB_Type *usb = (USB_Type *)_ci_controller[rhport].reg_base;
usb->SBUSCFG = USB_SBUSCFG_AHBBRST(CI_HS_IMXRT_AHBBRST_INCR16_UNSPEC);
}
// NXP recommends AHBBRST = INCR16 (remainder as unspecified-length bursts)
#define CI_HS_SET_AHB_BURST(_p) (CI_HS_REG(_p)->SBUSCFG = SBUSCFG_AHBBRST_INCR16_UNSPEC)
//------------- DCD -------------//
#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)

17
src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
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@ -34,18 +34,9 @@ static const ci_hs_controller_t _ci_controller[] =
#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
enum {
CI_HS_LPC18_43_SBUSCFG_OFFSET = 0x90u,
CI_HS_LPC18_43_AHBBRST_INCR16_UNSPEC = 0x07u,
};
TU_ATTR_ALWAYS_INLINE static inline void ci_hs_lpc18_43_set_ahb_burst(uint8_t rhport) {
// USB0 SBUSCFG is at offset 0x90. NXP recommends AHBBRST=0x7:
// INCR16 with non-multiple transfers decomposed into smaller unspecified bursts.
if (rhport == 0) {
volatile uint32_t *sbuscfg = (volatile uint32_t *)(_ci_controller[rhport].reg_base + CI_HS_LPC18_43_SBUSCFG_OFFSET);
*sbuscfg = CI_HS_LPC18_43_AHBBRST_INCR16_UNSPEC;
}
}
// USB0 (high-speed) only: NXP recommends AHBBRST = INCR16 (remainder as
// unspecified-length bursts)
#define CI_HS_SET_AHB_BURST(_p) \
do { if ((_p) == 0) { CI_HS_REG(_p)->SBUSCFG = SBUSCFG_AHBBRST_INCR16_UNSPEC; } } while (0)
#endif

9
src/portable/chipidea/ci_hs/ci_hs_type.h
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@ -71,11 +71,18 @@ enum {
USBMODE_VBUS_POWER_SELECT = TU_BIT(5), // Need to be enabled for LPC18XX/43XX in host mode
};
// SBUSCFG
enum {
SBUSCFG_AHBBRST_INCR16_UNSPEC = 7, // INCR16 burst, remainder as unspecified-length bursts
};
// Device Registers
typedef struct
{
//------------- ID + HW Parameter Registers-------------//
volatile uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
volatile uint32_t TU_RESERVED[36]; ///< ID/HW parameter registers, not used by this driver
volatile uint32_t SBUSCFG; ///< System Bus Interface Configuration (not present on every MCU)
volatile uint32_t TU_RESERVED[27];
//------------- Capability Registers-------------//
volatile uint8_t CAPLENGTH; ///< Capability Registers Length

6
src/portable/chipidea/ci_hs/dcd_ci_hs.c
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@ -237,10 +237,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
usbmode |= USBMODE_CM_DEVICE;
dcd_reg->USBMODE = usbmode;
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
ci_hs_imxrt_set_ahb_burst(rhport);
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
ci_hs_lpc18_43_set_ahb_burst(rhport);
#ifdef CI_HS_SET_AHB_BURST
CI_HS_SET_AHB_BURST(rhport);
#endif
#ifdef CFG_TUD_CI_HS_VBUS_CHARGE

6
src/portable/chipidea/ci_hs/hcd_ci_hs.c
View File

@ -82,10 +82,8 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
hcd_reg->USBMODE = USBMODE_CM_HOST;
#endif
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
ci_hs_imxrt_set_ahb_burst(rhport);
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
ci_hs_lpc18_43_set_ahb_burst(rhport);
#ifdef CI_HS_SET_AHB_BURST
CI_HS_SET_AHB_BURST(rhport);
#endif
#if !TUH_OPT_HIGH_SPEED