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Merge branch 'hathach:master' into non-blocking-host-v2

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This commit is contained in:
Cédric Berger
2026-02-22 21:39:14 +01:00
committed by GitHub
parent 90d0514630 dc072da5cc
commit 942479407e
74 changed files with 1388 additions and 1137 deletions
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8
.circleci/config2.yml
View File

@ -110,7 +110,7 @@ commands:
no_output_timeout: 20m
command: |
if [ << parameters.toolchain >> == esp-idf ]; then
docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.2 python tools/build.py << parameters.build-args >> << parameters.family >>
docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.2 python tools/build.py << parameters.build-args >> --target all << parameters.family >>
else
# Toolchain option default is gcc
if [ << parameters.toolchain >> == arm-clang ]; then
@ -124,7 +124,11 @@ commands:
# circleci docker return $nproc as 36 core, limit parallel to 4 (resource-class = large)
# Required for IAR, also prevent crashed/killed by docker
python tools/build.py -s << parameters.build-system >> $TOOLCHAIN_OPTION -j 4 << parameters.build-args >> << parameters.family >>
BUILD_PY_ARGS="-s << parameters.build-system >> $TOOLCHAIN_OPTION -j 4 << parameters.build-args >> --target all"
if [ << parameters.build-system >> == "cmake" ]; then
BUILD_PY_ARGS="$BUILD_PY_ARGS --target tinyusb_metrics"
fi
python tools/build.py $BUILD_PY_ARGS << parameters.family >>
fi
# Only collect and persist metrics for cmake builds (excluding esp-idf and --one-random)

1
.github/actions/get_deps/action.yml vendored
View File

@ -22,6 +22,7 @@ runs:
NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.13.1/ninja-linux.zip
wget $NINJA_URL -O ninja-linux.zip
unzip ninja-linux.zip -d ninja-bin
pip install membrowse
echo >> $GITHUB_PATH "${{ github.workspace }}/ninja-bin"
shell: bash

494
.github/membrowse-targets.json vendored
View File

@ -1,494 +0,0 @@
{
"templates": {
"build_cmd": "python3 tools/build.py -s cmake -b ${board}",
"elf": "cmake-build/cmake-build-${board}/device/${example}/${example}.elf",
"setup_cmd": "${toolchain.setup_cmd} && python3 tools/get_deps.py ${get_deps}",
"get_deps": "${port}"
},
"toolchains": {
"arm-none-eabi-gcc-14": {
"setup_cmd": "NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.13.1/ninja-linux.zip && wget -q $NINJA_URL -O ninja-linux.zip && unzip -q ninja-linux.zip -d $HOME/bin && echo \"$HOME/bin\" >> $GITHUB_PATH && TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v14.2.1-1.1/xpack-arm-none-eabi-gcc-14.2.1-1.1-linux-x64.tar.gz && mkdir -p $HOME/toolchain && wget -q $TOOLCHAIN_URL -O toolchain.tar.gz && tar -C $HOME/toolchain -xf toolchain.tar.gz && echo \"$HOME/toolchain/xpack-arm-none-eabi-gcc-14.2.1-1.1/bin\" >> $GITHUB_PATH"
},
"aarch64-none-elf-gcc-10": {
"setup_cmd": "NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.13.1/ninja-linux.zip && wget -q $NINJA_URL -O ninja-linux.zip && unzip -q ninja-linux.zip -d $HOME/bin && echo \"$HOME/bin\" >> $GITHUB_PATH && TOOLCHAIN_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz && mkdir -p $HOME/toolchain && wget -q $TOOLCHAIN_URL -O toolchain.tar.xz && tar -C $HOME/toolchain -xf toolchain.tar.xz && echo \"$HOME/toolchain/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin\" >> $GITHUB_PATH"
},
"riscv-none-elf-gcc-13": {
"setup_cmd": "NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.13.1/ninja-linux.zip && wget -q $NINJA_URL -O ninja-linux.zip && unzip -q ninja-linux.zip -d $HOME/bin && echo \"$HOME/bin\" >> $GITHUB_PATH && TOOLCHAIN_URL=https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz && mkdir -p $HOME/toolchain && wget -q $TOOLCHAIN_URL -O toolchain.tar.gz && tar -C $HOME/toolchain -xf toolchain.tar.gz && echo \"$HOME/toolchain/xpack-riscv-none-elf-gcc-13.2.0-2/bin\" >> $GITHUB_PATH"
},
"msp430-gcc-9": {
"setup_cmd": "NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.13.1/ninja-linux.zip && wget -q $NINJA_URL -O ninja-linux.zip && unzip -q ninja-linux.zip -d $HOME/bin && echo \"$HOME/bin\" >> $GITHUB_PATH && TOOLCHAIN_URL=http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2 && mkdir -p $HOME/toolchain && wget -q $TOOLCHAIN_URL -O toolchain.tar.bz2 && tar -C $HOME/toolchain -xf toolchain.tar.bz2 && echo \"$HOME/toolchain/msp430-gcc-9.2.0.50_linux64/bin\" >> $GITHUB_PATH"
}
},
"targets": [
{
"port": "at32f402_405",
"board": "at_start_f402",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/artery/at32f402_405/libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F402xC_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "at32f403a_407",
"board": "at32f403a_weact_blackpill",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/artery/at32f403a_407/libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F403AxC_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "at32f413",
"board": "at_start_f413",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/artery/at32f413/libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F413xC_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "at32f415",
"board": "at_start_f415",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/artery/at32f415/libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F415xC_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "at32f423",
"board": "at_start_f423",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/artery/at32f423/libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F423xC_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "at32f425",
"board": "at_start_f425",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/artery/at32f425/libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F425x8_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "at32f435_437",
"board": "at_start_f435",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/artery/at32f435_437/libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F435xM_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "broadcom_32bit",
"board": "raspberrypi_zero",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/broadcom/broadcom/link.ld",
"example": "cdc_msc"
},
{
"port": "broadcom_64bit",
"board": "raspberrypi_cm4",
"toolchain": "aarch64-none-elf-gcc-10",
"ld": "hw/mcu/broadcom/broadcom/link8.ld",
"example": "cdc_msc"
},
{
"port": "ch32v10x",
"board": "ch32v103r_r1_1v0",
"toolchain": "riscv-none-elf-gcc-13",
"ld": "hw/bsp/ch32v10x/linker/ch32v10x.ld",
"linker_vars": "__FLASH_SIZE=64K __RAM_SIZE=20K",
"example": "cdc_msc"
},
{
"port": "ch32v20x",
"board": "ch32v203c_r0_1v0",
"toolchain": "riscv-none-elf-gcc-13",
"ld": "hw/bsp/ch32v20x/linker/ch32v20x.ld",
"linker_vars": "__flash_size=64K __ram_size=20K",
"example": "cdc_msc"
},
{
"port": "ch32v30x",
"board": "ch32v307v_r1_1v0",
"toolchain": "riscv-none-elf-gcc-13",
"ld": "hw/bsp/ch32v30x/linker/ch32v30x.ld",
"linker_vars": "__flash_size=128K __ram_size=32K",
"example": "cdc_msc"
},
{
"port": "da1469x",
"board": "da14695_dk_usb",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/da1469x/linker/da1469x.ld",
"example": "cdc_msc"
},
{
"port": "fomu",
"board": "fomu",
"toolchain": "riscv-none-elf-gcc-13",
"ld": "hw/bsp/fomu/fomu.ld",
"example": "cdc_msc"
},
{
"port": "gd32vf103",
"board": "sipeed_longan_nano",
"toolchain": "riscv-none-elf-gcc-13",
"ld": "hw/mcu/gd/nuclei-sdk/SoC/gd32vf103/Board/gd32vf103c_longan_nano/Source/GCC/gcc_gd32vf103xb_flashxip.ld",
"linker_vars": "__ROM_BASE=0x08000000 __ROM_SIZE=0x00020000 __RAM_BASE=0x20000000 __RAM_SIZE=0x00008000",
"example": "cdc_msc"
},
{
"port": "hpmicro",
"board": "hpm6750evk2",
"toolchain": "riscv-none-elf-gcc-13",
"ld": "hw/mcu/hpmicro/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_xip.ld",
"linker_vars": "_flash_size=16M _stack_size=16K _heap_size=16K",
"example": "cdc_msc"
},
{
"port": "imxrt",
"board": "metro_m7_1011",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/nxp/mcux-sdk/devices/MIMXRT1011/gcc/MIMXRT1011xxxxx_flexspi_nor.ld",
"example": "cdc_msc"
},
{
"port": "kinetis_k",
"board": "frdm_k64f",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/nxp/mcux-sdk/devices/MK64F12/gcc/MK64FN1M0xxx12_flash.ld",
"get_deps": "kinetis_k kinetis_kl",
"example": "cdc_msc"
},
{
"port": "kinetis_k32l2",
"board": "frdm_k32l2a4s",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/nxp/mcux-sdk/devices/K32L2A41A/gcc/K32L2A41xxxxA_flash.ld",
"example": "cdc_msc"
},
{
"port": "kinetis_kl",
"board": "frdm_kl25z",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld",
"example": "cdc_msc"
},
{
"port": "lpc11",
"board": "lpcxpresso11u37",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld",
"example": "cdc_msc"
},
{
"port": "lpc13",
"board": "lpcxpresso1347",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld",
"example": "cdc_msc"
},
{
"port": "lpc15",
"board": "lpcxpresso1549",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld",
"example": "cdc_msc"
},
{
"port": "lpc17",
"board": "lpcxpresso1769",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld",
"example": "cdc_msc"
},
{
"port": "lpc18",
"board": "lpcxpresso18s37",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld",
"example": "cdc_msc"
},
{
"port": "lpc40",
"board": "ea4088_quickstart",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld",
"example": "cdc_msc"
},
{
"port": "lpc43",
"board": "ea4357",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc43/boards/ea4357/lpc4357.ld",
"example": "cdc_msc"
},
{
"port": "lpc51",
"board": "lpcxpresso51u68",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/nxp/mcux-sdk/devices/LPC51U68/gcc/LPC51U68_flash.ld",
"example": "cdc_msc"
},
{
"port": "lpc54",
"board": "lpcxpresso54114",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/nxp/mcux-sdk/devices/LPC54114/gcc/LPC54114J256_cm4_flash.ld",
"example": "cdc_msc"
},
{
"port": "lpc55",
"board": "double_m33_express",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld",
"example": "cdc_msc"
},
{
"port": "maxim",
"board": "apard32690",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/maxim/linker/max32690.ld",
"example": "cdc_msc"
},
{
"port": "mcx",
"board": "frdm_mcxa153",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/nxp/mcux-sdk/devices/MCXA153/gcc/MCXA153_flash.ld",
"example": "cdc_msc"
},
{
"port": "mm32",
"board": "mm32f327x_mb39",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld",
"example": "cdc_msc"
},
{
"port": "msp430",
"board": "msp_exp430f5529lp",
"toolchain": "msp430-gcc-9",
"ld": "hw/mcu/ti/msp430/msp430-gcc-support-files/include/msp430f5529.ld",
"example": "cdc_msc"
},
{
"port": "msp432e4",
"board": "msp_exp432e401y",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/ti/msp432e4/Source/msp432e411y.ld",
"example": "cdc_msc"
},
{
"port": "nrf",
"board": "adafruit_clue",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/nrf/linker/nrf52840_xxaa.ld",
"example": "cdc_msc"
},
{
"port": "nuc100_120",
"board": "nutiny_sdk_nuc120",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/nuc100_120/boards/nutiny_sdk_nuc120/nuc120_flash.ld",
"example": "cdc_msc"
},
{
"port": "nuc121_125",
"board": "nutiny_sdk_nuc121",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/nuc121_125/boards/nutiny_sdk_nuc121/nuc121_flash.ld",
"example": "cdc_msc"
},
{
"port": "nuc126",
"board": "nutiny_nuc126v",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/nuc126/boards/nutiny_nuc126v/nuc126_flash.ld",
"example": "cdc_msc"
},
{
"port": "nuc505",
"board": "nutiny_sdk_nuc505",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/nuc505/boards/nutiny_sdk_nuc505/nuc505_flashtoram.ld",
"example": "cdc_msc"
},
{
"port": "ra",
"board": "portenta_c33",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld hw/bsp/ra/boards/portenta_c33/script/fsp.ld",
"example": "cdc_msc"
},
{
"port": "rw61x",
"board": "frdm_rw612",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/nxp/mcux-sdk/devices/RW612/gcc/RW612_flash.ld",
"example": "cdc_msc"
},
{
"port": "samd11",
"board": "cynthion_d11",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/samd11/boards/cynthion_d11/cynthion_d11.ld",
"linker_vars": "BOOTLOADER_SIZE=0x800",
"example": "cdc_dual_ports"
},
{
"port": "samd5x_e5x",
"board": "metro_m4_express",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/samd5x_e5x/boards/metro_m4_express/metro_m4_express.ld",
"example": "cdc_msc"
},
{
"port": "samg",
"board": "samg55_xplained",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/samg/boards/samg55_xplained/samg55j19_flash.ld",
"example": "cdc_msc"
},
{
"port": "stm32c0",
"board": "stm32c071nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32f0",
"board": "stm32f070rbnucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld",
"example": "cdc_msc"
},
{
"port": "stm32f1",
"board": "stm32f103_bluepill",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32f2",
"board": "stm32f207nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32f3",
"board": "stm32f303disco",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32f4",
"board": "feather_stm32f405",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32f7",
"board": "stlinkv3mini",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32g0",
"board": "stm32g0b1nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32g4",
"board": "b_g474e_dpow1",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32h5",
"board": "stm32h503nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32h5/linker/STM32H533xx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32h7",
"board": "stm32h743eval",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32h7/linker/stm32h743xx_flash.ld",
"example": "cdc_msc"
},
{
"port": "stm32h7rs",
"board": "stm32h7s3nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.ld",
"linker_vars": "__FLASH_BEGIN=0x08000000 __FLASH_SIZE=0x00010000 __RAM_BEGIN=0x24000000 __RAM_SIZE=0x4FC00 __RAM_NONCACHEABLEBUFFER_SIZE=0x400",
"example": "cdc_msc"
},
{
"port": "stm32l0",
"board": "stm32l052dap52",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32l4",
"board": "stm32l412nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32n6",
"board": "stm32n6570dk",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32n6/boards/stm32n6570dk/STM32N657XX_AXISRAM2_fsbl.ld",
"example": "cdc_msc"
},
{
"port": "stm32u0",
"board": "stm32u083cdk",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32u0/boards/stm32u083cdk/STM32U083MCTx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32u5",
"board": "b_u585i_iot2a",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32u5/linker/STM32U5A9xx_FLASH.ld",
"example": "cdc_msc"
},
{
"port": "stm32wb",
"board": "stm32wb55nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld",
"example": "cdc_msc"
},
{
"port": "stm32wba",
"board": "stm32wba_nucleo",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/stm32wba/linker/STM32WBA65xx_FLASH_ns.ld",
"example": "cdc_msc"
},
{
"port": "tm4c",
"board": "ek_tm4c123gxl",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld",
"example": "cdc_msc"
},
{
"port": "xmc4000",
"board": "xmc4500_relax",
"toolchain": "arm-none-eabi-gcc-14",
"ld": "hw/mcu/infineon/mtb-xmclib-cat3/CMSIS/Infineon/COMPONENT_XMC4500/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld",
"example": "cdc_msc"
}
]
}

75
.github/workflows/build.yml vendored
View File

@ -47,8 +47,6 @@ jobs:
- '.github/workflows/ci_set_matrix.py'
set-matrix:
needs: [ check-paths ]
if: needs.check-paths.outputs.code_changed == 'true'
runs-on: ubuntu-latest
outputs:
json: ${{ steps.set-matrix-json.outputs.matrix }}
@ -75,7 +73,7 @@ jobs:
# For Make and IAR build: will be done on CircleCI only (one random per family as well)
# ------------------------------------------------------------------------------
cmake:
needs: set-matrix
needs: [ check-paths, set-matrix ]
uses: ./.github/workflows/build_util.yml
strategy:
fail-fast: false
@ -93,10 +91,14 @@ jobs:
build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
build-options: '--one-first'
upload-metrics: true
upload-artifacts: true
upload-artifacts: false
upload-membrowse: true
code-changed: ${{ needs.check-paths.outputs.code_changed == 'true' }}
secrets: inherit
code-metrics:
needs: cmake
needs: [ check-paths, cmake ]
if: needs.check-paths.outputs.code_changed == 'true'
runs-on: ubuntu-latest
permissions:
pull-requests: write
@ -200,11 +202,12 @@ jobs:
fail-fast: false
matrix:
os: [ windows-latest, macos-latest ]
build-system: [ 'make', 'cmake' ]
with:
os: ${{ matrix.os }}
build-system: 'cmake-make'
build-system: ${{ matrix.build-system }}
toolchain: 'arm-gcc-${{ matrix.os }}'
build-args: '["stm32h7"]'
build-args: '["stm32h7rs"]'
build-options: '--one-random'
# ---------------------------------------
@ -213,7 +216,8 @@ jobs:
zephyr:
needs: [ check-paths ]
# skip zephyr build due to failed build, fix later
if: false && needs.check-paths.outputs.code_changed == 'true'
if: false
#if: needs.check-paths.outputs.code_changed == 'true'
runs-on: ubuntu-latest
steps:
- name: Checkout TinyUSB
@ -235,8 +239,8 @@ jobs:
# Run on PR only (hil-tinyusb), hil-hfp only run on non-forked PR
# ---------------------------------------
hil-build:
needs: set-matrix
if: github.repository_owner == 'hathach'
needs: [ check-paths, set-matrix ]
if: needs.check-paths.outputs.code_changed == 'true' && github.repository_owner == 'hathach'
uses: ./.github/workflows/build_util.yml
strategy:
fail-fast: false
@ -297,6 +301,7 @@ jobs:
hil-hfp:
needs: [ check-paths ]
if: |
needs.check-paths.outputs.code_changed == 'true' &&
github.repository_owner == 'hathach' &&
!(github.event_name == 'pull_request' && github.event.pull_request.head.repo.fork == true)
runs-on: [ self-hosted, Linux, X64, hifiphile ]
@ -331,53 +336,3 @@ jobs:
- name: Test on actual hardware (hardware in the loop)
run: python3 test/hil/hil_test.py hfp.json
# ---------------------------------------
# Membrowse Memory Analysis
# Push: always runs (uses identical for doc-only to maintain commit chain)
# PR: only runs if code changed (doc-only PRs skip entirely)
# ---------------------------------------
membrowse:
needs: [check-paths, cmake]
if: |
always() && !cancelled() && (
github.event_name == 'push' ||
github.event_name == 'release' ||
github.event_name == 'workflow_dispatch' ||
(github.event_name == 'pull_request' && needs.check-paths.outputs.code_changed == 'true')
)
permissions:
contents: read
actions: read
uses: ./.github/workflows/membrowse-report.yml
with:
code_changed: ${{ needs.check-paths.outputs.code_changed == 'true' || github.event_name == 'release' || github.event_name == 'workflow_dispatch' }}
secrets: inherit
membrowse-comment:
needs: membrowse
# skip membrowse comment since it is too verbal
if: false && github.event_name == 'pull_request'
runs-on: ubuntu-latest
permissions:
contents: read
actions: read
steps:
- name: Checkout repository
uses: actions/checkout@v6
- name: Download report artifacts
id: download
uses: actions/download-artifact@v5
with:
pattern: membrowse-report-*
path: reports
merge-multiple: true
continue-on-error: true
- name: Upload Membrowse Comment Artifact
if: steps.download.outcome == 'success'
uses: actions/upload-artifact@v5
with:
name: membrowse-comment
path: reports/

58
.github/workflows/build_util.yml vendored
View File

@ -3,6 +3,10 @@ name: Reusable build util
on:
workflow_call:
inputs:
os:
required: false
type: string
default: 'ubuntu-latest'
build-system:
required: true
type: string
@ -24,10 +28,14 @@ on:
required: false
default: false
type: boolean
os:
upload-membrowse:
required: false
type: string
default: 'ubuntu-latest'
default: false
type: boolean
code-changed:
required: false
default: true
type: boolean
jobs:
family:
@ -39,6 +47,8 @@ jobs:
steps:
- name: Checkout TinyUSB
uses: actions/checkout@v6
with:
fetch-depth: ${{ !inputs.upload-membrowse && 1 || 0 }}
- name: Setup Toolchain
id: setup-toolchain
@ -52,42 +62,40 @@ jobs:
arg: ${{ matrix.arg }}
- name: Build
if: ${{ inputs.code-changed }}
env:
IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
TOOLCHAIN: ${{ inputs.toolchain }}
run: |
if [ "$TOOLCHAIN" == "esp-idf" ]; then
docker run --rm -v $PWD:/project -w /project espressif/idf:tinyusb python tools/build.py ${{ matrix.arg }}
elif [ "${{ inputs.build-system }}" == "cmake-make" ] || [ "${{ inputs.build-system }}" == "make-cmake" ]; then
python tools/build.py -s make ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} ${{ matrix.arg }}
python tools/build.py -s cmake ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} ${{ matrix.arg }}
if [ "${{ inputs.toolchain }}" == "esp-idf" ]; then
docker run --rm -e MEMBROWSE_API_KEY="$MEMBROWSE_API_KEY" -v $PWD:/project -w /project espressif/idf:tinyusb python tools/build.py --target all ${{ matrix.arg }}
else
python tools/build.py -s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} ${{ matrix.arg }}
BUILD_PY_ARGS="-s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} --target all"
if [ "${{ inputs.upload-metrics }}" = "true" ]; then
BUILD_PY_ARGS="$BUILD_PY_ARGS --target tinyusb_metrics"
fi
python tools/build.py $BUILD_PY_ARGS ${{ matrix.arg }}
fi
shell: bash
- name: Membrowse Upload
if: inputs.toolchain != 'esp-idf' && inputs.upload-membrowse == true
env:
MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }}
run: |
# if code-changed is false --> there is no elf -> membrowse target upload with --identical flag
BUILD_PY_ARGS="-s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }}"
python tools/build.py $BUILD_PY_ARGS --target examples-membrowse-upload -j 1 ${{ matrix.arg }}
shell: bash
- name: Upload Artifacts for Metrics
if: ${{ inputs.upload-metrics }}
if: inputs.upload-metrics == true && inputs.code-changed == true
uses: actions/upload-artifact@v5
with:
name: metrics-${{ matrix.arg }}
path: cmake-build/cmake-build-*/metrics.json
- name: Copy linker scripts for artifacts
if: ${{ inputs.upload-artifacts }}
run: |
for dir in cmake-build/cmake-build-*; do
board=$(basename "$dir" | sed 's/cmake-build-//')
ld_path=$(jq -r --arg b "$board" '.targets[] | select(.board == $b) | .ld // empty' .github/membrowse-targets.json)
if [ -n "$ld_path" ] && [ -f "$ld_path" ]; then
mkdir -p "cmake-build/$(dirname "$ld_path")"
cp "$ld_path" "cmake-build/$ld_path"
fi
done
shell: bash
- name: Upload Artifacts for Hardware Testing
if: ${{ inputs.upload-artifacts }}
if: inputs.upload-artifacts == true && inputs.code-changed == true
uses: actions/upload-artifact@v5
with:
name: binaries-${{ matrix.arg }}

74
.github/workflows/ci_set_matrix.py vendored
View File

@ -15,32 +15,76 @@ toolchain_list = [
# family: [supported toolchain]
family_list = {
"at32f45x at32f402_405 at32f403a_407 at32f413 at32f415 at32f423 at32f425 at32f435_437": ["arm-gcc"],
"broadcom_32bit da1469x": ["arm-gcc"],
"at32f402_405": ["arm-gcc"],
"at32f403a_407": ["arm-gcc"],
"at32f413": ["arm-gcc"],
"at32f415": ["arm-gcc"],
"at32f423": ["arm-gcc"],
"at32f425": ["arm-gcc"],
"at32f435_437": ["arm-gcc"],
"at32f45x": ["arm-gcc"],
"broadcom_32bit": ["arm-gcc"],
"broadcom_64bit": ["aarch64-gcc"],
"ch32v10x ch32v20x ch32v30x fomu gd32vf103 hpmicro": ["riscv-gcc"],
"ch32v10x": ["riscv-gcc"],
"ch32v20x": ["riscv-gcc"],
"ch32v30x": ["riscv-gcc"],
"da1469x": ["arm-gcc"],
"fomu": ["riscv-gcc"],
"gd32vf103": ["riscv-gcc"],
"hpmicro": ["riscv-gcc"],
"imxrt": ["arm-gcc", "arm-clang"],
"kinetis_k kinetis_kl kinetis_k32l2": ["arm-gcc", "arm-clang"],
"lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"],
"lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"],
"maxim mcx mm32 msp432e4 rw61x tm4c": ["arm-gcc"],
"kinetis_k": ["arm-gcc", "arm-clang"],
"kinetis_k32l2": ["arm-gcc", "arm-clang"],
"kinetis_kl": ["arm-gcc", "arm-clang"],
"lpc11": ["arm-gcc", "arm-clang"],
"lpc13": ["arm-gcc", "arm-clang"],
"lpc15": ["arm-gcc", "arm-clang"],
"lpc17": ["arm-gcc", "arm-clang"],
"lpc18": ["arm-gcc", "arm-clang"],
"lpc40": ["arm-gcc", "arm-clang"],
"lpc43": ["arm-gcc", "arm-clang"],
"lpc51": ["arm-gcc", "arm-clang"],
"lpc54": ["arm-gcc", "arm-clang"],
"lpc55": ["arm-gcc", "arm-clang"],
"maxim": ["arm-gcc"],
"mcx": ["arm-gcc"],
"mm32": ["arm-gcc"],
"msp430": ["msp430-gcc"],
"msp432e4": ["arm-gcc"],
"nrf": ["arm-gcc", "arm-clang"],
"nuc100_120 nuc121_125 nuc126 nuc505 xmc4000": ["arm-gcc"],
"nuc100_120": ["arm-gcc"],
"nuc121_125": ["arm-gcc"],
"nuc126": ["arm-gcc"],
"nuc505": ["arm-gcc"],
"ra": ["arm-gcc"],
"rp2040": ["arm-gcc"],
"rw61x": ["arm-gcc"],
"rx": ["rx-gcc"],
"samd11 samd2x_l2x samd5x_e5x samg": ["arm-gcc", "arm-clang"],
"stm32c0 stm32f0 stm32f1 stm32f2 stm32f3": ["arm-gcc", "arm-clang", "arm-iar"],
"samd11": ["arm-gcc", "arm-clang"],
"samd2x_l2x": ["arm-gcc", "arm-clang"],
"samd5x_e5x": ["arm-gcc", "arm-clang"],
"samg": ["arm-gcc", "arm-clang"],
"stm32c0": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32f0": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32f1": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32f2": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32f3": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32f4": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32f7": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32g0": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32g4": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32h5": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32h7": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32h7rs stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32h7rs": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32l0": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32n6": ["arm-gcc"],
"stm32u0 stm32u5": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32wb stm32wba": ["arm-gcc", "arm-clang", "arm-iar"],
# "-bespressif_s2_devkitc": ["esp-idf"],
"stm32u0": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32u5": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32wb": ["arm-gcc", "arm-clang", "arm-iar"],
"stm32wba": ["arm-gcc", "arm-clang", "arm-iar"],
"tm4c": ["arm-gcc"],
"xmc4000": ["arm-gcc"],
# S3, P4 will be built by hil test
# "-bespressif_s3_devkitm": ["esp-idf"],
# "-bespressif_p4_function_ev": ["esp-idf"],

101
.github/workflows/membrowse-report.yml vendored
View File

@ -1,101 +0,0 @@
name: Membrowse Memory Report
on:
workflow_call:
inputs:
code_changed:
description: 'Whether code paths changed (true) or doc-only (false)'
type: boolean
required: true
permissions:
contents: read
actions: read
jobs:
load-targets:
runs-on: ubuntu-latest
outputs:
targets: ${{ steps.load.outputs.targets }}
steps:
- name: Checkout repository
uses: actions/checkout@v6
- name: Load target matrix
id: load
run: echo "targets=$(jq -c '.targets' .github/membrowse-targets.json)" >> $GITHUB_OUTPUT
analyze:
needs: [load-targets]
runs-on: ubuntu-latest
strategy:
fail-fast: false
matrix:
include: ${{ fromJson(needs.load-targets.outputs.targets) }}
steps:
- name: Checkout repository
uses: actions/checkout@v6
with:
fetch-depth: 0
submodules: recursive
# Download artifacts when code changed (build artifacts available)
- name: Download build artifacts
if: inputs.code_changed
id: download
uses: actions/download-artifact@v5
with:
pattern: binaries-*
path: cmake-build
merge-multiple: true
continue-on-error: true
- name: Restore linker scripts
if: inputs.code_changed
run: cp -r cmake-build/hw . 2>/dev/null || true
- name: Check if ELF exists
id: check-elf
run: |
if [ -f "cmake-build/cmake-build-${{ matrix.board }}/device/${{ matrix.example }}/${{ matrix.example }}.elf" ]; then
echo "exists=true" >> $GITHUB_OUTPUT
else
echo "exists=false" >> $GITHUB_OUTPUT
fi
# Run with actual ELF analysis when build artifacts available
- name: Run Membrowse Analysis
if: steps.check-elf.outputs.exists == 'true'
id: membrowse
continue-on-error: true
uses: membrowse/membrowse-action@v1
with:
target_name: ${{ matrix.port }}-${{ matrix.board }}-${{ matrix.example }}
elf: cmake-build/cmake-build-${{ matrix.board }}/device/${{ matrix.example }}/${{ matrix.example }}.elf
ld: ${{ matrix.ld }}
linker_vars: ${{ matrix.linker_vars || '' }}
api_key: ${{ secrets.MEMBROWSE_API_KEY }}
api_url: ${{ vars.MEMBROWSE_API_URL }}
verbose: INFO
# Run with identical=true when no ELF (doc-only push)
# Preserves the chain of commits in membrowse tracking
- name: Run Membrowse Identical Report
if: steps.check-elf.outputs.exists == 'false'
id: membrowse-identical
continue-on-error: true
uses: membrowse/membrowse-action@v1
with:
target_name: ${{ matrix.port }}-${{ matrix.board }}-${{ matrix.example }}
identical: true
api_key: ${{ secrets.MEMBROWSE_API_KEY }}
api_url: ${{ vars.MEMBROWSE_API_URL }}
verbose: INFO
- name: Upload report artifact
if: steps.membrowse.outcome == 'success' || steps.membrowse-identical.outcome == 'success'
uses: actions/upload-artifact@v5
with:
name: membrowse-report-${{ matrix.port }}-${{ matrix.board }}-${{ matrix.example }}
path: ${{ steps.membrowse.outputs.report_path || steps.membrowse-identical.outputs.report_path }}

1
.idea/cmake.xml generated
View File

@ -171,6 +171,7 @@
<configuration PROFILE_NAME="mm32f327x_mb39" ENABLED="false" GENERATION_OPTIONS="-DBOARD=mm32f327x_mb39" />
<configuration PROFILE_NAME="fomu" ENABLED="false" GENERATION_OPTIONS="-DBOARD=fomu" />
<configuration PROFILE_NAME="sipeed_longan_nano" ENABLED="false" GENERATION_OPTIONS="-DBOARD=sipeed_longan_nano" />
<configuration PROFILE_NAME="ch32v103r_r1_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v103r_r1_1v0" />
<configuration PROFILE_NAME="nanoch32v203" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=nanoch32v203" />
<configuration PROFILE_NAME="ch32v203c_r0_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DLOG=0" />
<configuration PROFILE_NAME="ch32v203c_r0_1v0 USBFS" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DPORT=1" />

90
hw/bsp/family_support.cmake
View File

@ -267,6 +267,95 @@ function(family_add_linkermap TARGET)
VERBATIM)
endfunction()
# Add membrowse target (installed with pip install membrowse)
function(family_add_membrowse TARGET)
find_program(MEMBROWSE_EXE membrowse)
if (MEMBROWSE_EXE STREQUAL MEMBROWSE_EXE-NOTFOUND)
# force anyway, bash login shell will find it from pip install path
set(MEMBROWSE_EXE membrowse)
endif ()
set(OPTION "")
if (DEFINED MEMBROWSE_OPTION)
string(APPEND OPTION " ${MEMBROWSE_OPTION}")
endif ()
# For Ninja generator, extract all linker scripts from Ninja commands (with INCLUDE) and pass them to membrowse.
if (CMAKE_GENERATOR MATCHES "Ninja")
set(TARGET_ELF_PATH "$<TARGET_FILE_DIR:${TARGET}>/$<TARGET_FILE_NAME:${TARGET}>")
set(MEMBROWSE_LD_SCRIPTS_CMD
"ld_scripts=\"$(${CMAKE_MAKE_PROGRAM} -C ${CMAKE_BINARY_DIR} -t commands ${TARGET} | grep -oP '(?:-Wl,--script=|-T\\s*)\\K[A-Za-z0-9_./-]+\\.ld' | xargs)\"; \
all_ld_scripts=\"\"; \
pending_ld_scripts=\"$ld_scripts\"; \
while [ -n \"$pending_ld_scripts\" ]; do \
next_pending=\"\"; \
for script in $pending_ld_scripts; do \
case \" $all_ld_scripts \" in *\" $script \"*) continue ;; esac; \
all_ld_scripts=\"$all_ld_scripts $script\"; \
script_dir=$(dirname \"$script\"); \
include_scripts=$(grep -hoP '^\\s*INCLUDE\\s+[<\"]?\\K[^\">[:space:]]+\\.ld' \"$script\" 2>/dev/null | xargs); \
for include_script in $include_scripts; do \
resolved_script=\"\"; \
if [ -f \"$include_script\" ]; then \
resolved_script=\"$include_script\"; \
elif [ -f \"$script_dir/$include_script\" ]; then \
resolved_script=\"$script_dir/$include_script\"; \
fi; \
if [ -n \"$resolved_script\" ]; then \
case \" $all_ld_scripts $next_pending \" in *\" $resolved_script \"*) ;; *) next_pending=\"$next_pending $resolved_script\" ;; esac; \
fi; \
done; \
done; \
pending_ld_scripts=\"$(echo \"$next_pending\" | xargs)\"; \
done; \
ld_scripts=\"$(echo \"$all_ld_scripts\" | xargs)\"")
set(MEMBROWSE_LD_DEFS_CMD
"ld_symbols=\"$(${CMAKE_MAKE_PROGRAM} -C ${CMAKE_BINARY_DIR} -t commands ${TARGET} | grep -oP '(?<=--defsym[=,])[^[:space:]]+' | xargs)\"; \
ld_defs=\"\"; \
for symbol in $ld_symbols; do \
ld_defs=\"$ld_defs --def $symbol\"; \
done; \
ld_defs=\"$(echo \"$ld_defs\" | xargs)\"")
set(MEMBROWSE_PREPARE_CMD
"if [ -f \"${TARGET_ELF_PATH}\" ]; then \
${MEMBROWSE_LD_SCRIPTS_CMD}; \
${MEMBROWSE_LD_DEFS_CMD}; \
if [ \"$MEMBROWSE_UPLOAD\" = \"1\" ]; then \
MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} \\\"${TARGET_ELF_PATH}\\\" \\\"$ld_scripts\\\" $ld_defs --upload --github --target-name ${BOARD}/${TARGET} --api-key $ENV{MEMBROWSE_API_KEY}\"; \
else \
MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} \\\"${TARGET_ELF_PATH}\\\" \\\"$ld_scripts\\\" $ld_defs\"; \
fi; \
else \
if [ \"$MEMBROWSE_UPLOAD\" = \"1\" ]; then \
MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} --identical --upload --github --target-name ${BOARD}/${TARGET} --api-key $ENV{MEMBROWSE_API_KEY}\"; \
else \
MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} --identical\"; \
fi; \
fi; \
echo \"$MEMBROWSE_CMD\"")
add_custom_target(${TARGET}-membrowse
DEPENDS ${TARGET}
COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=0 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\""
VERBATIM
)
set_property(TARGET ${TARGET}-membrowse PROPERTY FOLDER ${TARGET})
add_custom_target(${TARGET}-membrowse-upload
COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=1 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\""
VERBATIM
)
if (NOT TARGET examples-membrowse-upload)
add_custom_target(examples-membrowse-upload)
endif ()
add_dependencies(examples-membrowse-upload ${TARGET}-membrowse-upload)
set_property(TARGET ${TARGET}-membrowse-upload PROPERTY FOLDER ${TARGET})
endif ()
endfunction()
#-------------------------------------------------------------
# Common Target Configure
# Most families use these settings except rp2040 and espressif
@ -380,6 +469,7 @@ function(family_configure_common TARGET RTOS)
# Analyze size with bloaty and linkermap
family_add_bloaty(${TARGET})
family_add_linkermap(${TARGET})
family_add_membrowse(${TARGET})
endif ()
# run size after build

3
hw/bsp/rp2040/family.cmake
View File

@ -250,9 +250,10 @@ function(family_configure_target TARGET RTOS)
family_flash_openocd(${TARGET})
family_flash_jlink(${TARGET})
# Generate linkermap target and post build. LINKERMAP_OPTION can be set with -D to change default options
# Generate linkermap target and post build. LINKERMAP_OPTION can be set with -D to change default options
family_add_bloaty(${TARGET})
family_add_linkermap(${TARGET})
family_add_membrowse(${TARGET})
endfunction()

8
hw/bsp/stm32f2/family.c
View File

@ -31,7 +31,6 @@
#include "stm32f2xx_hal.h"
#include "bsp/board_api.h"
#include "board.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
@ -105,9 +104,12 @@ void board_init(void) {
/* Enable USB FS Clocks */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
#if CFG_TUD_ENABLED
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = true;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
}
//--------------------------------------------------------------------+

10
hw/bsp/stm32f4/boards/feather_stm32f405/board.h
View File

@ -43,6 +43,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOC,
@ -106,14 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART3_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

10
hw/bsp/stm32f4/boards/pyboardv11/board.h
View File

@ -43,6 +43,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOB,
@ -106,14 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

11
hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
View File

@ -44,6 +44,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 0
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOC,
@ -107,15 +109,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
// Blackpill doesn't use VBUS sense (B device) explicitly disable it
if (rhport == 0) {
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

11
hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
View File

@ -44,6 +44,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 0
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOA,
@ -106,15 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Black F407VET6 doesn't use VBUS sense (B device) explicitly disable it
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

10
hw/bsp/stm32f4/boards/stm32f407disco/board.h
View File

@ -46,6 +46,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOD,
@ -114,14 +116,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

11
hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
View File

@ -43,6 +43,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 0
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOC,
@ -106,15 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
// Blackpill doesn't use VBUS sense (B device) explicitly disable it
if (rhport == 0) {
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

10
hw/bsp/stm32f4/boards/stm32f411disco/board.h
View File

@ -44,6 +44,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOD,
@ -111,14 +113,6 @@ static inline void board_clock_init(void) {
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
// Enable VBUS sense (B device) via pin PA9
if (rhport == 0) {
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

9
hw/bsp/stm32f4/boards/stm32f412disco/board.h
View File

@ -45,6 +45,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOE,
@ -127,13 +129,6 @@ static inline void board_clock_init(void) {
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

9
hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
View File

@ -45,6 +45,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOB,
@ -128,13 +130,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART3_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

10
hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
View File

@ -46,6 +46,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOB,
@ -117,14 +119,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART3_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

7
hw/bsp/stm32f4/family.c
View File

@ -180,11 +180,14 @@ void board_init(void) {
#endif
#if CFG_TUD_ENABLED
board_vbus_sense_init(BOARD_TUD_RHPORT);
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(BOARD_TUD_RHPORT, TUD_CFGID_DWC2, &cfg);
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, true);
board_vbus_set(BOARD_TUH_RHPORT, true);
#endif
}

2
hw/bsp/stm32f7/boards/stm32f723disco/board.h
View File

@ -41,7 +41,7 @@
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 1
#define PINID_LED 0
#define PINID_BUTTON 1

4
hw/bsp/stm32f7/boards/stm32f746disco/board.h
View File

@ -40,8 +40,8 @@
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 1
#define PINID_LED 0
#define PINID_BUTTON 1

36
hw/bsp/stm32f7/family.c
View File

@ -154,18 +154,14 @@ void board_init(void) {
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
//------------- rhport1: OTG_HS -------------//
#ifdef USB_HS_PHYC
// MCU with built-in HS PHY such as F723, F733, F730
@ -178,9 +174,6 @@ void board_init(void) {
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
// Enable HS VBUS sense (B device) via pin PB13
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
/* Configure OTG-HS ID pin */
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
@ -243,17 +236,16 @@ void board_init(void) {
__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
#if OTG_HS_VBUS_SENSE
#error OTG HS VBUS Sense enabled is not implemented
#else
// No VBUS sense
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
tud_configure(1, TUD_CFGID_DWC2, &cfg);
#endif
// Turn off device vbus
#if CFG_TUD_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
// Turn on host vbus
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUH_RHPORT, true);

2
hw/bsp/stm32h7/boards/stm32h743eval/board.h
View File

@ -44,7 +44,7 @@
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 1
// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
#define ULPI_PINS \

2
hw/bsp/stm32h7/boards/stm32h747disco/board.h
View File

@ -42,7 +42,7 @@
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 1
// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
#define ULPI_PINS \

42
hw/bsp/stm32h7/family.c
View File

@ -180,18 +180,14 @@ void board_init(void) {
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
//------------- USB HS -------------//
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
// Despite being call USB2_OTG
@ -216,28 +212,24 @@ void board_init(void) {
__HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE();
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
#if OTG_HS_VBUS_SENSE
#error OTG HS VBUS Sense enabled is not implemented
#else
// No VBUS sense
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif
// Force device mode
USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
tud_configure(1, TUD_CFGID_DWC2, &cfg);
#endif
#endif
HAL_PWREx_EnableUSBVoltageDetector();
board_init2(); // optional init
// Turn off device vbus
#if CFG_TUD_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
// Turn on host vbus
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUH_RHPORT, 1);
board_vbus_set(BOARD_TUH_RHPORT, true);
#endif
}

2
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
View File

@ -2,6 +2,8 @@ set(MCU_VARIANT stm32h7s3xx)
set(JLINK_DEVICE stm32h7s3l8)
set(LD_FILE_Clang ${LD_FILE_GNU})
set(RHPORT_DEVICE 1)
set(RHPORT_HOST 1)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC

2
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
View File

@ -44,7 +44,7 @@
#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define PINID_LED 0

51
hw/bsp/stm32h7rs/family.c
View File

@ -356,17 +356,14 @@ void board_init(void) {
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PM14
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device)
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
#endif
//------------- USB HS -------------//
@ -382,33 +379,31 @@ void board_init(void) {
#if OTG_HS_VBUS_SENSE
// Configure VBUS Pin
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PM9
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
GPIO_InitTypeDef GPIO_InitStruct2;
GPIO_InitStruct2.Pin = GPIO_PIN_8;
GPIO_InitStruct2.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct2.Pull = GPIO_NOPULL;
GPIO_InitStruct2.Alternate = GPIO_AF10_OTG_HS;
HAL_GPIO_Init(GPIOM, &GPIO_InitStruct2);
#endif
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
// B-peripheral session valid override enable
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
#else
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN;
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
tud_configure(1, TUD_CFGID_DWC2, &cfg);
#endif
#endif
#endif
board_init2();
// Turn off device vbus
#if CFG_TUD_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
// Turn on host vbus
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUH_RHPORT, 1);
board_vbus_set(BOARD_TUH_RHPORT, true);
#endif
}

2
hw/bsp/stm32h7rs/family.cmake
View File

@ -24,7 +24,7 @@ if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 1)
endif ()
if (NOT DEFINED RHPORT_HOST)
set(RHPORT_HOST 1)
set(RHPORT_HOST 0)
endif ()
if (NOT DEFINED RHPORT_SPEED)

11
hw/bsp/stm32l4/boards/stm32l476disco/board.h
View File

@ -51,6 +51,8 @@
#define UART_TX_PIN GPIO_PIN_5
#define UART_RX_PIN GPIO_PIN_6
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -128,15 +130,6 @@ static inline void board_clock_init(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
}
static inline void board_vbus_sense_init(void)
{
// L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
// Disable VBUS Sense and force device mode
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
}
#ifdef __cplusplus
}
#endif

8
hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
View File

@ -52,6 +52,8 @@
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 1
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -145,12 +147,6 @@ static inline void board_clock_init(void)
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
}
static inline void board_vbus_sense_init(void)
{
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
#ifdef __cplusplus
}
#endif

8
hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
View File

@ -51,6 +51,8 @@
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 1
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -129,12 +131,6 @@ static inline void board_clock_init(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
}
static inline void board_vbus_sense_init(void)
{
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
#ifdef __cplusplus
}
#endif

8
hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
View File

@ -51,6 +51,8 @@
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 1
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -129,12 +131,6 @@ static inline void board_clock_init(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
}
static inline void board_vbus_sense_init(void)
{
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
#ifdef __cplusplus
}
#endif

10
hw/bsp/stm32l4/family.c
View File

@ -170,10 +170,16 @@ void board_init(void) {
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
#endif
/* Enable USB FS Clocks */
#if defined(USB_OTG_FS)
/* Enable USB FS Clocks */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
board_vbus_sense_init();
#if CFG_TUD_ENABLED
/* Set Vbus sense */
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
#else
__HAL_RCC_USB_CLK_ENABLE();
#endif

2
hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
View File

@ -1,5 +1,5 @@
set(MCU_VARIANT stm32n657xx)
set(JLINK_DEVICE stm32n6xx)
set(JLINK_DEVICE stm32n657x0)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)

41
hw/bsp/stm32n6/boards/stm32n6570dk/board.h
View File

@ -44,17 +44,16 @@ extern "C" {
#define UART_DEV USART1
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
#define BOARD_TUD_RHPORT 1
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 1
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define PINID_LED 0
#define PINID_BUTTON 1
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define PINID_TCPP0203_EN 4
#define PINID_PWR_USB2 8
static board_pindef_t board_pindef[] = {
{// LED
@ -77,21 +76,22 @@ static board_pindef_t board_pindef[] = {
.port = GPIOA,
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
.active_state = 0},
{
// I2C SCL for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{ // I2C SCL for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// I2C SDA for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{// I2C SDA for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
{// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
},
{// PWR for USB2
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_9, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
}
};
//--------------------------------------------------------------------+
@ -262,9 +262,12 @@ static inline void board_init2(void) {
}
void board_vbus_set(uint8_t rhport, bool state) {
(void) state;
if (rhport == 1) {
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
if (rhport == 0) {
uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
} else if (rhport == 1) {
board_pindef_t *pindef = &board_pindef[PINID_PWR_USB2];
HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state ? GPIO_PIN_SET : GPIO_PIN_RESET);
}
}

9
hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
View File

@ -1,8 +1,15 @@
set(MCU_VARIANT stm32n657xx)
set(JLINK_DEVICE stm32n6xx)
set(JLINK_DEVICE stm32n657x0)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 0)
endif ()
if (NOT DEFINED RHPORT_HOST)
set(RHPORT_HOST 0)
endif ()
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
STM32N657xx

33
hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
View File

@ -44,11 +44,9 @@ extern "C" {
#define UART_DEV USART1
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
#define BOARD_TUD_RHPORT 1
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 1
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define PINID_LED 0
#define PINID_BUTTON 1
@ -77,20 +75,17 @@ static board_pindef_t board_pindef[] = {
.port = GPIOA,
.pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
.active_state = 0},
{
// I2C SCL for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{// I2C SCL for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// I2C SDA for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{// I2C SDA for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
{// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
},
};
@ -262,9 +257,9 @@ static inline void board_init2(void) {
}
void board_vbus_set(uint8_t rhport, bool state) {
(void) state;
if (rhport == 1) {
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
if (rhport == 0) {
uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
}
}

5
hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
View File

@ -1,9 +1,12 @@
MCU_VARIANT = stm32n657xx
CFLAGS += -DSTM32N657xx
JLINK_DEVICE = stm32n6xx
JLINK_DEVICE = stm32n657x0
LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
RHPORT_DEVICE ?= 0
RHPORT_HOST ?= 0
# flash target using on-board stlink
flash: flash-stlink

122
hw/bsp/stm32n6/family.c
View File

@ -48,7 +48,8 @@
TU_ATTR_UNUSED static void Error_Handler(void) { }
void HardFault_Handler(void);
static void MPU_Config(void);
static void SystemIsolation_Config(void);
typedef struct {
GPIO_TypeDef* port;
GPIO_InitTypeDef pin_init;
@ -87,20 +88,25 @@ static UART_HandleTypeDef UartHandle = {
// Despite being call USB2_OTG_FS on some MCUs
// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
void USB2_OTG_HS_IRQHandler(void) {
tusb_int_handler(0, true);
tusb_int_handler(1, true);
}
// Despite being call USB1_OTG_HS on some MCUs
// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
void USB1_OTG_HS_IRQHandler(void) {
tusb_int_handler(1, true);
tusb_int_handler(0, true);
}
void board_init(void) {
/* Enable BusFault and SecureFault handlers (HardFault is default) */
SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
MPU_Config();
SystemIsolation_Config();
SCB_EnableICache();
SCB_EnableDCache();
HAL_PWREx_EnableVddA();
HAL_PWREx_EnableVddIO2();
HAL_PWREx_EnableVddIO3();
@ -126,8 +132,6 @@ void board_init(void) {
__HAL_RCC_GPIOP_CLK_ENABLE();
__HAL_RCC_GPIOQ_CLK_ENABLE();
// HAL_ICACHE_Enable();
for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
}
@ -155,7 +159,7 @@ void board_init(void) {
HAL_UART_Init(&UartHandle);
#endif
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_EnableVddUSBVMEN();
@ -196,11 +200,109 @@ void board_init(void) {
/* Peripheral PHY clock enable */
__HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
board_init2();
#if CFG_TUH_ENABLED
#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0
board_vbus_set(BOARD_TUH_RHPORT, 1);
#endif
#endif
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
__HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_EnableVddUSBVMEN();
while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY));
HAL_PWREx_EnableVddUSB();
LL_AHB5_GRP1_ForceReset(0x00800000);
__HAL_RCC_USB2_OTG_HS_FORCE_RESET();
__HAL_RCC_USB2_OTG_HS_PHY_FORCE_RESET();
LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
LL_AHB5_GRP1_ReleaseReset(0x00800000);
/* Peripheral clock enable */
__HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
/* Required few clock cycles before accessing USB PHY Controller Registers */
for (volatile uint32_t i = 0; i < 10; i++) {
__NOP(); // No Operation instruction to create a delay
}
USB2_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
USB2_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
(0x2 << 4) |
(0x1 << 2) |
0x1U;
__HAL_RCC_USB2_OTG_HS_PHY_RELEASE_RESET();
/* Required few clock cycles before Releasing Reset */
for (volatile uint32_t i = 0; i < 10; i++) {
__NOP(); // No Operation instruction to create a delay
}
__HAL_RCC_USB2_OTG_HS_RELEASE_RESET();
/* Peripheral PHY clock enable */
__HAL_RCC_USB2_OTG_HS_PHY_CLK_ENABLE();
#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1
board_vbus_set(BOARD_TUH_RHPORT, 1);
#endif
#endif
board_init2();
}
static void MPU_Config(void)
{
MPU_Region_InitTypeDef default_config = {0};
MPU_Attributes_InitTypeDef attr_config = {0};
uint32_t primask_bit = __get_PRIMASK();
__disable_irq();
/* disable the MPU */
HAL_MPU_Disable();
/* create an attribute configuration for the MPU */
attr_config.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE);
attr_config.Number = MPU_ATTRIBUTES_NUMBER0;
HAL_MPU_ConfigMemoryAttributes(&attr_config);
/* Create a non cacheable region */
/*Normal memory type, code execution allowed */
default_config.Enable = MPU_REGION_ENABLE;
default_config.Number = MPU_REGION_NUMBER0;
default_config.BaseAddress = __NON_CACHEABLE_SECTION_BEGIN;
default_config.LimitAddress = __NON_CACHEABLE_SECTION_END;
default_config.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
default_config.AccessPermission = MPU_REGION_ALL_RW;
default_config.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
default_config.AttributesIndex = MPU_ATTRIBUTES_NUMBER0;
HAL_MPU_ConfigRegion(&default_config);
/* enable the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
/* Exit critical section to lock the system and avoid any issue around MPU mechanisme */
__set_PRIMASK(primask_bit);
}
static void SystemIsolation_Config(void) {
/* set all required IPs as secure privileged */
__HAL_RCC_RIFSC_CLK_ENABLE();
RIMC_MasterConfig_t RIMC_master = {0};
RIMC_master.MasterCID = RIF_CID_1;
RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
/*RIMC configuration*/
HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG1, &RIMC_master);
HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG2, &RIMC_master);
/*RISUP configuration*/
HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG1HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG2HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
}
//--------------------------------------------------------------------+

7
hw/bsp/stm32n6/family.cmake
View File

@ -21,7 +21,7 @@ set(FAMILY_MCUS STM32N6 CACHE INTERNAL "")
# Port & Speed Selection
# ----------------------
if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 1)
set(RHPORT_DEVICE 0)
endif ()
if (NOT DEFINED RHPORT_HOST)
set(RHPORT_HOST 1)
@ -68,6 +68,7 @@ function(family_add_board BOARD_TARGET)
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rif.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@ -80,8 +81,8 @@ function(family_add_board BOARD_TARGET)
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
BOARD_TUH_RHPORT=${RHPORT_HOST}
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
SEGGER_RTT_SECTION="noncacheable_buffer"
BUFFER_SIZE_UP=0x3000
SEGGER_RTT_SECTION=".noncacheable"
BUFFER_SIZE_UP=0x4000
)
update_board(${BOARD_TARGET})

6
hw/bsp/stm32n6/family.mk
View File

@ -12,7 +12,7 @@ CPU_CORE ?= cortex-m55
# ----------------------
# Port & Speed Selection
# ----------------------
RHPORT_DEVICE ?= 1
RHPORT_DEVICE ?= 0
RHPORT_HOST ?= 1
ifndef RHPORT_DEVICE_SPEED
@ -32,8 +32,8 @@ CFLAGS += \
-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
-DBUFFER_SIZE_UP=0x3000 \
-DSEGGER_RTT_SECTION="\".noncacheable\"" \
-DBUFFER_SIZE_UP=0x4000 \
# GCC Flags
CFLAGS_GCC += \

12
hw/bsp/stm32n6/setup_iar.mac Normal file
View File

@ -0,0 +1,12 @@
/* Called once after the target reset. */
execUserReset()
{
/* Re-load image as AIXRAM2 is erased after CPU reset */
__loadImage("$EXE_DIR$\\$TARGET_BNAME$.hex", 0, 0);
__restoreSoftwareBreakpoints();
#PC = __readMemory32(0x34180404, "Memory");
#SP = 0x341FFD00;
}

362
hw/bsp/stm32n6/stm32n6.jdebug Normal file
View File

@ -0,0 +1,362 @@
/*********************************************************************
* (c) SEGGER Microcontroller GmbH *
* The Embedded Experts *
* www.segger.com *
**********************************************************************
File :
Created : 31. Jan 2026 16:34
Ozone Version : V3.40e
*/
/*********************************************************************
*
* OnProjectLoad
*
* Function description
* Project load routine. Required.
*
**********************************************************************
*/
void OnProjectLoad (void) {
//
// Dialog-generated settings
//
Project.SetDevice ("STM32N657X0");
Project.SetHostIF ("USB", "");
Project.SetTargetIF ("SWD");
Project.SetTIFSpeed ("4 MHz");
Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M55F.svd");
//
// User settings
//
File.Open ("$(ProjectDir)/../../../examples/device/cdc_msc/build/stm32n6570dk/RelWithDebInfo/cdc_msc.elf");
}
/*********************************************************************
*
* OnStartupComplete
*
* Function description
* Called when program execution has reached/passed
* the startup completion point. Optional.
*
**********************************************************************
*/
//void OnStartupComplete (void) {
//}
/*********************************************************************
*
* TargetReset
*
* Function description
* Replaces the default target device reset routine. Optional.
*
* Notes
* This example demonstrates the usage when
* debugging an application in RAM on a Cortex-M target device.
*
**********************************************************************
*/
//void TargetReset (void) {
//
// unsigned int SP;
// unsigned int PC;
// unsigned int VectorTableAddr;
//
// VectorTableAddr = Elf.GetBaseAddr();
// //
// // Set up initial stack pointer
// //
// if (VectorTableAddr != 0xFFFFFFFF) {
// SP = Target.ReadU32(VectorTableAddr);
// Target.SetReg("SP", SP);
// }
// //
// // Set up entry point PC
// //
// PC = Elf.GetEntryPointPC();
//
// if (PC != 0xFFFFFFFF) {
// Target.SetReg("PC", PC);
// } else if (VectorTableAddr != 0xFFFFFFFF) {
// PC = Target.ReadU32(VectorTableAddr + 4);
// Target.SetReg("PC", PC);
// } else {
// Util.Error("Project file error: failed to set entry point PC", 1);
// }
//}
/*********************************************************************
*
* BeforeTargetReset
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetReset (void) {
//}
/*********************************************************************
*
* AfterTargetReset
*
* Function description
* Event handler routine. Optional.
* The default implementation initializes SP and PC to reset values.
**
**********************************************************************
*/
void AfterTargetReset (void) {
_SetupTarget();
}
/*********************************************************************
*
* DebugStart
*
* Function description
* Replaces the default debug session startup routine. Optional.
*
**********************************************************************
*/
//void DebugStart (void) {
//}
/*********************************************************************
*
* TargetConnect
*
* Function description
* Replaces the default target IF connection routine. Optional.
*
**********************************************************************
*/
//void TargetConnect (void) {
//}
/*********************************************************************
*
* BeforeTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetConnect (void) {
//}
/*********************************************************************
*
* AfterTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetConnect (void) {
//}
/*********************************************************************
*
* TargetDownload
*
* Function description
* Replaces the default program download routine. Optional.
*
**********************************************************************
*/
//void TargetDownload (void) {
//}
/*********************************************************************
*
* BeforeTargetDownload
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDownload (void) {
//}
/*********************************************************************
*
* AfterTargetDownload
*
* Function description
* Event handler routine. Optional.
* The default implementation initializes SP and PC to reset values.
*
**********************************************************************
*/
void AfterTargetDownload (void) {
//_SetupTarget();
}
/*********************************************************************
*
* BeforeTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetHalt
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetHalt (void) {
//}
/*********************************************************************
*
* BeforeTargetResume
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetResume (void) {
//}
/*********************************************************************
*
* OnSnapshotLoad
*
* Function description
* Called upon loading a snapshot. Optional.
*
* Additional information
* This function is used to restore the target state in cases
* where values cannot simply be written to the target.
* Typical use: GPIO clock needs to be enabled, before
* GPIO is configured.
*
**********************************************************************
*/
//void OnSnapshotLoad (void) {
//}
/*********************************************************************
*
* OnSnapshotSave
*
* Function description
* Called upon saving a snapshot. Optional.
*
* Additional information
* This function is usually used to save values of the target
* state which can either not be trivially read,
* or need to be restored in a specific way or order.
* Typically use: Memory Mapped Registers,
* such as PLL and GPIO configuration.
*
**********************************************************************
*/
//void OnSnapshotSave (void) {
//}
/*********************************************************************
*
* OnError
*
* Function description
* Called when an error occurred. Optional.
*
**********************************************************************
*/
//void OnError (void) {
//}
/*********************************************************************
*
* AfterProjectLoad
*
* Function description
* After Project load routine. Optional.
*
**********************************************************************
*/
//void AfterProjectLoad (void) {
//}
/*********************************************************************
*
* OnDebugStartBreakSymbolReached
*
* Function description
* Called when program execution has reached/passed
* the symbol to be breaked at during debug start. Optional.
*
**********************************************************************
*/
//void OnDebugStartBreakSymReached (void) {
//}
/*********************************************************************
*
* _SetupTarget
*
* Function description
* Setup the target.
* Called by AfterTargetReset() and AfterTargetDownload().
*
* Auto-generated function. May be overridden by Ozone.
*
**********************************************************************
*/
void _SetupTarget(void) {
unsigned int SP;
unsigned int PC;
unsigned int VectorTableAddr;
Debug.Download();
Debug.Halt();
VectorTableAddr = Elf.GetBaseAddr();
//
// Set up initial stack pointer
//
SP = Target.ReadU32(VectorTableAddr);
if (SP != 0xFFFFFFFF) {
Target.SetReg("SP", SP);
}
//
// Set up entry point PC
//
PC = Elf.GetEntryPointPC();
if (PC != 0xFFFFFFFF) {
Target.SetReg("PC", PC);
} else {
Util.Error("Project script error: failed to set up entry point PC", 1);
}
}

2
hw/bsp/stm32n6/stm32n6xx_hal_conf.h
View File

@ -67,7 +67,7 @@
/*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_PSSI_MODULE_ENABLED */
/*#define HAL_RAMCFG_MODULE_ENABLED */
/*#define HAL_RIF_MODULE_ENABLED */
#define HAL_RIF_MODULE_ENABLED
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */

5
hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
View File

@ -55,6 +55,8 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_9
#define UART_RX_PIN GPIO_PIN_10
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -110,6 +112,9 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
}
#ifdef __cplusplus
}
#endif

3
hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
View File

@ -110,6 +110,9 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
}
#ifdef __cplusplus
}
#endif

5
hw/bsp/stm32u5/boards/stm32u575eval/board.h
View File

@ -56,6 +56,8 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_9
#define UART_RX_PIN GPIO_PIN_10
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -111,6 +113,9 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
}
#ifdef __cplusplus
}
#endif

102
hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
View File

@ -37,6 +37,8 @@ extern "C"
{
#endif
#include "stm32u5xx_ll_tim.h"
// LED GREEN
#define LED_PORT GPIOC
#define LED_PIN GPIO_PIN_7
@ -55,6 +57,8 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -110,6 +114,104 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
/* ADC config */
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
__HAL_RCC_ADC12_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
ADC_HandleTypeDef hadc1;
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc1.Init.Resolution = ADC_RESOLUTION_14B;
hadc1.Init.GainCompensation = 0;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc1.Init.LowPowerAutoWait = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc1.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc1) != HAL_OK) {
Error_Handler();
}
ADC_ChannelConfTypeDef sConfig = {0};
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
Error_Handler();
}
HAL_NVIC_EnableIRQ(ADC1_IRQn);
/* TIM1 init for TRGO */
__HAL_RCC_TIM1_CLK_ENABLE();
TIM_HandleTypeDef htim1;
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
htim1.Instance = TIM1;
htim1.Init.Prescaler = 159;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 999;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
Error_Handler();
}
LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
HAL_ADC_Start_IT(&hadc1);
HAL_TIM_Base_Start(&htim1);
}
void ADC1_IRQHandler(void) {
if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
/* Clear flag ADC group regular end of unitary conversion */
LL_ADC_ClearFlag_EOC(ADC1);
/* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
* with R1 = 330kOhm and R2 = 50kOhm
*/
const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
if((ADC1->DR > threshold) && (USB_OTG_FS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
} else {
USB_OTG_FS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
}
}
if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
/* Clear flag ADC group regular overrun */
LL_ADC_ClearFlag_OVR(ADC1);
}
}
#ifdef __cplusplus
}
#endif

106
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
View File

@ -37,6 +37,8 @@ extern "C"
{
#endif
#include "stm32u5xx_ll_tim.h"
// LED GREEN
#define LED_PORT GPIOC
#define LED_PIN GPIO_PIN_7
@ -55,11 +57,13 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_9
#define UART_RX_PIN GPIO_PIN_10
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
static void SystemClock_Config(void) {
static inline void SystemClock_Config(void) {
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
@ -128,7 +132,7 @@ static void SystemClock_Config(void) {
}
}
static void SystemPower_Config(void) {
static inline void SystemPower_Config(void) {
HAL_PWREx_EnableVddIO2();
/*
@ -141,7 +145,105 @@ static void SystemPower_Config(void) {
/* USER CODE END PWR */
}
static inline void board_vbus_sense_init(void) {
/* ADC config */
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
__HAL_RCC_ADC12_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
ADC_HandleTypeDef hadc1;
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc1.Init.Resolution = ADC_RESOLUTION_14B;
hadc1.Init.GainCompensation = 0;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc1.Init.LowPowerAutoWait = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc1.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc1) != HAL_OK) {
Error_Handler();
}
ADC_ChannelConfTypeDef sConfig = {0};
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
Error_Handler();
}
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
/* TIM1 init for TRGO */
__HAL_RCC_TIM1_CLK_ENABLE();
TIM_HandleTypeDef htim1;
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
htim1.Instance = TIM1;
htim1.Init.Prescaler = 159;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 999;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
Error_Handler();
}
LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
HAL_ADC_Start_IT(&hadc1);
HAL_TIM_Base_Start(&htim1);
}
void ADC1_2_IRQHandler(void) {
if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
/* Clear flag ADC group regular end of unitary conversion */
LL_ADC_ClearFlag_EOC(ADC1);
/* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
* with R1 = 330kOhm and R2 = 50kOhm
*/
const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
if((ADC1->DR > threshold) && (USB_OTG_HS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
} else {
USB_OTG_HS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
}
}
if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
/* Clear flag ADC group regular overrun */
LL_ADC_ClearFlag_OVR(ADC1);
}
}
#ifdef __cplusplus
}
#endif

30
hw/bsp/stm32u5/family.c
View File

@ -179,18 +179,14 @@ void board_init(void) {
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
/* Enable USB power on Pwrctrl CR2 register */
HAL_PWREx_EnableVddUSB();
@ -218,13 +214,15 @@ void board_init(void) {
/*Configuring the SYSCFG registers OTG_HS PHY*/
HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
// Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
#if CFG_TUD_ENABLED
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
#endif // USB_OTG_FS
/* Non-standard VBus sense settings */
board_vbus_sense_init();
}
//--------------------------------------------------------------------+

5
hw/bsp/stm32u5/family.cmake
View File

@ -45,6 +45,9 @@ function(family_add_board BOARD_TARGET)
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@ -96,7 +99,7 @@ function(family_configure_example TARGET RTOS)
endif ()
if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes -Wno-self-assign")
endif ()
set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
SKIP_LINTING ON

7
hw/bsp/stm32u5/family.mk
View File

@ -16,6 +16,7 @@ CFLAGS_GCC += \
-Wno-error=undef \
-Wno-error=unused-parameter \
-Wno-error=type-limits \
-Wno-self-assign \
ifeq ($(TOOLCHAIN),gcc)
CFLAGS_GCC += -Wno-error=maybe-uninitialized
@ -35,11 +36,15 @@ SRC_C += \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c
ifneq ($(filter stm32u545xx stm32u535xx,$(MCU_VARIANT)),)
SRC_C += \
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c \
src/portable/st/stm32_fsdev/fsdev_common.c
else
SRC_C += \

4
hw/bsp/stm32u5/stm32u5xx_hal_conf.h
View File

@ -36,7 +36,7 @@
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_MDF_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CORDIC_MODULE_ENABLED */
@ -76,7 +76,7 @@
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
/*#define HAL_TSC_MODULE_ENABLED */
/*#define HAL_RAMCFG_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED

9
hw/bsp/stm32wba/family.c
View File

@ -172,14 +172,7 @@ void board_init(void) {
// Configuring the SYSCFG registers OTG_HS PHY
SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN;
// Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
#endif // USB_OTG_FS
#endif // USB_OTG_HS
}
void board_led_write(bool state) { HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); }

6
src/class/msc/msc_device.c
View File

@ -646,7 +646,11 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
break;
}
TU_ASSERT(prepare_cbw(p_msc));
if (!usbd_edpt_stalled(rhport, p_msc->ep_out)) {
TU_ASSERT(prepare_cbw(p_msc));
} else {
p_msc->stage = MSC_STAGE_CMD;
}
} else {
// Any xfer ended here is considered unknown error, ignore it
TU_LOG1(" Warning expect SCSI Status but received unknown data\r\n");

7
src/common/tusb_verify.h
View File

@ -73,8 +73,13 @@
#define TU_MESS_FAILED() do {} while (0)
#endif
// Custom defined application function
#ifdef CFG_TUSB_DEBUG_BREAKPOINT
extern void CFG_TUSB_DEBUG_BREAKPOINT(void);
#define TU_BREAKPOINT() CFG_TUSB_DEBUG_BREAKPOINT()
// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
#elif defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define TU_BREAKPOINT() do { \
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \

5
src/device/usbd.h
View File

@ -41,8 +41,13 @@ enum {
typedef struct {
uint16_t bm_double_buffered; // bitmap of IN endpoints to be double buffered, only effective for bulk endpoints
bool vbus_sensing; // Vbus pin is used for device connection detection, mandatory for tud_umount_cb()
} tud_configure_dwc2_t;
#ifndef CFG_TUD_CONFIGURE_DWC2_DEFAULT
#define CFG_TUD_CONFIGURE_DWC2_DEFAULT {.bm_double_buffered = 0, .vbus_sensing = CFG_TUD_VBUS_DETECT_HW}
#endif
typedef union {
tud_configure_dwc2_t dwc2;
} tud_configure_param_t;

6
src/host/usbh.c
View File

@ -1961,6 +1961,12 @@ static uint8_t enum_get_new_address(bool is_hub) {
}
}
#if CFG_TUH_HUB
if ( is_hub ) {
TU_LOG1("All addresses are occupied, try to increase CFG_TUH_HUB value.\r\n");
}
#endif // CFG_TUH_HUB
return 0; // invalid address
}

6
src/host/usbh.h
View File

@ -96,6 +96,7 @@ enum {
TUH_CFGID_RPI_PIO_USB_CONFIGURATION = 100, // cfg_param: pio_usb_configuration_t
TUH_CFGID_MAX3421 = 200,
TUH_CFGID_FSDEV = 300,
TUH_CFGID_DWC2 = 400
};
typedef struct {
@ -108,10 +109,15 @@ typedef struct {
uint8_t max_nak; // max NAK per endpoint per frame to save CPU usage (0=unlimited)
} tuh_configure_fsdev_t;
typedef struct {
bool use_hs_phy; // Always use high-speed ULPI/UTMI phy even when working at full-speed
} tuh_configure_dwc2_t;
typedef union {
// For TUH_CFGID_RPI_PIO_USB_CONFIGURATION use pio_usb_configuration_t
tuh_configure_max3421_t max3421;
tuh_configure_fsdev_t fsdev;
tuh_configure_dwc2_t dwc2;
} tuh_configure_param_t;
//--------------------------------------------------------------------+

26
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@ -77,9 +77,7 @@ CFG_TUD_MEM_SECTION static struct {
TUD_EPBUF_DEF(setup_packet, 8);
} _dcd_usbbuf;
static tud_configure_dwc2_t _tud_cfg = {
.bm_double_buffered = 0
};
static tud_configure_dwc2_t _tud_cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) {
#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
@ -444,14 +442,14 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
tu_memclr(&_dcd_data, sizeof(_dcd_data));
// Core Initialization
const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
const bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, TUD_OPT_HIGH_SPEED);
const bool is_dma = dma_device_enabled(dwc2);
TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
TU_ASSERT(dwc2_core_init(rhport, highspeed_phy, is_dma));
//------------- 7.1 Device Initialization -------------//
// Set device max speed
uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk;
if (is_highspeed) {
if (highspeed_phy) {
// dcfg Highspeed's mask is 0
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
@ -472,12 +470,15 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
// Force device mode
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
// Clear A override, force B Valid
dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
// OTG Ctrl
uint32_t gotgctl = dwc2->gotgctl & ~GOTGCTL_AVALOEN; // Clear A-override
if (!_tud_cfg.vbus_sensing) {
gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; // force B Valid if not sensing VBus
}
dwc2->gotgctl = gotgctl;
#if CFG_TUSB_MCU == OPT_MCU_STM32N6
// No hardware detection of Vbus B-session is available on the STM32N6
dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL;
#ifdef TUP_USBIP_DWC2_STM32
dwc2_stm32_gccfg_cfg(dwc2, _tud_cfg.vbus_sensing, false);
#endif
// Enable required interrupts
@ -780,7 +781,7 @@ static void handle_bus_reset(uint8_t rhport) {
dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
}
dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT | GINTMSK_IISOIXFRM;
dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_OEPINT | GINTMSK_IEPINT | GINTMSK_IISOIXFRM;
}
static void handle_enum_done(uint8_t rhport) {
@ -1180,6 +1181,7 @@ void dcd_int_handler(uint8_t rhport) {
const uint32_t otg_int = dwc2->gotgint;
if (otg_int & GOTGINT_SEDET) {
dwc2->gintmsk &= ~GINTMSK_OTGINT;
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
}

19
src/portable/synopsys/dwc2/dwc2_common.c
View File

@ -179,18 +179,17 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
//--------------------------------------------------------------------
//
//--------------------------------------------------------------------
bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
(void)dwc2;
#if CFG_TUD_ENABLED
if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
return false;
bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy) {
#ifdef TUP_USBIP_DWC2_STM32
if (dwc2->guid >= 0x5000) {
// femtoPHY UTMI+ PHY
return true;
}
#endif
#if CFG_TUH_ENABLED
if (role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) {
if (!prefer_hs_phy) {
return false;
}
#endif
const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
return ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
@ -204,7 +203,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
* In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz
*
*/
bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
bool dwc2_core_init(uint8_t rhport, bool highspeed_phy, bool is_dma) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
// Check Synopsys ID register, failed if controller clock/power is not enabled
@ -213,7 +212,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
// disable global interrupt
dwc2->gahbcfg &= ~GAHBCFG_GINT;
if (is_highspeed) {
if (highspeed_phy) {
phy_hs_init(dwc2);
} else {
phy_fs_init(dwc2);

4
src/portable/synopsys/dwc2/dwc2_common.h
View File

@ -84,8 +84,8 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base;
}
bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role);
bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma);
bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy);
bool dwc2_core_init(uint8_t rhport, bool highspeed_phy, bool is_dma);
void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr);
//--------------------------------------------------------------------+

116
src/portable/synopsys/dwc2/dwc2_info.md
View File

@ -1,58 +1,58 @@
| | AT32 F405 FS | AT32 F405 HS | AT32 F415 | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | nRF54 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 |
|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------|
| GUID | 0x00002000 | 0x00000000 | 0x00001000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 |
| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54430A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 |
| - specs version | 4.00a | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 4.30a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W |
| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0xAA555000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DCD00 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x228BFC72 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 |
| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP |
| - arch | Slave only | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only |
| - single_point | hub | hub | hub | hub | hub | n/a | hub | n/a | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub |
| - hs_phy_type | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a | UTMI+/ULPI | UTMI+ | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a |
| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | n/a | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a |
| - num_dev_ep | 7 | 7 | 3 | 7 | 6 | 6 | 15 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
| - num_host_ch | 15 | 15 | 7 | 7 | 13 | 7 | 15 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 |
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - nptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 |
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x020004E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x0BEAC0E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 |
| - xfer_size_width | 8 | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 |
| - packet_size_width | 6 | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 |
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
| - optional_feature_removed | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| - dfifo_depth | 512 | 1008 | 512 | 4080 | 498 | 200 | 896 | 3050 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 |
| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x0000000F | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x1E10AA60 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 |
| - num_dev_period_in_ep | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - partial_powerdown | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - ahb_freq_min | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit |
| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - iddg_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - vbus_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - a_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - b_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - session_end_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - dedicated_fifos | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - num_dev_in_eps | 7 | 7 | 0 | 7 | 6 | 4 | 7 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| | AT32 F405 FS | AT32 F405 HS | AT32 F415 | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | nRF54 | ST F407/429 HS | ST F207/F407/411/429 FS | ST L476 FS | ST F412/76x FS | ST F76x HS | ST H743/H750 | ST F723/L4P5 FS | ST F723 HS | ST H7RS FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 |
|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:-----------------|:--------------------------|:-------------|:-----------------|:-------------|:---------------|:------------------|:-------------|:-------------|:---------------------|:-------------|:------------|
| GUID | 0x00002000 | 0x00000000 | 0x00001000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00002000 | 0x00002100 | 0x00002300 | 0x00003000 | 0x00003100 | 0x00004000 | 0x00005000 | 0x00AEC000 | 0x00001000 |
| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54430A | 0x4F54281A | 0x4F54281A | 0x4F54310A | 0x4F54320A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54411A | 0x4F54411A | 0x4F54292A | 0x00000000 |
| - specs version | 4.00a | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 4.30a | 2.81a | 2.81a | 3.10a | 3.20a | 3.20a | 3.30a | 3.30a | 3.30a | 4.11a | 4.11a | 2.92a | 0.00W |
| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0xAA555000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DCD00 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x228BFC72 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229ED520 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x229FE1D0 | 0x229ED522 | 0x228FE052 | 0x228F5930 | 0x00000000 |
| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | noHNP noSRP | HNP SRP | HNP SRP |
| - arch | Slave only | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | Slave only | Slave only | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | DMA internal | Slave only |
| - single_point | hub | hub | hub | hub | hub | n/a | hub | n/a | hub | n/a | n/a | n/a | hub | hub | n/a | hub | n/a | hub | n/a | hub |
| - hs_phy_type | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a | UTMI+/ULPI | UTMI+ | ULPI | n/a | n/a | n/a | ULPI | ULPI | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a |
| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | n/a | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a |
| - num_dev_ep | 7 | 7 | 3 | 7 | 6 | 6 | 15 | 15 | 5 | 3 | 5 | 5 | 8 | 8 | 5 | 8 | 5 | 8 | 6 | 0 |
| - num_host_ch | 15 | 15 | 7 | 7 | 13 | 7 | 15 | 15 | 11 | 7 | 11 | 11 | 15 | 15 | 11 | 15 | 11 | 15 | 13 | 0 |
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - nptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 |
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x020004E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x0BEAC0E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03EED2E8 | 0x020081E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 |
| - xfer_size_width | 8 | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 |
| - packet_size_width | 6 | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 |
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| - optional_feature_removed | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| - dfifo_depth | 512 | 1008 | 512 | 4080 | 498 | 200 | 896 | 3050 | 1012 | 512 | 512 | 512 | 1006 | 952 | 512 | 1006 | 512 | 952 | 634 | 0 |
| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x0000000F | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x1E10AA60 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0x23F00030 | 0x1610B230 | 0xE2103E30 | 0xDBF08030 | 0x00000000 |
| - num_dev_period_in_ep | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - partial_powerdown | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - ahb_freq_min | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit |
| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - iddg_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - vbus_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - a_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - b_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - session_end_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - dedicated_fifos | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - num_dev_in_eps | 7 | 7 | 0 | 7 | 6 | 4 | 7 | 7 | 5 | 3 | 5 | 5 | 8 | 8 | 5 | 8 | 5 | 8 | 6 | 0 |
| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |

10
src/portable/synopsys/dwc2/dwc2_info.py
View File

@ -16,14 +16,16 @@ dwc2_reg_value = {
'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030],
'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030],
'nRF54': [0, 0x4F54430A, 0xAA555000, 0x228BFC72, 0x0BEAC0E8, 0x1E10AA60],
'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
# ST sort by GUID
'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030],
'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030],
'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
'ST H7RS FS': [0x4000, 0x4F54411A, 0, 0x229ED522, 0x20081E8, 0x1610B230],
'ST U5A5/H7RS/N6 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030],
'GD32VF103': [0x1000, 0, 0, 0, 0, 0],

74
src/portable/synopsys/dwc2/dwc2_stm32.h
View File

@ -85,8 +85,11 @@ extern "C" {
#define EP_MAX_HS 9
#define EP_FIFO_SIZE_HS 4096
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_BASE
#define OTG_HS_IRQn USB1_OTG_HS_IRQn
#define USB_OTG_FS_PERIPH_BASE USB1_OTG_HS_BASE
#define OTG_FS_IRQn USB1_OTG_HS_IRQn
#define USB_OTG_HS_PERIPH_BASE USB2_OTG_HS_BASE
#define OTG_HS_IRQn USB2_OTG_HS_IRQn
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
#include "stm32f7xx.h"
@ -300,6 +303,66 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
}
}
//------------- GCCFG configuration -------------//
static inline void dwc2_stm32_gccfg_cfg(dwc2_regs_t* dwc2, bool vbus_sensing, bool is_host) {
if (is_host) {
vbus_sensing = false;
}
uint32_t gccfg = dwc2->stm32_gccfg;
if (dwc2->guid < 0x2000) {
// use VBUSASEN/VBUSBSEN/NOVBUSSENS bits
if (is_host) {
gccfg &= ~(STM32_GCCFG_NOVBUSSENS | STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
} else {
if (vbus_sensing) {
gccfg &= ~STM32_GCCFG_NOVBUSSENS;
gccfg |= STM32_GCCFG_VBUSBSEN;
} else {
gccfg |= STM32_GCCFG_NOVBUSSENS;
gccfg &= ~(STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
}
}
} else if (dwc2->guid < 0x5000) {
// the later version uses VBDEN with battery charging detection
if (vbus_sensing) {
gccfg |= STM32_GCCFG_VBDEN;
} else {
gccfg &= ~STM32_GCCFG_VBDEN;
}
} else {
// from 0x5000 ST seems to use femtoPHY for UTMI+ HS PHY. Which use VBVALEXTOEN and VBVALOVAL for software override
// external VBUS sensing
// Note: N6 does not support hardware VBUS sensing, so the software override is always active. Therefore, VBDEN and
// VBVALEXTOEN are not available
#if CFG_TUSB_MCU == OPT_MCU_STM32N6
if (is_host) {
gccfg |= STM32_GCCFG_PULLDOWNEN;
gccfg &= ~(STM32_GCCFG_VBVALOVAL);
} else {
gccfg &= ~STM32_GCCFG_PULLDOWNEN;
gccfg |= STM32_GCCFG_VBVALOVAL;
}
#else
if (is_host) {
gccfg |= STM32_GCCFG_PULLDOWNEN;
gccfg &= ~(STM32_GCCFG_VBDEN | STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
} else {
gccfg &= ~STM32_GCCFG_PULLDOWNEN;
if (vbus_sensing) {
gccfg |= STM32_GCCFG_VBDEN;
gccfg &= ~(STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
} else {
gccfg &= ~STM32_GCCFG_VBDEN;
gccfg |= STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL;
}
}
#endif
}
dwc2->stm32_gccfg = gccfg;
}
//------------- DCache -------------//
#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
@ -321,8 +384,13 @@ static mem_region_t uncached_regions[] = {
// DTCM (although USB DMA can't transfer to/from DTCM)
{.start = 0x20000000, .end = 0x2002FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
// DTCM
// DTCM
{.start = 0x20000000, .end = 0x2000FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32N6
// DTCM NS
{.start = 0x20000000, .end = 0x2003FFFF},
// DTCM S
{.start = 0x30000000, .end = 0x3003FFFF},
#else
#error "Cache maintenance is not supported yet"
#endif

42
src/portable/synopsys/dwc2/dwc2_type.h
View File

@ -1650,24 +1650,38 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000
#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable
// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
//#define STM32_GCCFG_SDEN_Pos (22U)
//#define STM32_GCCFG_SDEN_Msk (0x1U << STM32_GCCFG_SDEN_Pos) // 0x00400000
//#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (PD) mode enable
// GUID < 0x2000: VBUSASEN, VBUSBSEN, NOVBUSSENS bits
#define STM32_GCCFG_VBUSASEN_Pos (18U)
#define STM32_GCCFG_VBUSASEN_Msk (0x1UL << STM32_GCCFG_VBUSASEN_Pos) // 0x00040000
#define STM32_GCCFG_VBUSASEN STM32_GCCFG_VBUSASEN_Msk // Enable A-device (host) VBUS sensing
// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
#define STM32_GCCFG_VBVALOVAL_Pos (23U)
#define STM32_GCCFG_VBVALOVAL_Msk (0x1U << STM32_GCCFG_VBVALOVAL_Pos) // 0x00800000
#define STM32_GCCFG_VBVALOVAL STM32_GCCFG_VBVALOVAL_Msk // Value of VBUSVLDEXT0 femtoPHY input
#define STM32_GCCFG_VBUSBSEN_Pos (19U)
#define STM32_GCCFG_VBUSBSEN_Msk (0x1UL << STM32_GCCFG_VBUSBSEN_Pos) // 0x00080000
#define STM32_GCCFG_VBUSBSEN STM32_GCCFG_VBUSBSEN_Msk // Enable B-device (peripheral) VBUS sensing
#define STM32_GCCFG_VBVALEXTOEN_Pos (24U)
#define STM32_GCCFG_VBVALEXTOEN_Msk (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos) // 0x01000000
#define STM32_GCCFG_VBVALEXTOEN STM32_GCCFG_VBVALEXTOEN_Msk // Enables of VBUSVLDEXT0 femtoPHY input override
#define STM32_GCCFG_NOVBUSSENS_Pos (21U)
#define STM32_GCCFG_NOVBUSSENS_Msk (0x1UL << STM32_GCCFG_NOVBUSSENS_Pos) // 0x00200000
#define STM32_GCCFG_NOVBUSSENS STM32_GCCFG_NOVBUSSENS_Msk // VBUS sensing disable option
// GUID < 0x2000: end
#define STM32_GCCFG_PULLDOWNEN_Pos (25U)
#define STM32_GCCFG_PULLDOWNEN_Msk (0x1U << STM32_GCCFG_PULLDOWNEN_Pos) // 0x02000000
#define STM32_GCCFG_PULLDOWNEN STM32_GCCFG_PULLDOWNEN_Msk // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
// TODO: stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
// #define STM32_GCCFG_SDEN_Pos (22U)
// #define STM32_GCCFG_SDEN_Msk (0x1U << STM32_GCCFG_SDEN_Pos) // 0x00400000
// #define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (PD) mode enable
// GUID >= 0x5000 use femtoPHY: VBVALOVA, VBVALEXTOEN, PULLDOWNEN
#define STM32_GCCFG_VBVALOVAL_Pos (23U)
#define STM32_GCCFG_VBVALOVAL_Msk (0x1U << STM32_GCCFG_VBVALOVAL_Pos) // 0x00800000
#define STM32_GCCFG_VBVALOVAL STM32_GCCFG_VBVALOVAL_Msk // Value of VBUSVLDEXT0 femtoPHY input
#define STM32_GCCFG_VBVALEXTOEN_Pos (24U)
#define STM32_GCCFG_VBVALEXTOEN_Msk (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos) // 0x01000000
#define STM32_GCCFG_VBVALEXTOEN STM32_GCCFG_VBVALEXTOEN_Msk // Enables of VBUSVLDEXT0 femtoPHY input override
#define STM32_GCCFG_PULLDOWNEN_Pos (25U)
#define STM32_GCCFG_PULLDOWNEN_Msk (0x1U << STM32_GCCFG_PULLDOWNEN_Pos) // 0x02000000
#define STM32_GCCFG_PULLDOWNEN STM32_GCCFG_PULLDOWNEN_Msk // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
// GUID >= 0x5000: end
/******************** Bit definition for DEACHINTMSK register ********************/
#define DEACHINTMSK_IEP1INTM_Pos (1U)

39
src/portable/synopsys/dwc2/hcd_dwc2.c
View File

@ -111,7 +111,9 @@ typedef struct {
hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX];
} hcd_data_t;
hcd_data_t _hcd_data;
static hcd_data_t _hcd_data;
static tuh_configure_dwc2_t _tuh_cfg = {.use_hs_phy = TUH_OPT_HIGH_SPEED};
//--------------------------------------------------------------------
//
@ -364,9 +366,9 @@ static void dfifo_host_init(uint8_t rhport) {
// fixed allocation for now, improve later:
// - ptx_largest is limited to 256 for FS since most FS core only has 1024 bytes total
bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
uint32_t nptx_largest = is_highspeed ? TUSB_EPSIZE_BULK_HS/4 : TUSB_EPSIZE_BULK_FS/4;
uint32_t ptx_largest = is_highspeed ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4;
bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, _tuh_cfg.use_hs_phy);
uint32_t nptx_largest = highspeed_phy ? TUSB_EPSIZE_BULK_HS/4 : TUSB_EPSIZE_BULK_FS/4;
uint32_t ptx_largest = highspeed_phy ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4;
uint16_t nptxfsiz = 2 * nptx_largest;
uint16_t rxfsiz = 2 * (ptx_largest + 2) + ghwcfg2.num_host_ch;
@ -392,29 +394,25 @@ static void dfifo_host_init(uint8_t rhport) {
// optional hcd configuration, called by tuh_configure()
bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
(void) rhport;
(void) cfg_id;
(void) cfg_param;
TU_VERIFY(cfg_id == TUH_CFGID_DWC2 && cfg_param != NULL);
tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
_tuh_cfg = cfg->dwc2;
return true;
}
// Initialize controller to host mode
bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rh_init;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
tu_memclr(&_hcd_data, sizeof(_hcd_data));
// Core Initialization
const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
const bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, _tuh_cfg.use_hs_phy);
const bool is_dma = dma_host_enabled(dwc2);
TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
TU_ASSERT(dwc2_core_init(rhport, highspeed_phy, is_dma));
//------------- 3.1 Host Initialization -------------//
// work at max supported speed
dwc2->hcfg &= ~HCFG_FSLS_ONLY;
// Enable HFIR reload
if (dwc2->gsnpsid >= DWC2_CORE_REV_2_92a) {
dwc2->hfir |= HFIR_RELOAD_CTRL;
@ -428,6 +426,21 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
#endif
while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {}
#ifdef TUP_USBIP_DWC2_STM32
dwc2_stm32_gccfg_cfg(dwc2, false, true);
#endif
if (rh_init->speed < TUSB_SPEED_HIGH || !TUH_OPT_HIGH_SPEED) {
// disable high speed mode
dwc2->hcfg |= HCFG_FSLS_ONLY;
}
#if TUH_OPT_HIGH_SPEED
else {
// work at max supported speed
dwc2->hcfg &= ~HCFG_FSLS_ONLY;
}
#endif
// configure fixed-allocated fifo scheme
dfifo_host_init(rhport);

11
src/tusb_option.h
View File

@ -579,9 +579,18 @@
#define CFG_TUD_TEST_MODE 0
#endif
#ifndef CFG_TUD_VBUS_DETECT_HW_DEFAULT
#define CFG_TUD_VBUS_DETECT_HW_DEFAULT 0
#endif
// Enable VBUS Detect hardware, usually via functional GPIO
#ifndef CFG_TUD_VBUS_DETECT_HW
#define CFG_TUD_VBUS_DETECT_HW CFG_TUD_VBUS_DETECT_HW_DEFAULT
#endif
//------------- Device Class Driver -------------//
#ifndef CFG_TUD_BTH
#define CFG_TUD_BTH 0
#define CFG_TUD_BTH 0
#endif
#if CFG_TUD_BTH && !defined(CFG_TUD_BTH_ISO_ALT_COUNT)

60
tools/build.py
View File

@ -24,7 +24,6 @@ build_separator = '-' * 95
build_status = [STATUS_OK, STATUS_FAILED, STATUS_SKIPPED]
verbose = False
clean_build = False
parallel_jobs = os.cpu_count()
# CI board control lists (used when running under CI)
@ -98,15 +97,15 @@ def get_examples(family):
return all_examples
def print_build_result(board, example, status, duration):
def print_build_result(board, build_target, status, duration):
if isinstance(duration, (int, float)):
duration = "{:.2f}s".format(duration)
print(build_format.format(board, example, build_status[status], duration))
print(build_format.format(board, build_target, build_status[status], duration))
# -----------------------------
# CMake
# -----------------------------
def cmake_board(board, build_args, build_flags_on):
def cmake_board(board, build_args, build_flags_on, build_targets):
ret = [0, 0, 0]
start_time = time.monotonic()
@ -135,39 +134,36 @@ def cmake_board(board, build_args, build_flags_on):
f'-DBOARD={board}', '-DCMAKE_BUILD_TYPE=MinSizeRel', '-DLINKERMAP_OPTION=-q -f tinyusb/src',
*build_args, *build_flags])
if rcmd.returncode == 0:
if clean_build:
run_cmd(["cmake", "--build", build_dir, '--target', 'clean'])
cmd = ["cmake", "--build", build_dir, '--parallel', str(parallel_jobs)]
rcmd = run_cmd(cmd)
if rcmd.returncode == 0:
ret[0] += 1
run_cmd(["cmake", "--build", build_dir, '--target', 'tinyusb_metrics'])
# print(rcmd.stdout.decode("utf-8"))
else:
ret[1] += 1
for target in build_targets:
rcmd = run_cmd(cmd + ['--target', target])
if rcmd.returncode != 0:
break
ret[0 if rcmd.returncode == 0 else 1] += 1
example = 'all'
print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
print_build_result(board, ','.join(build_targets), 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
return ret
# -----------------------------
# Make
# -----------------------------
def make_one_example(example, board, make_option):
def make_one_example(example, board, make_option, build_targets):
# Check if board is skipped
if build_utils.skip_example(example, board):
print_build_result(board, example, 2, '-')
r = 2
else:
start_time = time.monotonic()
make_args = ["make", "-C", f"examples/{example}", f"BOARD={board}", '-j', str(parallel_jobs)]
make_cmd = ["make", "-C", f"examples/{example}", f"BOARD={board}", '-j', str(parallel_jobs)]
if make_option:
make_args += shlex.split(make_option)
if clean_build:
run_cmd(make_args + ["clean"])
build_result = run_cmd(make_args + ['all'])
r = 0 if build_result.returncode == 0 else 1
make_cmd += shlex.split(make_option)
r = 0
for target in build_targets:
build_result = run_cmd(make_cmd + [target])
if build_result.returncode != 0:
r = 1
break
print_build_result(board, example, r, time.monotonic() - start_time)
ret = [0, 0, 0]
@ -175,7 +171,7 @@ def make_one_example(example, board, make_option):
return ret
def make_board(board, build_args):
def make_board(board, build_args, build_targets):
print(build_separator)
family = find_family(board);
all_examples = get_examples(family)
@ -186,7 +182,7 @@ def make_board(board, build_args):
final_status = 2
else:
with Pool(processes=os.cpu_count()) as pool:
pool_args = list((map(lambda e, b=board, o=f"{build_args}": [e, b, o], all_examples)))
pool_args = list((map(lambda e, b=board, o=f"{build_args}", t=build_targets: [e, b, o, t], all_examples)))
r = pool.starmap(make_one_example, pool_args)
# sum all element of same index (column sum)
ret = list(map(sum, list(zip(*r))))
@ -198,16 +194,16 @@ def make_board(board, build_args):
# -----------------------------
# Build Family
# -----------------------------
def build_boards_list(boards, build_defines, build_system, build_flags_on):
def build_boards_list(boards, build_defines, build_system, build_flags_on, build_targets):
ret = [0, 0, 0]
for b in boards:
r = [0, 0, 0]
if build_system == 'cmake':
build_args = [f'-D{d}' for d in build_defines]
r = cmake_board(b, build_args, build_flags_on)
r = cmake_board(b, build_args, build_flags_on, build_targets)
elif build_system == 'make':
build_args = ' '.join(f'{d}' for d in build_defines)
r = make_board(b, build_args)
r = make_board(b, build_args, build_targets)
ret[0] += r[0]
ret[1] += r[1]
ret[2] += r[2]
@ -257,13 +253,11 @@ def get_family_boards(family, one_random, one_first):
# -----------------------------
def main():
global verbose
global clean_build
global parallel_jobs
parser = argparse.ArgumentParser()
parser.add_argument('families', nargs='*', default=[], help='Families to build')
parser.add_argument('-b', '--board', action='append', default=[], help='Boards to build')
parser.add_argument('-c', '--clean', action='store_true', default=False, help='Clean before build')
parser.add_argument('-t', '--toolchain', default='gcc', help='Toolchain to use, default is gcc')
parser.add_argument('-s', '--build-system', default='cmake', help='Build system to use, default is cmake')
parser.add_argument('-D', '--define-symbol', action='append', default=[], help='Define to pass to build system')
@ -273,6 +267,8 @@ def main():
parser.add_argument('--one-first', action='store_true', default=False,
help='Build only the first board (alphabetical) of each specified family')
parser.add_argument('-j', '--jobs', type=int, default=os.cpu_count(), help='Number of jobs to run in parallel')
parser.add_argument('-T', '--target', action='append', default=[],
help='Build target to use, may be specified multiple times (default: all)')
parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output')
args = parser.parse_args()
@ -284,8 +280,8 @@ def main():
build_flags_on = args.build_flags_on
one_random = args.one_random
one_first = args.one_first
build_targets = args.target if args.target else ['all']
verbose = args.verbose
clean_build = args.clean
parallel_jobs = args.jobs
build_defines.append(f'TOOLCHAIN={toolchain}')
@ -295,7 +291,7 @@ def main():
return 1
print(build_separator)
print(build_format.format('Board', 'Example', '\033[39mResult\033[0m', 'Time'))
print(build_format.format('Board', 'Target', '\033[39mResult\033[0m', 'Time'))
total_time = time.monotonic()
# get all families
@ -314,7 +310,7 @@ def main():
all_boards.extend(get_family_boards(f, one_random, one_first))
# build all boards
result = build_boards_list(all_boards, build_defines, build_system, build_flags_on)
result = build_boards_list(all_boards, build_defines, build_system, build_flags_on, build_targets)
total_time = time.monotonic() - total_time
print(build_separator)

6
tools/get_deps.py
View File

@ -45,7 +45,7 @@ deps_optional = {
'xmc4000'],
'hw/mcu/microchip': ['https://github.com/hathach/microchip_driver.git',
'9e8b37e307d8404033bb881623a113931e1edf27',
'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg'],
'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x samd2x_l2x samg'],
'hw/mcu/mindmotion/mm32sdk': ['https://github.com/hathach/mm32sdk.git',
'b93e856211060ae825216c6a1d6aa347ec758843',
'mm32'],
@ -252,11 +252,11 @@ deps_optional = {
'hpmicro'],
'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
'2b7495b8535bdcb306dac29b9ded4cfb679d7e5c',
'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x mm32 msp432e4 nrf saml2x '
'imxrt kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x mm32 msp432e4 nrf samd2x_l2x '
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 '
'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 '
'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u0 stm32u5 stm32wb stm32wba '
'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg '
'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x samd2x_l2x samg '
'tm4c '],
'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git',
'6f0a58d01aa9bd2feba212097f9afe7acd991d52',