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portable/chipidea: configure LPC USB0 AHB bursts

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This commit is contained in:
Zixun LI
2026-07-27 14:39:02 +02:00
parent 2d56dc533e
commit a2f4786865
3 changed files with 22 additions and 0 deletions
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14
src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
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@ -34,4 +34,18 @@ static const ci_hs_controller_t _ci_controller[] =
#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
enum {
CI_HS_LPC18_43_SBUSCFG_OFFSET = 0x90u,
CI_HS_LPC18_43_AHBBRST_INCR16_UNSPEC = 0x07u,
};
TU_ATTR_ALWAYS_INLINE static inline void ci_hs_lpc18_43_set_ahb_burst(uint8_t rhport) {
// USB0 SBUSCFG is at offset 0x90. NXP recommends AHBBRST=0x7:
// INCR16 with non-multiple transfers decomposed into smaller unspecified bursts.
if (rhport == 0) {
volatile uint32_t *sbuscfg = (volatile uint32_t *)(_ci_controller[rhport].reg_base + CI_HS_LPC18_43_SBUSCFG_OFFSET);
*sbuscfg = CI_HS_LPC18_43_AHBBRST_INCR16_UNSPEC;
}
}
#endif

4
src/portable/chipidea/ci_hs/dcd_ci_hs.c
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@ -237,6 +237,10 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
usbmode |= USBMODE_CM_DEVICE;
dcd_reg->USBMODE = usbmode;
#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
ci_hs_lpc18_43_set_ahb_burst(rhport);
#endif
#ifdef CFG_TUD_CI_HS_VBUS_CHARGE
dcd_reg->OTGSC = OTGSC_VBUS_CHARGE | OTGSC_OTG_TERMINATION;
#else

4
src/portable/chipidea/ci_hs/hcd_ci_hs.c
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@ -82,6 +82,10 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
hcd_reg->USBMODE = USBMODE_CM_HOST;
#endif
#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
ci_hs_lpc18_43_set_ahb_burst(rhport);
#endif
#if !TUH_OPT_HIGH_SPEED
hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
#endif