mirror of
https://github.com/hathach/tinyusb.git
synced 2026-02-05 11:15:44 +00:00
bsp: nxp: add support for RW612 (FRDM-RW612)
- Added `rw61x` family support. - Added `frdm_rw612` board support. - Update `get_deps.py` to include mcux-sdk for RW61x. - Add ci_hs_rw61x include to ChipIdea HS driver and enable host examples.
This commit is contained in:
gab-k
@ -8,6 +8,7 @@ mcu:LPC43XX
|
||||
mcu:MIMXRT1XXX
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||||
mcu:MIMXRT10XX
|
||||
mcu:MIMXRT11XX
|
||||
mcu:RW61X
|
||||
mcu:RP2040
|
||||
mcu:MSP432E4
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||||
mcu:RX65X
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||||
|
||||
@ -8,6 +8,7 @@ mcu:LPC43XX
|
||||
mcu:MIMXRT1XXX
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||||
mcu:MIMXRT10XX
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||||
mcu:MIMXRT11XX
|
||||
mcu:RW61X
|
||||
mcu:RP2040
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||||
mcu:MSP432E4
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||||
mcu:RX65X
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||||
|
||||
@ -6,6 +6,7 @@ mcu:LPC43XX
|
||||
mcu:MIMXRT1XXX
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||||
mcu:MIMXRT10XX
|
||||
mcu:MIMXRT11XX
|
||||
mcu:RW61X
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||||
mcu:MSP432E4
|
||||
mcu:RX65X
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||||
mcu:MAX3421
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||||
|
||||
@ -9,6 +9,7 @@ mcu:MAX3421
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||||
mcu:MIMXRT1XXX
|
||||
mcu:MIMXRT10XX
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||||
mcu:MIMXRT11XX
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||||
mcu:RW61X
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||||
mcu:MSP432E4
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||||
mcu:RP2040
|
||||
mcu:RX65X
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||||
|
||||
@ -8,6 +8,7 @@ mcu:LPC43XX
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||||
mcu:MIMXRT1XXX
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||||
mcu:MIMXRT10XX
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||||
mcu:MIMXRT11XX
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||||
mcu:RW61X
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||||
mcu:RP2040
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||||
mcu:MSP432E4
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||||
mcu:RX65X
|
||||
|
||||
@ -12,6 +12,7 @@ mcu:MAX3421
|
||||
mcu:MIMXRT1XXX
|
||||
mcu:MIMXRT10XX
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||||
mcu:MIMXRT11XX
|
||||
mcu:RW61X
|
||||
mcu:MSP432E4
|
||||
mcu:RP2040
|
||||
mcu:RX65X
|
||||
|
||||
@ -8,6 +8,7 @@ mcu:LPC43XX
|
||||
mcu:MIMXRT1XXX
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||||
mcu:MIMXRT10XX
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||||
mcu:MIMXRT11XX
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||||
mcu:RW61X
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mcu:RP2040
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mcu:MSP432E4
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mcu:RX65X
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||||
|
||||
150
hw/bsp/rw61x/FreeRTOSConfig/FreeRTOSConfig.h
Normal file
150
hw/bsp/rw61x/FreeRTOSConfig/FreeRTOSConfig.h
Normal file
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.0
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software. If you wish to use our Amazon
|
||||
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
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||||
|
||||
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||||
#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
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||||
* See http://www.freertos.org/a00110.html.
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||||
*----------------------------------------------------------*/
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||||
|
||||
// skip if included from IAR assembler
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||||
#ifndef __IASMARM__
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#include "fsl_device_registers.h"
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||||
#endif
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||||
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||||
/* Cortex M23/M33 port configuration. */
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#define configENABLE_MPU 0
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#define configENABLE_FPU 0 // RW61x has FPU but is disabled due to using cortex-m33-nodsp-nofp.mk
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#define configENABLE_TRUSTZONE 0
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#define configRUN_FREERTOS_SECURE_ONLY 1 // Cortex-M33 runs in secure mode after reset by default!
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#define configMINIMAL_SECURE_STACK_SIZE (1024)
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||||
|
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#define configUSE_PREEMPTION 1
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||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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||||
#define configCPU_CLOCK_HZ SystemCoreClock
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#define configTICK_RATE_HZ ( 1000 )
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#define configMAX_PRIORITIES ( 5 )
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#define configMINIMAL_STACK_SIZE ( 128 )
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#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
|
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#define configMAX_TASK_NAME_LEN 16
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#define configUSE_16_BIT_TICKS 0
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||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_MUTEXES 1
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||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
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||||
#define configQUEUE_REGISTRY_SIZE 4
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||||
#define configUSE_QUEUE_SETS 0
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#define configUSE_TIME_SLICING 0
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#define configUSE_NEWLIB_REENTRANT 0
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#define configENABLE_BACKWARD_COMPATIBILITY 1
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#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
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#define configSUPPORT_STATIC_ALLOCATION 1
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#define configSUPPORT_DYNAMIC_ALLOCATION 0
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||||
|
||||
/* Hook function related definitions. */
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#define configUSE_IDLE_HOOK 0
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||||
#define configUSE_TICK_HOOK 0
|
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#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
#define configCHECK_HANDLER_INSTALLATION 0
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||||
|
||||
/* Run time and task stats gathering related definitions. */
|
||||
#define configGENERATE_RUN_TIME_STATS 0
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||||
#define configRECORD_STACK_HIGH_ADDRESS 1
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||||
#define configUSE_TRACE_FACILITY 1 // legacy trace
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||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
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||||
|
||||
/* Co-routine definitions. */
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||||
#define configUSE_CO_ROUTINES 0
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||||
#define configMAX_CO_ROUTINE_PRIORITIES 2
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||||
|
||||
/* Software timer related definitions. */
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#define configUSE_TIMERS 1
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#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
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#define configTIMER_QUEUE_LENGTH 32
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#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
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|
||||
/* Optional functions - most linkers will remove unused functions anyway. */
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#define INCLUDE_vTaskPrioritySet 0
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#define INCLUDE_uxTaskPriorityGet 0
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#define INCLUDE_vTaskDelete 0
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||||
#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
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||||
#define INCLUDE_xResumeFromISR 0
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#define INCLUDE_vTaskDelayUntil 1
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||||
#define INCLUDE_vTaskDelay 1
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#define INCLUDE_xTaskGetSchedulerState 0
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#define INCLUDE_xTaskGetCurrentTaskHandle 1
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#define INCLUDE_uxTaskGetStackHighWaterMark 0
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||||
#define INCLUDE_xTaskGetIdleTaskHandle 0
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#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
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||||
#define INCLUDE_pcTaskGetTaskName 0
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||||
#define INCLUDE_eTaskGetState 0
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||||
#define INCLUDE_xEventGroupSetBitFromISR 0
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||||
#define INCLUDE_xTimerPendFunctionCall 0
|
||||
|
||||
/* FreeRTOS hooks to NVIC vectors */
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
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||||
#define vPortSVCHandler SVC_Handler
|
||||
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||||
//--------------------------------------------------------------------+
|
||||
// Interrupt nesting behavior configuration.
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||||
//--------------------------------------------------------------------+
|
||||
|
||||
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
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#define configPRIO_BITS 3
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||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
|
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#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
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routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
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PRIORITY THAN THIS! (higher priorities are lower numeric values. */
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#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
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|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
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to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
#endif
|
||||
30
hw/bsp/rw61x/boards/frdm_rw612/board.cmake
Normal file
30
hw/bsp/rw61x/boards/frdm_rw612/board.cmake
Normal file
@ -0,0 +1,30 @@
|
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set(MCU_VARIANT RW612)
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set(MCU_CORE RW612)
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|
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set(JLINK_DEVICE ${MCU_VARIANT})
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set(PYOCD_TARGET rw612eta2i)
|
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|
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set(BOARD_DIR ${SDK_DIR}/boards/frdmrw612)
|
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|
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set(PORT 1)
|
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|
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|
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function(update_board BOARD_TARGET)
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target_compile_definitions(${BOARD_TARGET} PUBLIC
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CPU_RW612ETA2I
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BOARD_TUD_RHPORT=${PORT}
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BOARD_TUH_RHPORT=${PORT}
|
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BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
|
||||
BOOT_HEADER_ENABLE=1
|
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)
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||||
|
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target_sources(${BOARD_TARGET} PUBLIC
|
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${BOARD_DIR}/flash_config/flash_config.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
|
||||
)
|
||||
|
||||
target_include_directories(${BOARD_TARGET} PUBLIC
|
||||
${BOARD_DIR}/flash_config
|
||||
)
|
||||
endfunction()
|
||||
76
hw/bsp/rw61x/boards/frdm_rw612/board.h
Normal file
76
hw/bsp/rw61x/boards/frdm_rw612/board.h
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021, Ha Thach (tinyusb.org)
|
||||
* Copyright (c) 2025, Gabriel Koppenstein
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: FRDM-RW612
|
||||
url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-RW612
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
// LED - Green channel of RGB LED
|
||||
#define LED_GPIO BOARD_INITLEDPINS_LED_GREEN_PERIPHERAL
|
||||
#define LED_CLK kCLOCK_HsGpio0
|
||||
#define LED_PIN BOARD_INITLEDPINS_LED_GREEN_PIN
|
||||
#define LED_PORT BOARD_INITLEDPINS_LED_GREEN_PORT
|
||||
#define LED_STATE_ON 0
|
||||
|
||||
// WAKE button (Dummy, use unused pin
|
||||
#define BUTTON_GPIO BOARD_INITPINS_WAKEUP_BTN_PERIPHERAL
|
||||
#define BUTTON_CLK kCLOCK_HsGpio0
|
||||
#define BUTTON_PIN BOARD_INITPINS_WAKEUP_BTN_PIN
|
||||
#define BUTTON_PORT BOARD_INITPINS_WAKEUP_BTN_PORT
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
// UART
|
||||
#define UART_DEV USART3
|
||||
#define LP_FLEXCOMM_INST 3U
|
||||
|
||||
#define BOARD_DEBUG_UART_FRG_CLK \
|
||||
(&(const clock_frg_clk_config_t){3, kCLOCK_FrgPllDiv, 255, 0}) /*!< Select FRG3 mux as frg_pll */
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH kFRG_to_FLEXCOMM3
|
||||
|
||||
|
||||
static inline void board_uart_init_clock(void) {
|
||||
/* attach FRG0 clock to FLEXCOMM3/USART3 */
|
||||
CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
20
hw/bsp/rw61x/boards/frdm_rw612/board.mk
Normal file
20
hw/bsp/rw61x/boards/frdm_rw612/board.mk
Normal file
@ -0,0 +1,20 @@
|
||||
MCU_VARIANT = RW612
|
||||
MCU_CORE = RW612
|
||||
|
||||
CPU_CORE = cortex-m33-nodsp-nofp
|
||||
CFLAGS += \
|
||||
-DCPU_RW612ETA2I \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_RW61X \
|
||||
-DBOOT_HEADER_ENABLE=1 \
|
||||
|
||||
JLINK_DEVICE = ${MCU_VARIANT}
|
||||
PYOCD_TARGET = rw612eta2i
|
||||
|
||||
SRC_C += \
|
||||
$(SDK_DIR)/boards/frdmrw612/flash_config/flash_config.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(SDK_DIR)/boards/frdmrw612/flash_config/ \
|
||||
|
||||
# flash using pyocd
|
||||
flash: flash-jlink
|
||||
170
hw/bsp/rw61x/boards/frdm_rw612/clock_config.c
Normal file
170
hw/bsp/rw61x/boards/frdm_rw612/clock_config.c
Normal file
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* Copyright 2024,2025 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
/*
|
||||
* How to set up clock using clock driver functions:
|
||||
*
|
||||
* 1. Setup clock sources.
|
||||
*
|
||||
* 2. Set up all selectors to provide selected clocks.
|
||||
*
|
||||
* 3. Set up all dividers.
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v15.0
|
||||
processor: RW612
|
||||
package_id: RW612ETA2I
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 24.12.10
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_power.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: audio_pll_clk.outFreq, value: 4246732800/345600007 MHz}
|
||||
- {id: aux0_pll_clk.outFreq, value: 260 MHz}
|
||||
- {id: avpll_ch1_clkout.outFreq, value: 4246732800/345600007 MHz}
|
||||
- {id: avpll_ch2_clkout.outFreq, value: 1415577600/22118401 MHz}
|
||||
- {id: cau_slp_clk.outFreq, value: 4 MHz}
|
||||
- {id: clk_32k.outFreq, value: 32 kHz}
|
||||
- {id: clk_pmu_sys.outFreq, value: 52 MHz}
|
||||
- {id: els_128m_clk.outFreq, value: 128 MHz}
|
||||
- {id: els_256m_clk.outFreq, value: 256 MHz}
|
||||
- {id: els_64m_clk.outFreq, value: 64 MHz}
|
||||
- {id: ffro_clk_div4.outFreq, value: 640/53 MHz}
|
||||
- {id: hclk.outFreq, value: 260 MHz}
|
||||
- {id: lposc_clk_i.outFreq, value: 1 MHz}
|
||||
- {id: main_clk.outFreq, value: 260 MHz}
|
||||
- {id: main_pll_clk.outFreq, value: 260 MHz}
|
||||
- {id: otp_fuse_32m_clk.outFreq, value: 32 MHz}
|
||||
- {id: refclk_phy.outFreq, value: 40 MHz}
|
||||
- {id: sfro_clk_i.outFreq, value: 16 MHz}
|
||||
- {id: systick_fclk.outFreq, value: 260 MHz}
|
||||
- {id: t3pll_mci_256m.outFreq, value: 256 MHz}
|
||||
- {id: t3pll_mci_48_60m_irc.outFreq, value: 2560/53 MHz}
|
||||
- {id: tcpu_mci_clk.outFreq, value: 260 MHz}
|
||||
- {id: tddr_mci_flexspi_clk.outFreq, value: 320 MHz}
|
||||
settings:
|
||||
- {id: CLKCTL0.MAINCLKSELB.sel, value: CLKCTL0.MAINPLLCLKDIV}
|
||||
- {id: CLKCTL0.MAINPLLCLKDIV.scale, value: '1', locked: true}
|
||||
- {id: CLKCTL0.PMUFCLKDIV.scale, value: '5', locked: true}
|
||||
- {id: CLKCTL0.SYSCPUAHBCLKDIV.scale, value: '1', locked: true}
|
||||
- {id: CLKCTL0.SYSTICKFCLKSEL.sel, value: CLKCTL0.SYSTICKFCLKDIV}
|
||||
- {id: CLKCTL0.WDT0FCLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: CLKCTL1.FRGPLLCLKDIV.scale, value: '13', locked: true}
|
||||
- {id: CLKCTL1.OSEVENTFCLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: REFCLK_SYS_Config, value: Disabled}
|
||||
- {id: SYSCTL2.CH1_M.scale, value: '2621440', locked: true}
|
||||
- {id: SYSCTL2.CH1_OFFSET_DIV.scale, value: '345600007', locked: true}
|
||||
- {id: SYSCTL2.CH2_M.scale, value: '2621440', locked: true}
|
||||
- {id: SYSCTL2.CH2_OFFSET_DIV.scale, value: '66355203', locked: true}
|
||||
- {id: SYSCTL2.T3_FBDIV.scale, value: '64', locked: true}
|
||||
- {id: SYSCTL2.T3_REFDIV.scale, value: '1', locked: true}
|
||||
- {id: T3PLL_MCI_213P3M_Config, value: Disabled}
|
||||
- {id: T3PLL_MCI_FLEXSPI_Config, value: Disabled}
|
||||
- {id: TCPU_MCI_FLEXSPI_CLK_Config, value: Disabled}
|
||||
- {id: TDDR_MCI_ENET_CLK_Config, value: Disabled}
|
||||
sources:
|
||||
- {id: CAU.XTAL_OSC.outFreq, value: 40 MHz, enabled: true}
|
||||
- {id: PMU.XTAL32K.outFreq, value: 32.768 kHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.ch1Freq = kCLOCK_AvPllChFreq12p288m, /* AVPLL channel frequency 12.288 MHz */
|
||||
.ch2Freq = kCLOCK_AvPllChFreq64m, /* AVPLL channel frequency 64 MHz */
|
||||
.enableCali = true, /* AVPLL calibration is enabled */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Disable GDET and VSensors */
|
||||
POWER_DisableGDetVSensors();
|
||||
/* Enable CAU sleep clock for PMU */
|
||||
if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U)
|
||||
{
|
||||
/* Enable the CAU sleep clock. */
|
||||
CLOCK_EnableClock(kCLOCK_RefClkCauSlp);
|
||||
}
|
||||
if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U)
|
||||
{
|
||||
/* Enable the REFCLK_SYS clock. */
|
||||
CLOCK_EnableClock(kCLOCK_RefClkSys);
|
||||
}
|
||||
/* Initialize T3 PLL and enable outputs that are not clock gated. */
|
||||
CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m);
|
||||
/* Enable FFRO - T3 PLL 48/60 MHz IRC clock output */
|
||||
CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk);
|
||||
/* Enable T3 PLL 256 MHz clock output */
|
||||
CLOCK_EnableClock(kCLOCK_T3PllMci256mClk);
|
||||
/* Set core clock to safe system oscillator clock for initialization of other sources. */
|
||||
CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK);
|
||||
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1);
|
||||
/* Enable TCPU PLL MCI clock output */
|
||||
CLOCK_EnableClock(kCLOCK_TcpuMciClk);
|
||||
/* Initialize TDDR PLL and enable outputs that are not clock gated. */
|
||||
CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10);
|
||||
/* Enable TDDR PLL FlexSPI clock output */
|
||||
CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk);
|
||||
/* Initialize AVPLL and enable both channels. */
|
||||
CLOCK_InitAvPll(&avpllConfig_BOARD_BootClockRUN);
|
||||
/* Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kRC32K_to_CLK32K); /* Switch CLK32K to RC32K */
|
||||
/*!< Please note SYSTICK_CLK source is used only if the SysTick SYST_CSR register CLKSOURCE bit is set to 0. */
|
||||
CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK); /* Switch SYSTICK_CLK to SYSTICK_DIV */
|
||||
/* Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); /* Set .AUDIOPLLCLKDIV divider to value 1 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); /* Set .FRGPLLCLKDIV divider to value 13 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); /* Set .MAINPLLCLKDIV divider to value 1 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); /* Set .AUX0PLLCLKDIV divider to value 1 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U); /* Set .SYSTICKFCLKDIV divider to value 1 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U); /* Set .PMUFCLKDIV divider to value 5 */
|
||||
/* Select the main clock source for the main system clock (MAINCLKSELA and MAINCLKSELB). */
|
||||
CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK);
|
||||
/*!< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_HCLK;
|
||||
}
|
||||
|
||||
116
hw/bsp/rw61x/boards/frdm_rw612/clock_config.h
Normal file
116
hw/bsp/rw61x/boards/frdm_rw612/clock_config.h
Normal file
@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_AUDIO_PLL_CLK 12287999UL /* Clock consumers of audio_pll_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_AUX0_PLL_CLK 260000000UL /* Clock consumers of aux0_pll_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_AUX1_PLL_CLK 0UL /* Clock consumers of aux1_pll_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_AVPLL_CH1_CLKOUT 12287999UL /* Clock consumers of avpll_ch1_clkout output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_AVPLL_CH2_CLKOUT 63999997UL /* Clock consumers of avpll_ch2_clkout output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CAU_SLP_CLK 4000000UL /* Clock consumers of cau_slp_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_32K 32000UL /* Clock consumers of clk_32k output : RTC */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_OUT 0UL /* Clock consumers of clk_out output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_PMU_SYS 52000000UL /* Clock consumers of clk_pmu_sys output : PMU */
|
||||
#define BOARD_BOOTCLOCKRUN_CTIMER0_FCLK 0UL /* Clock consumers of ctimer0_fclk output : CTIMER0 */
|
||||
#define BOARD_BOOTCLOCKRUN_CTIMER1_FCLK 0UL /* Clock consumers of ctimer1_fclk output : CTIMER1 */
|
||||
#define BOARD_BOOTCLOCKRUN_CTIMER2_FCLK 0UL /* Clock consumers of ctimer2_fclk output : CTIMER2 */
|
||||
#define BOARD_BOOTCLOCKRUN_CTIMER3_FCLK 0UL /* Clock consumers of ctimer3_fclk output : CTIMER3 */
|
||||
#define BOARD_BOOTCLOCKRUN_DMIC_FCLK 0UL /* Clock consumers of dmic_fclk output : DMIC0 */
|
||||
#define BOARD_BOOTCLOCKRUN_ELS_128M_CLK 128000000UL /* Clock consumers of els_128m_clk output : ELS */
|
||||
#define BOARD_BOOTCLOCKRUN_ELS_256M_CLK 256000000UL /* Clock consumers of els_256m_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ELS_64M_CLK 64000000UL /* Clock consumers of els_64m_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ELS_FCLK 0UL /* Clock consumers of els_fclk output : ELS */
|
||||
#define BOARD_BOOTCLOCKRUN_FFRO_CLK_DIV4 12075471UL /* Clock consumers of ffro_clk_div4 output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXCOMM0_FCLK 0UL /* Clock consumers of flexcomm0_fclk output : FLEXCOMM0 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXCOMM14_FCLK 0UL /* Clock consumers of flexcomm14_fclk output : FLEXCOMM14 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXCOMM1_FCLK 0UL /* Clock consumers of flexcomm1_fclk output : FLEXCOMM1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXCOMM2_FCLK 0UL /* Clock consumers of flexcomm2_fclk output : FLEXCOMM2 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXCOMM3_FCLK 0UL /* Clock consumers of flexcomm3_fclk output : FLEXCOMM3 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_FCLK 0UL /* Clock consumers of flexspi_fclk output : FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKRUN_GAU_FCLK 0UL /* Clock consumers of gau_fclk output : GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_HCLK 260000000UL /* Clock consumers of hclk output : AHB_SECURE_CTRL, APU0, APU1, BLEAPU, BLECTRL, BUCK11, BUCK18, CACHE64_CTRL0, CACHE64_CTRL1, CACHE64_POLSEL0, CACHE64_POLSEL1, CAU, CDOG, CLKCTL0, CLKCTL1, CRC, CTIMER0, CTIMER1, CTIMER2, CTIMER3, DMA0, DMA1, DMIC0, ELS, ENET, FLEXCOMM0, FLEXCOMM1, FLEXCOMM14, FLEXCOMM2, FLEXCOMM3, FLEXSPI, FREQME, GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1, GDMA, GPIO, INPUTMUX, ITRC, LCDIC, MCI_IO_MUX, MRT0, MRT1, OCOTP, OSTIMER, PINT, PKC, PMU, POWERQUAD, PUF, ROMCP, RSTCTL0, RSTCTL1, RTC, SCT0, SDU_FBR_CARD, SDU_FN0_CARD, SDU_FN_CARD, SECGPIO, SENSOR_CTRL, SOCCTRL, SOC_OTP_CTRL, SYSCTL0, SYSCTL1, SYSCTL2, SysTick, TRNG, USBOTG, USIM, UTICK, WLAPU, WLCTRL, WWDT0 */
|
||||
#define BOARD_BOOTCLOCKRUN_LCD_FCLK 0UL /* Clock consumers of lcd_fclk output : LCDIC */
|
||||
#define BOARD_BOOTCLOCKRUN_LPOSC_CLK_I 1000000UL /* Clock consumers of lposc_clk_i output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_MAIN_CLK 260000000UL /* Clock consumers of main_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_MAIN_PLL_CLK 260000000UL /* Clock consumers of main_pll_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_MCLK_OUT 0UL /* Clock consumers of mclk_out output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_OSEVENT_FCLK 0UL /* Clock consumers of osevent_fclk output : OSTIMER */
|
||||
#define BOARD_BOOTCLOCKRUN_OTP_FUSE_32M_CLK 32000000UL /* Clock consumers of otp_fuse_32m_clk output : OCOTP */
|
||||
#define BOARD_BOOTCLOCKRUN_REFCLK_PHY 40000000UL /* Clock consumers of refclk_phy output : USBOTG */
|
||||
#define BOARD_BOOTCLOCKRUN_REFCLK_SYS 0UL /* Clock consumers of refclk_sys output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SCT_FCLK 0UL /* Clock consumers of sct_fclk output : SCT0 */
|
||||
#define BOARD_BOOTCLOCKRUN_SFRO_CLK_I 16000000UL /* Clock consumers of sfro_clk_i output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYSOSC_CLK_I 0UL /* Clock consumers of sysosc_clk_i output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYSTICK_FCLK 260000000UL /* Clock consumers of systick_fclk output : SysTick */
|
||||
#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_213P3M 0UL /* Clock consumers of t3pll_mci_213p3m output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_256M 256000000UL /* Clock consumers of t3pll_mci_256m output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_48_60M_IRC 48301886UL /* Clock consumers of t3pll_mci_48_60m_irc output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_FLEXSPI_CLK 0UL /* Clock consumers of t3pll_mci_flexspi_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TCPU_MCI_CLK 260000000UL /* Clock consumers of tcpu_mci_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TCPU_MCI_FLEXSPI_CLK 0UL /* Clock consumers of tcpu_mci_flexspi_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TDDR_MCI_ENET_CLK 0UL /* Clock consumers of tddr_mci_enet_clk output : ENET */
|
||||
#define BOARD_BOOTCLOCKRUN_TDDR_MCI_FLEXSPI_CLK 320000000UL /* Clock consumers of tddr_mci_flexspi_clk output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_USIM_FCLK 0UL /* Clock consumers of usim_fclk output : USIM */
|
||||
#define BOARD_BOOTCLOCKRUN_UTICK_FCLK 0UL /* Clock consumers of utick_fclk output : UTICK */
|
||||
#define BOARD_BOOTCLOCKRUN_WDT0_FCLK 0UL /* Clock consumers of wdt0_fclk output : WWDT0 */
|
||||
|
||||
/*! @brief AVPLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN;
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
223
hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c
Normal file
223
hw/bsp/rw61x/boards/frdm_rw612/pin_mux.c
Normal file
@ -0,0 +1,223 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v17.0
|
||||
processor: RW612
|
||||
package_id: RW612ETA2I
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 25.09.10
|
||||
board: FRDM-RW612
|
||||
pin_labels:
|
||||
- {pin_num: M2, pin_signal: GPIO_11, label: 'J1[6]/WAKEUP_BTN', identifier: WAKEUP;WAKEUP_BTN}
|
||||
- {pin_num: L7, pin_signal: GPIO_5, label: 'J1[7]/MCLK', identifier: MCLKOUT}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_io_mux.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitPins();
|
||||
BOARD_InitDEBUG_UARTPins();
|
||||
BOARD_InitSWD_DEBUGPins();
|
||||
BOARD_InitLEDPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: M2, peripheral: GPIO, signal: 'PIO0, 11', pin_signal: GPIO_11, identifier: WAKEUP_BTN, direction: INPUT}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description :
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 */
|
||||
void BOARD_InitPins(void)
|
||||
{
|
||||
/* Enables the clock for the GPIO0 module */
|
||||
GPIO_PortInit(GPIO, 0);
|
||||
|
||||
gpio_pin_config_t WAKEUP_BTN_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_11 (pin M2) */
|
||||
GPIO_PinInit(BOARD_INITPINS_WAKEUP_BTN_GPIO, BOARD_INITPINS_WAKEUP_BTN_PORT, BOARD_INITPINS_WAKEUP_BTN_PIN, &WAKEUP_BTN_config);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitDEBUG_UARTPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: E5, peripheral: FLEXCOMM3, signal: USART_RXD, pin_signal: GPIO_24}
|
||||
- {pin_num: F6, peripheral: FLEXCOMM3, signal: USART_TXD, pin_signal: GPIO_26}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitDEBUG_UARTPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 */
|
||||
void BOARD_InitDEBUG_UARTPins(void)
|
||||
{
|
||||
/* Initialize FC3_USART_DATA functionality on pin GPIO_24, GPIO_26 (pin E5_F6) */
|
||||
IO_MUX_SetPinMux(IO_MUX_FC3_USART_DATA);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSWD_DEBUGPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: G5, peripheral: SWD, signal: CLK, pin_signal: GPIO_13}
|
||||
- {pin_num: K4, peripheral: SWD, signal: IO, pin_signal: GPIO_14}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSWD_DEBUGPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 */
|
||||
void BOARD_InitSWD_DEBUGPins(void)
|
||||
{
|
||||
|
||||
MCI_IO_MUX->C_TIMER_IN = ((MCI_IO_MUX->C_TIMER_IN &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL_MASK | MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL_MASK)))
|
||||
|
||||
/* sel GPIO-13 as ct_inp3: 0x00u */
|
||||
| MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL(0x00u)
|
||||
/* sel GPIO-14 as ct_inp4: 0x00u */
|
||||
| MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL(0x00u));
|
||||
|
||||
MCI_IO_MUX->C_TIMER_OUT = ((MCI_IO_MUX->C_TIMER_OUT &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL_MASK | MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL_MASK)))
|
||||
|
||||
/* sel GPIO-13 as ct0mat3: 0x00u */
|
||||
| MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL(0x00u)
|
||||
/* sel GPIO-14 as ct1mat0: 0x00u */
|
||||
| MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL(0x00u));
|
||||
|
||||
MCI_IO_MUX->FC2 =
|
||||
((MCI_IO_MUX->FC2 &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(MCI_IO_MUX_FC2_SEL_FC2_I2C_MASK | MCI_IO_MUX_FC2_SEL_FC2_I2S_MASK | MCI_IO_MUX_FC2_SEL_FC2_SPI_MASK | MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY_MASK | MCI_IO_MUX_FC2_SEL_FC2_USART_DATA_MASK)))
|
||||
|
||||
/* flexcomm2:select GPIO-13/14 as i2c function: 0x00u */
|
||||
| MCI_IO_MUX_FC2_SEL_FC2_I2C(0x00u)
|
||||
/* flexcomm2:select GPIO-13/14/15 as i2s function: 0x00u */
|
||||
| MCI_IO_MUX_FC2_SEL_FC2_I2S(0x00u)
|
||||
/* flexcomm2:select GPIO-13/14/15/16 as spi function: 0x00u */
|
||||
| MCI_IO_MUX_FC2_SEL_FC2_SPI(0x00u)
|
||||
/* flexcomm2:select GPIO-13 as i2s data function: 0x00u */
|
||||
| MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY(0x00u)
|
||||
/* flexcomm2:select GPIO-13/14 as usart rxd/txd: 0x00u */
|
||||
| MCI_IO_MUX_FC2_SEL_FC2_USART_DATA(0x00u));
|
||||
|
||||
MCI_IO_MUX->GPIO_GRP0 = ((MCI_IO_MUX->GPIO_GRP0 &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(MCI_IO_MUX_GPIO_GRP0_SEL_13_MASK | MCI_IO_MUX_GPIO_GRP0_SEL_14_MASK)))
|
||||
|
||||
/* pio0[31:0] selection, high valid; sel[i]->pio0[i]->GPIO[i]: 0x00u */
|
||||
| MCI_IO_MUX_GPIO_GRP0_SEL(0x00u));
|
||||
|
||||
SOCCTRL->MCI_IOMUX_EN0 = ((SOCCTRL->MCI_IOMUX_EN0 &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(SOCCIU_MCI_IOMUX_EN0_EN_21_0_13_MASK | SOCCIU_MCI_IOMUX_EN0_EN_21_0_14_MASK)))
|
||||
|
||||
/* Bitwise enable control for mci_io_mux GPIO[21:0]: 0x00u */
|
||||
| SOCCIU_MCI_IOMUX_EN0_EN_21_0(0x00u));
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitLEDPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: M1, peripheral: GPIO, signal: 'PIO0, 0', pin_signal: GPIO_0, direction: OUTPUT, gpio_init_state: 'true'}
|
||||
- {pin_num: N2, peripheral: GPIO, signal: 'PIO0, 1', pin_signal: GPIO_1, direction: OUTPUT, gpio_init_state: 'true'}
|
||||
- {pin_num: N8, peripheral: GPIO, signal: 'PIO0, 12', pin_signal: GPIO_12, direction: OUTPUT, gpio_init_state: 'true'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitLEDPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 */
|
||||
void BOARD_InitLEDPins(void)
|
||||
{
|
||||
/* Enables the clock for the GPIO0 module */
|
||||
CLOCK_EnableClock(kCLOCK_HsGpio0);
|
||||
|
||||
gpio_pin_config_t LED_BLUE_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_0 (pin M1) */
|
||||
GPIO_PinInit(BOARD_INITLEDPINS_LED_BLUE_GPIO, BOARD_INITLEDPINS_LED_BLUE_PORT, BOARD_INITLEDPINS_LED_BLUE_PIN, &LED_BLUE_config);
|
||||
|
||||
gpio_pin_config_t LED_RED_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_1 (pin N2) */
|
||||
GPIO_PinInit(BOARD_INITLEDPINS_LED_RED_GPIO, BOARD_INITLEDPINS_LED_RED_PORT, BOARD_INITLEDPINS_LED_RED_PIN, &LED_RED_config);
|
||||
|
||||
gpio_pin_config_t LED_GREEN_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_12 (pin N8) */
|
||||
GPIO_PinInit(BOARD_INITLEDPINS_LED_GREEN_GPIO, BOARD_INITLEDPINS_LED_GREEN_PORT, BOARD_INITLEDPINS_LED_GREEN_PIN, &LED_GREEN_config);
|
||||
/* Initialize GPIO0 functionality on pin GPIO_0 (pin M1) */
|
||||
IO_MUX_SetPinMux(IO_MUX_GPIO0);
|
||||
/* Initialize GPIO1 functionality on pin GPIO_1 (pin N2) */
|
||||
IO_MUX_SetPinMux(IO_MUX_GPIO1);
|
||||
/* Initialize GPIO12 functionality on pin GPIO_12 (pin N8) */
|
||||
IO_MUX_SetPinMux(IO_MUX_GPIO12);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
146
hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h
Normal file
146
hw/bsp/rw61x/boards/frdm_rw612/pin_mux.h
Normal file
@ -0,0 +1,146 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*!
|
||||
* @brief mclk direction control: MCLK is in the output direction. */
|
||||
#define MCLKPINDIR_MCLKPINDIR_OUTPUT_DIRECTION 0x01u
|
||||
|
||||
/*! @name GPIO_5 (coord L7), J1[7]/MCLK
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_MCLKOUT_PERIPHERAL CLKCTL1 /*!<@brief Peripheral name */
|
||||
#define BOARD_INITPINS_MCLKOUT_SIGNAL MCLK /*!<@brief Signal name */
|
||||
#define BOARD_INITPINS_MCLKOUT_GPIO_PIN 5U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITPINS_MCLKOUT_PORT 0U /*!<@brief PORT number */
|
||||
#define BOARD_INITPINS_MCLKOUT_PIN 5U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITPINS_MCLKOUT_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name GPIO_11 (coord M2), J1[6]/WAKEUP_BTN
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_SIGNAL PIO0 /*!<@brief Signal name */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_CHANNEL 11 /*!<@brief Signal channel */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_GPIO_PIN 11U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_PORT 0U /*!<@brief PORT number */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_PIN 11U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITPINS_WAKEUP_BTN_PIN_MASK (1U << 11U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 */
|
||||
|
||||
/*!
|
||||
* @brief pio0[31:0] selection, high valid; sel[i]->pio0[i]->GPIO[i] Mask for item 13. */
|
||||
#define MCI_IO_MUX_GPIO_GRP0_SEL_13_MASK 0x2000u
|
||||
/*!
|
||||
* @brief pio0[31:0] selection, high valid; sel[i]->pio0[i]->GPIO[i] Mask for item 14. */
|
||||
#define MCI_IO_MUX_GPIO_GRP0_SEL_14_MASK 0x4000u
|
||||
/*!
|
||||
* @brief Bitwise enable control for mci_io_mux GPIO[21:0] Mask for item 13. */
|
||||
#define SOCCIU_MCI_IOMUX_EN0_EN_21_0_13_MASK 0x2000u
|
||||
/*!
|
||||
* @brief Bitwise enable control for mci_io_mux GPIO[21:0] Mask for item 14. */
|
||||
#define SOCCIU_MCI_IOMUX_EN0_EN_21_0_14_MASK 0x4000u
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 */
|
||||
|
||||
/*! @name GPIO_0 (coord M1), J1[14]/LED_BLUE
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_SIGNAL PIO0 /*!<@brief Signal name */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_CHANNEL 0 /*!<@brief Signal channel */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_GPIO_PIN 0U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_PORT 0U /*!<@brief PORT number */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_PIN 0U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDPINS_LED_BLUE_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name GPIO_1 (coord N2), J5[1]/LED_RED
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITLEDPINS_LED_RED_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITLEDPINS_LED_RED_SIGNAL PIO0 /*!<@brief Signal name */
|
||||
#define BOARD_INITLEDPINS_LED_RED_CHANNEL 1 /*!<@brief Signal channel */
|
||||
#define BOARD_INITLEDPINS_LED_RED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
|
||||
#define BOARD_INITLEDPINS_LED_RED_GPIO_PIN 1U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDPINS_LED_RED_PORT 0U /*!<@brief PORT number */
|
||||
#define BOARD_INITLEDPINS_LED_RED_PIN 1U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDPINS_LED_RED_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name GPIO_12 (coord N8), LED_GREEN
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_SIGNAL PIO0 /*!<@brief Signal name */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_CHANNEL 12 /*!<@brief Signal channel */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_GPIO_PIN 12U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_PORT 0U /*!<@brief PORT number */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_PIN 12U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDPINS_LED_GREEN_PIN_MASK (1U << 12U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitLEDPins(void); /* Function assigned for the Cortex-M33 */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
135
hw/bsp/rw61x/family.c
Normal file
135
hw/bsp/rw61x/family.c
Normal file
@ -0,0 +1,135 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2018, hathach (tinyusb.org)
|
||||
* Copyright (c) 2025, Gabriel Koppenstein
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
manufacturer: NXP
|
||||
*/
|
||||
|
||||
#include "bsp/board_api.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "board.h"
|
||||
#include "fsl_usart.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void USB_IRQHandler(void) {
|
||||
tusb_int_handler(1, true);
|
||||
}
|
||||
|
||||
void board_init(void) {
|
||||
|
||||
// Init button pin, LED pins, SWD pins & UART pins
|
||||
BOARD_InitBootPins();
|
||||
|
||||
// Init Clocks
|
||||
BOARD_InitBootClocks();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// Explicitly disable systick to prevent its ISR from running before scheduler start
|
||||
SysTick->CTRL &= ~1U;
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#ifdef NEOPIXEL_PIN
|
||||
// No neo pixel support yet
|
||||
#endif
|
||||
|
||||
#ifdef UART_DEV
|
||||
// Enable UART when debug log is on
|
||||
board_uart_init_clock();
|
||||
usart_config_t uart_config;
|
||||
USART_GetDefaultConfig(&uart_config);
|
||||
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
|
||||
uart_config.enableRx = true;
|
||||
uart_config.enableTx = true;
|
||||
USART_Init(UART_DEV, &uart_config, CLOCK_GetFlexCommClkFreq(LP_FLEXCOMM_INST));
|
||||
#endif
|
||||
|
||||
// USB Initialization
|
||||
// Reset USB
|
||||
RESET_PeripheralReset(kUSB_RST_SHIFT_RSTn);
|
||||
|
||||
// Enable USB Clock
|
||||
CLOCK_EnableClock(kCLOCK_Usb);
|
||||
|
||||
// Enable USB PHY
|
||||
CLOCK_EnableUsbhsPhyClock();
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state) {
|
||||
GPIO_PinWrite(LED_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void) {
|
||||
#ifdef BUTTON_GPIO
|
||||
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BOARD_INITPINS_WAKEUP_BTN_PORT, BUTTON_PIN);
|
||||
#endif
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len) {
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const* buf, int len) {
|
||||
#ifdef UART_DEV
|
||||
USART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
|
||||
return len;
|
||||
#else
|
||||
(void) buf; (void) len;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler(void) {
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void) {
|
||||
return system_ticks;
|
||||
}
|
||||
|
||||
#endif
|
||||
102
hw/bsp/rw61x/family.cmake
Normal file
102
hw/bsp/rw61x/family.cmake
Normal file
@ -0,0 +1,102 @@
|
||||
include_guard()
|
||||
|
||||
set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
|
||||
set(CMSIS_5 ${TOP}/lib/CMSIS_5)
|
||||
|
||||
# include board specific
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
|
||||
|
||||
# toolchain set up
|
||||
set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
|
||||
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS RW61X CACHE INTERNAL "")
|
||||
|
||||
#------------------------------------
|
||||
# Startup & Linker script
|
||||
#------------------------------------
|
||||
|
||||
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
|
||||
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
#------------------------------------
|
||||
function(family_add_board BOARD_TARGET)
|
||||
add_library(${BOARD_TARGET} STATIC
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
|
||||
${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
|
||||
${SDK_DIR}/drivers/common/fsl_common_arm.c
|
||||
${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
|
||||
${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
|
||||
${SDK_DIR}/drivers/flexspi/fsl_flexspi.c
|
||||
)
|
||||
|
||||
target_include_directories(${BOARD_TARGET} PUBLIC
|
||||
${CMSIS_5}/CMSIS/Core/Include
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/drivers
|
||||
${SDK_DIR}/drivers
|
||||
${SDK_DIR}/drivers/common
|
||||
${SDK_DIR}/drivers/lpc_gpio
|
||||
${SDK_DIR}/drivers/flexcomm
|
||||
${SDK_DIR}/drivers/flexcomm/usart
|
||||
${SDK_DIR}/drivers/flexspi
|
||||
)
|
||||
|
||||
update_board(${BOARD_TARGET})
|
||||
endfunction()
|
||||
|
||||
#------------------------------------
|
||||
# Functions
|
||||
#------------------------------------
|
||||
function(family_configure_example TARGET RTOS)
|
||||
family_configure_common(${TARGET} ${RTOS})
|
||||
family_add_tinyusb(${TARGET} OPT_MCU_RW61X)
|
||||
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
|
||||
|
||||
# ChipIdea HS
|
||||
${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
|
||||
${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
|
||||
${TOP}/src/portable/ehci/ehci.c
|
||||
|
||||
# Startup File
|
||||
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
|
||||
)
|
||||
|
||||
# Add Board specific includes
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
|
||||
)
|
||||
|
||||
# Linker Options
|
||||
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
|
||||
target_link_options(${TARGET} PUBLIC
|
||||
"LINKER:--script=${LD_FILE_GNU}"
|
||||
--specs=nosys.specs
|
||||
--specs=nano.specs
|
||||
)
|
||||
endif()
|
||||
|
||||
if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
|
||||
set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
|
||||
endif ()
|
||||
|
||||
# Handle Startup File Properties (Linting/Warnings)
|
||||
set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
|
||||
SKIP_LINTING ON
|
||||
COMPILE_OPTIONS -w
|
||||
)
|
||||
|
||||
# Flashing & Binary Generation
|
||||
family_add_bin_hex(${TARGET})
|
||||
family_flash_jlink(${TARGET})
|
||||
endfunction()
|
||||
52
hw/bsp/rw61x/family.mk
Normal file
52
hw/bsp/rw61x/family.mk
Normal file
@ -0,0 +1,52 @@
|
||||
UF2_FAMILY_ID = 0x2abc77ec
|
||||
SDK_DIR = hw/mcu/nxp/mcux-sdk
|
||||
|
||||
include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
|
||||
# Default to Highspeed PORT1
|
||||
PORT ?= 1
|
||||
|
||||
CFLAGS += \
|
||||
-flto \
|
||||
-DBOARD_TUD_RHPORT=$(PORT) \
|
||||
-DBOARD_TUH_RHPORT=$(PORT) \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED \
|
||||
-DBOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED \
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls
|
||||
|
||||
LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
|
||||
|
||||
SRC_C += \
|
||||
src/portable/chipidea/ci_hs/dcd_ci_hs.c \
|
||||
src/portable/chipidea/ci_hs/hcd_ci_hs.c \
|
||||
src/portable/ehci/ehci.c \
|
||||
$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
|
||||
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
|
||||
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
|
||||
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_power.c \
|
||||
$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
|
||||
$(SDK_DIR)/drivers/common/fsl_common_arm.c\
|
||||
$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
|
||||
$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
|
||||
$(SDK_DIR)/drivers/flexspi/fsl_flexspi.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
|
||||
$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
|
||||
$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
|
||||
$(TOP)/$(SDK_DIR)/drivers/ \
|
||||
$(TOP)/$(SDK_DIR)/drivers/common\
|
||||
$(TOP)/$(SDK_DIR)/drivers/lpc_gpio\
|
||||
$(TOP)/$(SDK_DIR)/drivers/flexcomm \
|
||||
$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
|
||||
$(TOP)/$(SDK_DIR)/drivers/flexspi \
|
||||
|
||||
|
||||
SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
|
||||
@ -61,6 +61,9 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
|
||||
|
||||
#include "ci_hs_lpc18_43.h"
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RW61X)
|
||||
#include "ci_hs_rw61x.h"
|
||||
|
||||
#else
|
||||
#error "Unsupported MCUs"
|
||||
#endif
|
||||
|
||||
@ -60,7 +60,7 @@ deps_optional = {
|
||||
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
|
||||
'hw/mcu/nxp/mcux-sdk': ['https://github.com/nxp-mcuxpresso/mcux-sdk',
|
||||
'a1bdae309a14ec95a4f64a96d3315a4f89c397c6',
|
||||
'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
|
||||
'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x imxrt'],
|
||||
'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
|
||||
'675543bcc9baa8170f868ab7ba316d418dbcf41f',
|
||||
'rp2040'],
|
||||
@ -246,7 +246,7 @@ deps_optional = {
|
||||
'at32f413'],
|
||||
'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
|
||||
'2b7495b8535bdcb306dac29b9ded4cfb679d7e5c',
|
||||
'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x '
|
||||
'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x mm32 msp432e4 nrf saml2x '
|
||||
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 '
|
||||
'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 '
|
||||
'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u0 stm32u5 stm32wb stm32wba '
|
||||
|
||||
Reference in New Issue
Block a user