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refactor speed check

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Signed-off-by: HiFiPhile <admin@hifiphile.com>
This commit is contained in:
HiFiPhile
2026-02-21 17:44:17 +01:00
parent dafb0d2bf4
commit b585df168a
4 changed files with 6 additions and 13 deletions
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2
src/portable/synopsys/dwc2/dcd_dwc2.c
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@ -442,7 +442,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
tu_memclr(&_dcd_data, sizeof(_dcd_data));
// Core Initialization
const bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, TUSB_ROLE_DEVICE);
const bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, TUD_OPT_HIGH_SPEED);
const bool is_dma = dma_device_enabled(dwc2);
TU_ASSERT(dwc2_core_init(rhport, highspeed_phy, is_dma));

11
src/portable/synopsys/dwc2/dwc2_common.c
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@ -179,7 +179,7 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
//--------------------------------------------------------------------
//
//--------------------------------------------------------------------
bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, tusb_role_t role) {
bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy) {
#ifdef TUP_USBIP_DWC2_STM32
if (dwc2->guid >= 0x5000) {
// femtoPHY UTMI+ PHY
@ -187,16 +187,9 @@ bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, tusb_role_t role) {
}
#endif
#if CFG_TUD_ENABLED
if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
if (!prefer_hs_phy) {
return false;
}
#endif
#if CFG_TUH_ENABLED
if (role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) {
return false;
}
#endif
const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
return ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;

2
src/portable/synopsys/dwc2/dwc2_common.h
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@ -84,7 +84,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base;
}
bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, tusb_role_t role);
bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy);
bool dwc2_core_init(uint8_t rhport, bool highspeed_phy, bool is_dma);
void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr);

4
src/portable/synopsys/dwc2/hcd_dwc2.c
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@ -366,7 +366,7 @@ static void dfifo_host_init(uint8_t rhport) {
// fixed allocation for now, improve later:
// - ptx_largest is limited to 256 for FS since most FS core only has 1024 bytes total
bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, TUSB_ROLE_HOST);
bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, _tuh_cfg.use_hs_phy);
uint32_t nptx_largest = highspeed_phy ? TUSB_EPSIZE_BULK_HS/4 : TUSB_EPSIZE_BULK_FS/4;
uint32_t ptx_largest = highspeed_phy ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4;
@ -406,7 +406,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
tu_memclr(&_hcd_data, sizeof(_hcd_data));
// Core Initialization
const bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, TUSB_ROLE_HOST) || _tuh_cfg.use_hs_phy;
const bool highspeed_phy = dwc2_core_is_highspeed_phy(dwc2, _tuh_cfg.use_hs_phy);
const bool is_dma = dma_host_enabled(dwc2);
TU_ASSERT(dwc2_core_init(rhport, highspeed_phy, is_dma));