mirror of
https://github.com/hathach/tinyusb.git
synced 2026-02-07 16:35:33 +00:00
make TUP_DCD_EDPT_ISO_ALLOC i.e dcd_edpt_iso_alloc()/dcd_edpt_iso_activate() as default driver implementation. dcd_edpt_close() is deprecated and will be removed from all driver in the future.
This commit is contained in:
hathach
@ -1,6 +1,5 @@
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mcu:CH32V103
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mcu:CH32V20X
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mcu:MCXA15
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mcu:MSP430x5xx
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mcu:NUC121
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mcu:SAMD11
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@ -6,7 +6,6 @@ mcu:CH32V103
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mcu:CH32V20X
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mcu:CH32V307
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mcu:STM32L0
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mcu:MCXA15
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family:espressif
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board:curiosity_nano
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board:kuiic
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@ -264,6 +264,9 @@ function(family_configure_common TARGET RTOS)
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ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib
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SKIP_LINTING ON # need cmake 4.2
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)
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if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
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set_target_properties(${BOARD_TARGET} PROPERTIES COMPILE_OPTIONS -w)
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endif ()
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endif ()
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target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET})
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endif ()
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@ -14,8 +14,11 @@ function(update_board TARGET)
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BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
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CFG_EXAMPLE_VIDEO_READONLY
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)
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target_sources(${TARGET} PUBLIC
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
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target_sources(${TARGET} PRIVATE
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c
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)
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target_include_directories(${TARGET} PUBLIC
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board
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)
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endfunction()
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@ -6,6 +6,14 @@ CPU_CORE = cortex-m33-nodsp-nofp
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CFLAGS += \
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-DCPU_MCXA153VLH \
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-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
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-DCFG_EXAMPLE_VIDEO_READONLY
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SRC_C += \
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${BOARD_PATH}/board/clock_config.c \
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${BOARD_PATH}/board/pin_mux.c
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INC += \
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$(TOP)/$(BOARD_PATH)/board
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JLINK_DEVICE = MCXA153
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PYOCD_TARGET = MCXA153
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@ -1,5 +1,5 @@
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/*
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* Copyright 2023 NXP
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* Copyright 2025 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -25,11 +25,12 @@
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v12.0
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product: Clocks v18.0
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processor: MCXA153
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package_id: MCXA153VLH
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mcu_data: ksdk2_0
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processor_version: 0.13.0
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processor_version: 25.09.10
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board: FRDM-MCXA153
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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@ -45,13 +46,14 @@ processor_version: 0.13.0
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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//extern uint32_t SystemCoreClock;
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockFRO96M();
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}
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/*******************************************************************************
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@ -68,9 +70,13 @@ outputs:
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- {id: MAIN_clock.outFreq, value: 12 MHz}
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- {id: Slow_clock.outFreq, value: 3 MHz}
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- {id: System_clock.outFreq, value: 12 MHz}
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- {id: TRACE_clock.outFreq, value: 12 MHz}
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- {id: UTICK_clock.outFreq, value: 1 MHz}
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- {id: WWDT0_clock.outFreq, value: 1 MHz}
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settings:
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- {id: SCGMode, value: SIRC}
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- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
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- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
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- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
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@ -106,6 +112,9 @@ void BOARD_BootClockFRO12M(void)
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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/*!< Set up system dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */
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@ -125,9 +134,11 @@ void BOARD_BootClockFRO12M(void)
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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@ -149,9 +160,14 @@ outputs:
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- {id: MAIN_clock.outFreq, value: 48 MHz}
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- {id: Slow_clock.outFreq, value: 6 MHz}
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- {id: System_clock.outFreq, value: 24 MHz}
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- {id: TRACE_clock.outFreq, value: 24 MHz}
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- {id: UTICK_clock.outFreq, value: 1 MHz}
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- {id: WWDT0_clock.outFreq, value: 1 MHz}
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settings:
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- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
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- {id: SYSCON.AHBCLKDIV.scale, value: '2'}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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@ -184,6 +200,11 @@ void BOARD_BootClockFRO24M(void)
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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/*!< Set up system dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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@ -205,10 +226,21 @@ void BOARD_BootClockFRO24M(void)
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
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@ -230,7 +262,12 @@ outputs:
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- {id: MAIN_clock.outFreq, value: 48 MHz}
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- {id: Slow_clock.outFreq, value: 12 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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- {id: TRACE_clock.outFreq, value: 48 MHz}
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- {id: UTICK_clock.outFreq, value: 1 MHz}
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- {id: WWDT0_clock.outFreq, value: 1 MHz}
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settings:
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- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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@ -264,6 +301,11 @@ void BOARD_BootClockFRO48M(void)
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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/*!< Set up system dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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@ -285,10 +327,21 @@ void BOARD_BootClockFRO48M(void)
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
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CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
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@ -310,8 +363,13 @@ outputs:
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- {id: MAIN_clock.outFreq, value: 64 MHz}
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- {id: Slow_clock.outFreq, value: 16 MHz}
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- {id: System_clock.outFreq, value: 64 MHz}
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- {id: TRACE_clock.outFreq, value: 64 MHz}
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- {id: UTICK_clock.outFreq, value: 1 MHz}
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- {id: WWDT0_clock.outFreq, value: 1 MHz}
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settings:
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- {id: VDD_CORE, value: voltage_1v1}
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- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
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- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
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@ -349,6 +407,11 @@ void BOARD_BootClockFRO64M(void)
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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/*!< Set up system dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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@ -370,10 +433,21 @@ void BOARD_BootClockFRO64M(void)
|
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}
|
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|
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/*!< Set up clock selectors - Attach clocks to the peripheries */
|
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CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
|
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CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
|
||||
|
||||
/*!< Set up dividers */
|
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
|
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
|
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CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
|
||||
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
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SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
|
||||
@ -385,6 +459,7 @@ void BOARD_BootClockFRO64M(void)
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFRO96M
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
@ -395,12 +470,14 @@ outputs:
|
||||
- {id: MAIN_clock.outFreq, value: 96 MHz}
|
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- {id: Slow_clock.outFreq, value: 24 MHz}
|
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- {id: System_clock.outFreq, value: 96 MHz}
|
||||
- {id: TRACE_clock.outFreq, value: 96 MHz}
|
||||
- {id: UTICK_clock.outFreq, value: 1 MHz}
|
||||
- {id: WWDT0_clock.outFreq, value: 1 MHz}
|
||||
settings:
|
||||
- {id: VDD_CORE, value: voltage_1v1}
|
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- {id: CLKOUTDIV_HALT, value: Enable}
|
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- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
|
||||
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
|
||||
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
|
||||
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
|
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- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
|
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sources:
|
||||
- {id: SCG.FIRC.outFreq, value: 96 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
@ -435,6 +512,11 @@ void BOARD_BootClockFRO96M(void)
|
||||
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
|
||||
}
|
||||
|
||||
|
||||
/*!< Set up system dividers */
|
||||
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
|
||||
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
|
||||
|
||||
CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
|
||||
|
||||
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
|
||||
@ -456,10 +538,21 @@ void BOARD_BootClockFRO96M(void)
|
||||
}
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
|
||||
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
|
||||
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
|
||||
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
|
||||
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
|
||||
385
hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h
Normal file
385
hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h
Normal file
@ -0,0 +1,385 @@
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKFRO12M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CLK_48M_CLOCK 0UL /* Clock consumers of CLK_48M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CPU_CLOCK 12000000UL /* Clock consumers of CPU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_FRO_HF_DIV_CLOCK 0UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_FRO_HF_CLOCK 0UL /* Clock consumers of FRO_HF_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_MAIN_CLOCK 12000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_SLOW_CLOCK 3000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 12000000UL /* Clock consumers of TRACE_clock output : SWD */
|
||||
#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
|
||||
#define BOARD_BOOTCLOCKFRO12M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO12M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO12M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO24M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO24M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKFRO24M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CPU_CLOCK 24000000UL /* Clock consumers of CPU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_FRO_HF_DIV_CLOCK 48000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_FRO_HF_CLOCK 48000000UL /* Clock consumers of FRO_HF_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_MAIN_CLOCK 48000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_SLOW_CLOCK 6000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_SYSTEM_CLOCK 24000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_TRACE_CLOCK 24000000UL /* Clock consumers of TRACE_clock output : SWD */
|
||||
#define BOARD_BOOTCLOCKFRO24M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
|
||||
#define BOARD_BOOTCLOCKFRO24M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO24M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO24M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO24M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO48M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO48M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKFRO48M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CPU_CLOCK 48000000UL /* Clock consumers of CPU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_FRO_HF_DIV_CLOCK 48000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_FRO_HF_CLOCK 48000000UL /* Clock consumers of FRO_HF_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_MAIN_CLOCK 48000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_SLOW_CLOCK 12000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_SYSTEM_CLOCK 48000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_TRACE_CLOCK 48000000UL /* Clock consumers of TRACE_clock output : SWD */
|
||||
#define BOARD_BOOTCLOCKFRO48M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
|
||||
#define BOARD_BOOTCLOCKFRO48M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO48M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO48M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO48M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO64M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO64M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKFRO64M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CPU_CLOCK 64000000UL /* Clock consumers of CPU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_FRO_HF_DIV_CLOCK 64000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_FRO_HF_CLOCK 64000000UL /* Clock consumers of FRO_HF_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_MAIN_CLOCK 64000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_SLOW_CLOCK 16000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_SYSTEM_CLOCK 64000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_TRACE_CLOCK 64000000UL /* Clock consumers of TRACE_clock output : SWD */
|
||||
#define BOARD_BOOTCLOCKFRO64M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
|
||||
#define BOARD_BOOTCLOCKFRO64M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO64M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO64M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO64M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO96M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO96M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKFRO96M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CPU_CLOCK 96000000UL /* Clock consumers of CPU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_FRO_HF_DIV_CLOCK 96000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_FRO_HF_CLOCK 96000000UL /* Clock consumers of FRO_HF_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_MAIN_CLOCK 96000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_SLOW_CLOCK 24000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_TRACE_CLOCK 96000000UL /* Clock consumers of TRACE_clock output : SWD */
|
||||
#define BOARD_BOOTCLOCKFRO96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
|
||||
#define BOARD_BOOTCLOCKFRO96M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKFRO96M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO96M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO96M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
492
hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c
Normal file
492
hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c
Normal file
@ -0,0 +1,492 @@
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v17.0
|
||||
processor: MCXA153
|
||||
package_id: MCXA153VLH
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 25.09.10
|
||||
board: FRDM-MCXA153
|
||||
external_user_signals: {}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_port.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitDEBUG_UARTPins();
|
||||
BOARD_InitLEDsPins();
|
||||
BOARD_InitBUTTONsPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitDEBUG_UARTPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: high, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitDEBUG_UARTPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitDEBUG_UARTPins(void)
|
||||
{
|
||||
/* Write to PORT0: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GatePORT0);
|
||||
/* LPUART0 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
|
||||
/* PORT0 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
|
||||
|
||||
const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
|
||||
.pullSelect = kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
.openDrainEnable = kPORT_OpenDrainDisable,
|
||||
/* High drive strength is configured */
|
||||
.driveStrength = kPORT_HighDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as LPUART0_RXD */
|
||||
.mux = kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT0_2 (pin 51) is configured as LPUART0_RXD */
|
||||
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
|
||||
|
||||
const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up resistor is enabled */
|
||||
.pullSelect = kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
.openDrainEnable = kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
.driveStrength = kPORT_LowDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as LPUART0_TXD */
|
||||
.mux = kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT0_3 (pin 52) is configured as LPUART0_TXD */
|
||||
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSWD_DEBUGPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '50', peripheral: SWD, signal: SWCLK, pin_signal: P0_1/TCLK/SWCLK/LPUART0_CTS_B/LPSPI0_SDI/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low,
|
||||
pull_select: down, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '49', peripheral: SWD, signal: SWDIO, pin_signal: P0_0/TMS/SWDIO/LPUART0_RTS_B/LPSPI0_PCS0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high,
|
||||
pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '51', peripheral: SWD, signal: SWO, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: high, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSWD_DEBUGPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSWD_DEBUGPins(void)
|
||||
{
|
||||
/* Write to PORT0: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GatePORT0);
|
||||
/* PORT0 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
|
||||
/* LPUART0 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWDIO = {/* Internal pull-up resistor is enabled */
|
||||
.pullSelect = kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
.openDrainEnable = kPORT_OpenDrainDisable,
|
||||
/* High drive strength is configured */
|
||||
.driveStrength = kPORT_HighDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as SWDIO */
|
||||
.mux = kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT0_0 (pin 49) is configured as SWDIO */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, &DEBUG_SWD_SWDIO);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWDCLK = {/* Internal pull-down resistor is enabled */
|
||||
.pullSelect = kPORT_PullDown,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
.openDrainEnable = kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
.driveStrength = kPORT_LowDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as SWCLK */
|
||||
.mux = kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT0_1 (pin 50) is configured as SWCLK */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, &DEBUG_SWD_SWDCLK);
|
||||
|
||||
const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
|
||||
.pullSelect = kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
.openDrainEnable = kPORT_OpenDrainDisable,
|
||||
/* High drive strength is configured */
|
||||
.driveStrength = kPORT_HighDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as SWO */
|
||||
.mux = kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT0_2 (pin 51) is configured as SWO */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitLEDsPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '37', peripheral: GPIO3, signal: 'GPIO, 13', pin_signal: P3_13/LPUART2_CTS_B/CT1_MAT3/PWM0_X1, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '46', peripheral: GPIO3, signal: 'GPIO, 0', pin_signal: P3_0/WUU0_IN22/TRIG_IN0/CT_INP16/PWM0_A0, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitLEDsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitLEDsPins(void)
|
||||
{
|
||||
/* Write to GPIO3: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GateGPIO3);
|
||||
/* Write to PORT3: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GatePORT3);
|
||||
/* GPIO3 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
|
||||
/* PORT3 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
|
||||
|
||||
gpio_pin_config_t LED_BLUE_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO3_0 (pin 46) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
|
||||
|
||||
gpio_pin_config_t LED_RED_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO3_12 (pin 38) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
|
||||
|
||||
gpio_pin_config_t LED_GREEN_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO3_13 (pin 37) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
|
||||
|
||||
/* PORT3_0 (pin 46) is configured as P3_0 */
|
||||
PORT_SetPinMux(BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, kPORT_MuxAlt0);
|
||||
|
||||
PORT3->PCR[0] =
|
||||
((PORT3->PCR[0] &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK)))
|
||||
|
||||
/* Pull Select: Enables internal pullup resistor. */
|
||||
| PORT_PCR_PS(PCR_PS_ps1)
|
||||
|
||||
/* Pull Enable: Disables. */
|
||||
| PORT_PCR_PE(PCR_PE_pe0)
|
||||
|
||||
/* Slew Rate Enable: Fast. */
|
||||
| PORT_PCR_SRE(PCR_SRE_sre0)
|
||||
|
||||
/* Passive Filter Enable: Disables. */
|
||||
| PORT_PCR_PFE(PCR_PFE_pfe0)
|
||||
|
||||
/* Open Drain Enable: Disables. */
|
||||
| PORT_PCR_ODE(PCR_ODE_ode0)
|
||||
|
||||
/* Drive Strength Enable: Low. */
|
||||
| PORT_PCR_DSE(PCR_DSE_dse0)
|
||||
|
||||
/* Input Buffer Enable: Enables. */
|
||||
| PORT_PCR_IBE(PCR_IBE_ibe1)
|
||||
|
||||
/* Invert Input: Does not invert. */
|
||||
| PORT_PCR_INV(PCR_INV_inv0));
|
||||
|
||||
/* PORT3_12 (pin 38) is configured as P3_12 */
|
||||
PORT_SetPinMux(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, kPORT_MuxAlt0);
|
||||
|
||||
PORT3->PCR[12] =
|
||||
((PORT3->PCR[12] &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK)))
|
||||
|
||||
/* Pull Select: Enables internal pullup resistor. */
|
||||
| PORT_PCR_PS(PCR_PS_ps1)
|
||||
|
||||
/* Pull Enable: Disables. */
|
||||
| PORT_PCR_PE(PCR_PE_pe0)
|
||||
|
||||
/* Slew Rate Enable: Fast. */
|
||||
| PORT_PCR_SRE(PCR_SRE_sre0)
|
||||
|
||||
/* Open Drain Enable: Disables. */
|
||||
| PORT_PCR_ODE(PCR_ODE_ode0)
|
||||
|
||||
/* Drive Strength Enable: Low. */
|
||||
| PORT_PCR_DSE(PCR_DSE_dse0)
|
||||
|
||||
/* Input Buffer Enable: Enables. */
|
||||
| PORT_PCR_IBE(PCR_IBE_ibe1)
|
||||
|
||||
/* Invert Input: Does not invert. */
|
||||
| PORT_PCR_INV(PCR_INV_inv0));
|
||||
|
||||
/* PORT3_13 (pin 37) is configured as P3_13 */
|
||||
PORT_SetPinMux(BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, kPORT_MuxAlt0);
|
||||
|
||||
PORT3->PCR[13] =
|
||||
((PORT3->PCR[13] &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK)))
|
||||
|
||||
/* Pull Select: Enables internal pullup resistor. */
|
||||
| PORT_PCR_PS(PCR_PS_ps1)
|
||||
|
||||
/* Pull Enable: Disables. */
|
||||
| PORT_PCR_PE(PCR_PE_pe0)
|
||||
|
||||
/* Slew Rate Enable: Fast. */
|
||||
| PORT_PCR_SRE(PCR_SRE_sre0)
|
||||
|
||||
/* Open Drain Enable: Disables. */
|
||||
| PORT_PCR_ODE(PCR_ODE_ode0)
|
||||
|
||||
/* Drive Strength Enable: Low. */
|
||||
| PORT_PCR_DSE(PCR_DSE_dse0)
|
||||
|
||||
/* Input Buffer Enable: Enables. */
|
||||
| PORT_PCR_IBE(PCR_IBE_ibe1)
|
||||
|
||||
/* Invert Input: Does not invert. */
|
||||
| PORT_PCR_INV(PCR_INV_inv0));
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitBUTTONsPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '1', peripheral: GPIO1, signal: 'GPIO, 7', pin_signal: P1_7/WUU0_IN9/TRIG_OUT2/LPUART2_CTS_B/CT_INP7/ADC0_A23, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '8', peripheral: GPIO1, signal: 'GPIO, 29', pin_signal: P1_29/RESET_B/SPC_LPREQ, slew_rate: fast, open_drain: enable, drive_strength: low, pull_select: up,
|
||||
pull_enable: enable, passive_filter: enable, pull_value: low, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '32', peripheral: GPIO3, signal: 'GPIO, 29', pin_signal: P3_29/WUU0_IN27/ISPMODE_N/CT_INP3/ADC0_A14, slew_rate: fast, open_drain: disable, drive_strength: low,
|
||||
pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBUTTONsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBUTTONsPins(void)
|
||||
{
|
||||
/* Write to PORT1: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GatePORT1);
|
||||
/* Write to PORT3: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GatePORT3);
|
||||
/* GPIO1 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
|
||||
/* PORT1 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
|
||||
/* GPIO3 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
|
||||
/* PORT3 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
|
||||
|
||||
const port_pin_config_t SW1 = {/* Internal pull-up resistor is enabled */
|
||||
.pullSelect = kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is enabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterEnable,
|
||||
/* Open drain output is enabled */
|
||||
.openDrainEnable = kPORT_OpenDrainEnable,
|
||||
/* Low drive strength is configured */
|
||||
.driveStrength = kPORT_LowDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as P1_29 */
|
||||
.mux = kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT1_29 (pin 8) is configured as P1_29 */
|
||||
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW1_PORT, BOARD_INITBUTTONSPINS_SW1_PIN, &SW1);
|
||||
|
||||
const port_pin_config_t SW3 = {/* Internal pull-up/down resistor is disabled */
|
||||
.pullSelect = kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
.openDrainEnable = kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
.driveStrength = kPORT_LowDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as P1_7 */
|
||||
.mux = kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT1_7 (pin 1) is configured as P1_7 */
|
||||
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3);
|
||||
|
||||
const port_pin_config_t ISP = {/* Internal pull-up resistor is enabled */
|
||||
.pullSelect = kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
.pullValueSelect = kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
.slewRate = kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
.passiveFilterEnable = kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
.openDrainEnable = kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
.driveStrength = kPORT_LowDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
.driveStrength1 = kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as P3_29 */
|
||||
.mux = kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
.inputBuffer = kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
.invertInput = kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
.lockRegister = kPORT_UnlockRegister};
|
||||
/* PORT3_29 (pin 32) is configured as P3_29 */
|
||||
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_ISP_PORT, BOARD_INITBUTTONSPINS_ISP_PIN, &ISP);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
211
hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h
Normal file
211
hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h
Normal file
@ -0,0 +1,211 @@
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*! @name PORT0_2 (number 51), P0_2/SWO/J25[3]/J18[6]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 2U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_3 (number 52), P0_3/J25[1]/J18[8]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 3U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 3U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitDEBUG_UARTPins(void);
|
||||
|
||||
/*! @name PORT0_1 (number 50), P0_1/SWCLK/JP10[2]/J18[4]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 1U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_0 (number 49), P0_0/SWDIO/J18[2]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 0U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_2 (number 51), P0_2/SWO/J25[3]/J18[6]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN 2U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSWD_DEBUGPins(void);
|
||||
|
||||
#define PCR_DSE_dse0 0x00u /*!<@brief Drive Strength Enable: Low */
|
||||
#define PCR_IBE_ibe1 0x01u /*!<@brief Input Buffer Enable: Enables */
|
||||
#define PCR_INV_inv0 0x00u /*!<@brief Invert Input: Does not invert */
|
||||
#define PCR_ODE_ode0 0x00u /*!<@brief Open Drain Enable: Disables */
|
||||
#define PCR_PE_pe0 0x00u /*!<@brief Pull Enable: Disables */
|
||||
#define PCR_PFE_pfe0 0x00u /*!<@brief Passive Filter Enable: Disables */
|
||||
#define PCR_PS_ps1 0x01u /*!<@brief Pull Select: Enables internal pullup resistor */
|
||||
#define PCR_SRE_sre0 0x00u /*!<@brief Slew Rate Enable: Fast */
|
||||
|
||||
/*! @name PORT3_13 (number 37), P3_13/J1[14]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 13U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 13U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PORT PORT3 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN 13U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT3_12 (number 38), P3_12/J1[12]/J5[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 12U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 12U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PORT PORT3 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN 12U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 12U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT3_0 (number 46), P3_0/J1[8]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 0U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PORT PORT3 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PIN 0U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitLEDsPins(void);
|
||||
|
||||
/*! @name PORT1_7 (number 1), P1_7/J1[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 7U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PIN 7U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PIN_MASK (1U << 7U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT1_29 (number 8), P1_29/J3[6]/J18[10]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW1_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW1_GPIO_PIN 29U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW1_GPIO_PIN_MASK (1U << 29U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW1_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW1_PIN 29U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW1_PIN_MASK (1U << 29U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT3_29 (number 32), P3_29/J18[7]/J4[11]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_ISP_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_ISP_GPIO_PIN 29U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_ISP_GPIO_PIN_MASK (1U << 29U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITBUTTONSPINS_ISP_PORT PORT3 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_ISP_PIN 29U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_ISP_PIN_MASK (1U << 29U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBUTTONsPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -1,170 +0,0 @@
|
||||
/*
|
||||
* Copyright 2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO12M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO24M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO24M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO24M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO24M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO48M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO48M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO48M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO48M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO64M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO64M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO64M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO64M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO96M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO96M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO96M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO96M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
573
hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex
Normal file
573
hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex
Normal file
@ -0,0 +1,573 @@
|
||||
<?xml version="1.0" encoding= "UTF-8" ?>
|
||||
<configuration name="FRDM-MCXA153" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="39087bef-8f98-40a9-aaf4-e556fb7a1ce1" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<common>
|
||||
<processor>MCXA153</processor>
|
||||
<package>MCXA153VLH</package>
|
||||
<board>FRDM-MCXA153</board>
|
||||
<mcu_data>ksdk2_0</mcu_data>
|
||||
<cores selected="cm33_core0">
|
||||
<core name="Cortex-M33" id="cm33_core0" description="M33 core"/>
|
||||
</cores>
|
||||
<description></description>
|
||||
</common>
|
||||
<preferences>
|
||||
<validate_boot_init_only>true</validate_boot_init_only>
|
||||
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
|
||||
<custom_copyright>
|
||||
<text>/*
|
||||
* Copyright 2025 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
</text>
|
||||
<enabled>true</enabled>
|
||||
</custom_copyright>
|
||||
<update_include_paths>true</update_include_paths>
|
||||
<enable_parallel_routing>true</enable_parallel_routing>
|
||||
<generate_registers_defines>false</generate_registers_defines>
|
||||
</preferences>
|
||||
<tools>
|
||||
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/pin_mux.c" update_enabled="true"/>
|
||||
<file path="board/pin_mux.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<pins_profile>
|
||||
<processor_version>25.09.10</processor_version>
|
||||
<external_user_signals>
|
||||
<properties/>
|
||||
</external_user_signals>
|
||||
</pins_profile>
|
||||
<functions_list>
|
||||
<function name="BOARD_InitDEBUG_UARTPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>true</callFromInitBoot>
|
||||
<coreID>cm33_core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="LPUART0" description="Peripheral LPUART0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="LPUART0" signal="RX" pin_num="51" pin_signal="P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="high"/>
|
||||
<pin_feature name="pull_select" value="down"/>
|
||||
<pin_feature name="pull_enable" value="disable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="LPUART0" signal="TX" pin_num="52" pin_signal="P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="up"/>
|
||||
<pin_feature name="pull_enable" value="enable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
<function name="BOARD_InitSWD_DEBUGPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>false</callFromInitBoot>
|
||||
<coreID>cm33_core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="SWD" signal="SWCLK" pin_num="50" pin_signal="P0_1/TCLK/SWCLK/LPUART0_CTS_B/LPSPI0_SDI/CT_INP1">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="down"/>
|
||||
<pin_feature name="pull_enable" value="enable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="SWD" signal="SWDIO" pin_num="49" pin_signal="P0_0/TMS/SWDIO/LPUART0_RTS_B/LPSPI0_PCS0/CT_INP0">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="high"/>
|
||||
<pin_feature name="pull_select" value="up"/>
|
||||
<pin_feature name="pull_enable" value="enable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="SWD" signal="SWO" pin_num="51" pin_signal="P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="high"/>
|
||||
<pin_feature name="pull_select" value="down"/>
|
||||
<pin_feature name="pull_enable" value="disable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
<function name="BOARD_InitLEDsPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>true</callFromInitBoot>
|
||||
<coreID>cm33_core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.gpio" description="Pins initialization requires the GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="GPIO3" signal="GPIO, 13" pin_num="37" pin_signal="P3_13/LPUART2_CTS_B/CT1_MAT3/PWM0_X1">
|
||||
<pin_features>
|
||||
<pin_feature name="direction" value="OUTPUT"/>
|
||||
<pin_feature name="gpio_init_state" value="true"/>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="up"/>
|
||||
<pin_feature name="pull_enable" value="disable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO3" signal="GPIO, 12" pin_num="38" pin_signal="P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0">
|
||||
<pin_features>
|
||||
<pin_feature name="direction" value="OUTPUT"/>
|
||||
<pin_feature name="gpio_init_state" value="true"/>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="up"/>
|
||||
<pin_feature name="pull_enable" value="disable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO3" signal="GPIO, 0" pin_num="46" pin_signal="P3_0/WUU0_IN22/TRIG_IN0/CT_INP16/PWM0_A0">
|
||||
<pin_features>
|
||||
<pin_feature name="direction" value="OUTPUT"/>
|
||||
<pin_feature name="gpio_init_state" value="true"/>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="up"/>
|
||||
<pin_feature name="pull_enable" value="disable"/>
|
||||
<pin_feature name="passive_filter" value="disable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
<function name="BOARD_InitBUTTONsPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>true</callFromInitBoot>
|
||||
<coreID>cm33_core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="GPIO1" signal="GPIO, 7" pin_num="1" pin_signal="P1_7/WUU0_IN9/TRIG_OUT2/LPUART2_CTS_B/CT_INP7/ADC0_A23">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="down"/>
|
||||
<pin_feature name="pull_enable" value="disable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO1" signal="GPIO, 29" pin_num="8" pin_signal="P1_29/RESET_B/SPC_LPREQ">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="enable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="up"/>
|
||||
<pin_feature name="pull_enable" value="enable"/>
|
||||
<pin_feature name="passive_filter" value="enable"/>
|
||||
<pin_feature name="pull_value" value="low"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO3" signal="GPIO, 29" pin_num="32" pin_signal="P3_29/WUU0_IN27/ISPMODE_N/CT_INP3/ADC0_A14">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="fast"/>
|
||||
<pin_feature name="open_drain" value="disable"/>
|
||||
<pin_feature name="drive_strength" value="low"/>
|
||||
<pin_feature name="pull_select" value="up"/>
|
||||
<pin_feature name="pull_enable" value="enable"/>
|
||||
<pin_feature name="input_buffer" value="enable"/>
|
||||
<pin_feature name="invert_input" value="normal"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
</functions_list>
|
||||
</pins>
|
||||
<clocks name="Clocks" version="18.0" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/clock_config.c" update_enabled="true"/>
|
||||
<file path="board/clock_config.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<clocks_profile>
|
||||
<processor_version>25.09.10</processor_version>
|
||||
</clocks_profile>
|
||||
<clock_configurations>
|
||||
<clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources/>
|
||||
<clock_outputs>
|
||||
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CPU_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MAIN_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="Slow_clock.outFreq" value="3 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="SCGMode" value="SIRC" locked="false"/>
|
||||
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
|
||||
<setting id="SCG.SCSSEL.sel" value="SCG.SIRC" locked="false"/>
|
||||
<setting id="SCG_FIRCCSR_FIRCEN_CFG" value="Disabled" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>false</called_from_default_init>
|
||||
</clock_configuration>
|
||||
<clock_configuration name="BOARD_BootClockFRO24M" id_prefix="" prefix_user_defined="false">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO24M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO24M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO24M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources/>
|
||||
<clock_outputs>
|
||||
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CPU_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_DIV_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MAIN_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="Slow_clock.outFreq" value="6 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="System_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
|
||||
<setting id="SYSCON.AHBCLKDIV.scale" value="2" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>false</called_from_default_init>
|
||||
</clock_configuration>
|
||||
<clock_configuration name="BOARD_BootClockFRO48M" id_prefix="" prefix_user_defined="false">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO48M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO48M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO48M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources/>
|
||||
<clock_outputs>
|
||||
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CPU_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_DIV_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MAIN_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="Slow_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="System_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>false</called_from_default_init>
|
||||
</clock_configuration>
|
||||
<clock_configuration name="BOARD_BootClockFRO64M" id_prefix="" prefix_user_defined="false">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO64M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO64M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO64M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources>
|
||||
<clock_source id="SCG.FIRC.outFreq" value="64 MHz" locked="false" enabled="false"/>
|
||||
</clock_sources>
|
||||
<clock_outputs>
|
||||
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CPU_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_DIV_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MAIN_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="Slow_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="System_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="VDD_CORE" value="voltage_1v1" locked="false"/>
|
||||
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.FROHFDIV.scale" value="1" locked="true"/>
|
||||
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
|
||||
<setting id="SYSCON.AHBCLKDIV.scale" value="1" locked="true"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>false</called_from_default_init>
|
||||
</clock_configuration>
|
||||
<clock_configuration name="BOARD_BootClockFRO96M" id_prefix="" prefix_user_defined="false">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO96M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO96M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO96M">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources>
|
||||
<clock_source id="SCG.FIRC.outFreq" value="96 MHz" locked="false" enabled="false"/>
|
||||
</clock_sources>
|
||||
<clock_outputs>
|
||||
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CPU_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_DIV_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FRO_HF_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MAIN_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="Slow_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="VDD_CORE" value="voltage_1v1" locked="false"/>
|
||||
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
|
||||
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>true</called_from_default_init>
|
||||
</clock_configuration>
|
||||
</clock_configurations>
|
||||
</clocks>
|
||||
<dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
|
||||
<generated_project_files/>
|
||||
<dcdx_profile>
|
||||
<processor_version>N/A</processor_version>
|
||||
</dcdx_profile>
|
||||
<dcdx_configurations/>
|
||||
</dcdx>
|
||||
<periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/peripherals.c" update_enabled="true"/>
|
||||
<file path="board/peripherals.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<peripherals_profile>
|
||||
<processor_version>25.09.10</processor_version>
|
||||
</peripherals_profile>
|
||||
<functional_groups>
|
||||
<functional_group name="BOARD_InitPeripherals" uuid="e7964cfd-63b7-4756-a1af-71a53c49bda7" called_from_default_init="true" id_prefix="" core="cm33_core0">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies/>
|
||||
<instances>
|
||||
<instance name="NVIC" uuid="6948572f-4bff-423f-8e78-3f0608580bb3" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
||||
<config_set name="nvic">
|
||||
<array name="interrupt_table"/>
|
||||
<array name="interrupts"/>
|
||||
</config_set>
|
||||
</instance>
|
||||
</instances>
|
||||
</functional_group>
|
||||
</functional_groups>
|
||||
<components>
|
||||
<component name="system" uuid="3700167a-8497-4b9d-ad19-c395e5e33267" type_id="system">
|
||||
<config_set_global name="global_system_definitions">
|
||||
<setting name="user_definitions" value=""/>
|
||||
<setting name="user_includes" value=""/>
|
||||
<setting name="global_init" value=""/>
|
||||
</config_set_global>
|
||||
</component>
|
||||
<component name="msg" uuid="faf79cc1-e0a0-4bf8-a803-42cf14e2a60a" type_id="msg">
|
||||
<config_set_global name="global_messages"/>
|
||||
</component>
|
||||
<component name="generic_can" uuid="f1cb80d2-97a1-4bdd-ab65-0d3d8493019c" type_id="generic_can">
|
||||
<config_set_global name="global_can"/>
|
||||
</component>
|
||||
<component name="uart_cmsis_common" uuid="a17f12aa-b188-417b-a499-c22892686ae2" type_id="uart_cmsis_common">
|
||||
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
|
||||
</component>
|
||||
<component name="generic_uart" uuid="96c6481f-affb-44c4-9d6f-ebc972fcae38" type_id="generic_uart">
|
||||
<config_set_global name="global_uart"/>
|
||||
</component>
|
||||
<component name="generic_enet" uuid="44df8b34-f20e-449a-8d2d-2cba12faf3f7" type_id="generic_enet">
|
||||
<config_set_global name="global_enet"/>
|
||||
</component>
|
||||
<component name="gpio_adapter_common" uuid="2fe36bae-ef17-4655-9cf5-91cac6de7288" type_id="gpio_adapter_common">
|
||||
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
|
||||
</component>
|
||||
</components>
|
||||
</periphs>
|
||||
<tee name="TEE" version="10.0" enabled="false" update_project_code="true">
|
||||
<generated_project_files/>
|
||||
<tee_profile>
|
||||
<processor_version>N/A</processor_version>
|
||||
</tee_profile>
|
||||
</tee>
|
||||
</tools>
|
||||
</configuration>
|
||||
@ -1,130 +0,0 @@
|
||||
/*
|
||||
* Copyright 2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v14.0
|
||||
processor: MCXA153
|
||||
package_id: MCXA153VLH
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.14.4
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_port.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_GateGPIO3);
|
||||
/* Write to PORT3: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GatePORT3);
|
||||
/* GPIO3 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
|
||||
/* PORT3 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
|
||||
|
||||
|
||||
/* Write to PORT0: Peripheral clock is enabled */
|
||||
CLOCK_EnableClock(kCLOCK_GatePORT0);
|
||||
/* LPUART0 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
|
||||
/* PORT0 peripheral is released from reset */
|
||||
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
|
||||
|
||||
const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
|
||||
kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as LPUART0_RXD */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_2 (pin 51) is configured as LPUART0_RXD */
|
||||
PORT_SetPinConfig(PORT0, 2U, &port0_2_pin51_config);
|
||||
|
||||
const port_pin_config_t port0_3_pin52_config = {/* Internal pull-up resistor is enabled */
|
||||
kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Normal drive strength is configured */
|
||||
kPORT_NormalDriveStrength,
|
||||
/* Pin is configured as LPUART0_TXD */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_3 (pin 52) is configured as LPUART0_TXD */
|
||||
PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -1,51 +0,0 @@
|
||||
/*
|
||||
* Copyright 2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -61,14 +61,9 @@ void USB0_IRQHandler(void) {
|
||||
|
||||
void board_init(void) {
|
||||
|
||||
BOARD_InitPins();
|
||||
|
||||
BOARD_InitBootPins();
|
||||
BOARD_InitBootClocks();
|
||||
|
||||
#ifdef XTAL0_CLK_HZ
|
||||
CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
|
||||
@ -11,7 +11,7 @@ CFLAGS += \
|
||||
-DBOARD_TUD_RHPORT=$(PORT) \
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls
|
||||
|
||||
LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
|
||||
|
||||
@ -56,12 +56,9 @@ INC += \
|
||||
$(TOP)/$(SDK_DIR)/drivers/ \
|
||||
$(TOP)/$(SDK_DIR)/drivers/lpuart \
|
||||
$(TOP)/$(SDK_DIR)/drivers/lpflexcomm \
|
||||
$(TOP)/$(SDK_DIR)/drivers/common\
|
||||
$(TOP)/$(SDK_DIR)/drivers/gpio\
|
||||
$(TOP)/$(SDK_DIR)/drivers/port\
|
||||
$(TOP)/hw/bsp/mcx/drivers/spc
|
||||
|
||||
|
||||
|
||||
$(TOP)/$(SDK_DIR)/drivers/common\
|
||||
$(TOP)/$(SDK_DIR)/drivers/gpio\
|
||||
$(TOP)/$(SDK_DIR)/drivers/port\
|
||||
$(TOP)/hw/bsp/mcx/drivers/spc
|
||||
|
||||
SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
|
||||
|
||||
@ -543,6 +543,10 @@
|
||||
#define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS
|
||||
#define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
|
||||
|
||||
#if CFG_TUD_WCH_USBIP_USBHS
|
||||
#define TUP_DCD_EDPT_CLOSE_API
|
||||
#endif
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_CH32V103)
|
||||
#define TUP_USBIP_WCH_USBFS
|
||||
|
||||
@ -590,6 +594,10 @@
|
||||
#define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS
|
||||
#define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
|
||||
|
||||
#if CFG_TUD_WCH_USBIP_USBHS
|
||||
#define TUP_DCD_EDPT_CLOSE_API
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Analog Devices
|
||||
//--------------------------------------------------------------------+
|
||||
@ -681,8 +689,7 @@
|
||||
#define TU_ATTR_FAST_FUNC
|
||||
#endif
|
||||
|
||||
#if defined(TUP_USBIP_CHIPIDEA_FS) || defined(TUP_USBIP_IP3511) || defined(TUP_USBIP_RUSB2) || \
|
||||
(defined(TUP_USBIP_WCH_USBFS) && CFG_TUD_WCH_USBIP_USBFS)
|
||||
#if defined(TUP_USBIP_IP3511) || defined(TUP_USBIP_RUSB2)
|
||||
#define TUP_DCD_EDPT_CLOSE_API
|
||||
#endif
|
||||
|
||||
|
||||
@ -344,24 +344,21 @@ void dcd_sof_enable(uint8_t rhport, bool en)
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoint API
|
||||
//--------------------------------------------------------------------+
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
const unsigned ep_addr = ep_desc->bEndpointAddress;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned xfer = ep_desc->bmAttributes.xfer;
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
const unsigned odd = ep->odd;
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
static bool edpt_open(uint8_t rhport, uint8_t ep_addr, uint16_t max_packet_size, tusb_xfer_type_t xfer) {
|
||||
(void)rhport;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
const unsigned odd = ep->odd;
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
|
||||
/* No support for control transfer */
|
||||
TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
|
||||
|
||||
ep->max_packet_size = tu_edpt_packet_size(ep_desc);
|
||||
ep->max_packet_size = max_packet_size;
|
||||
|
||||
unsigned val = USB_ENDPT_EPCTLDIS_MASK;
|
||||
val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
|
||||
val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK : 0;
|
||||
val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
|
||||
CI_REG->EP[epn].CTL |= val;
|
||||
|
||||
@ -375,8 +372,27 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
||||
return true;
|
||||
}
|
||||
|
||||
void dcd_edpt_close_all(uint8_t rhport)
|
||||
{
|
||||
bool dcd_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) {
|
||||
return edpt_open(rhport, ep_desc->bEndpointAddress, tu_edpt_packet_size(ep_desc), ep_desc->bmAttributes.xfer);
|
||||
}
|
||||
|
||||
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
|
||||
return edpt_open(rhport, ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS);
|
||||
}
|
||||
|
||||
bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) {
|
||||
const unsigned epn = tu_edpt_number(ep_desc->bEndpointAddress);
|
||||
const unsigned dir = tu_edpt_dir(ep_desc->bEndpointAddress);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
|
||||
dcd_int_disable(rhport);
|
||||
ep->max_packet_size = tu_edpt_packet_size(ep_desc);
|
||||
dcd_int_enable(rhport);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void dcd_edpt_close_all(uint8_t rhport) {
|
||||
dcd_int_disable(rhport);
|
||||
|
||||
for (unsigned i = 1; i < 16; ++i) {
|
||||
@ -399,43 +415,6 @@ void dcd_edpt_close_all(uint8_t rhport)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef TUP_DCD_EDPT_CLOSE_API
|
||||
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
|
||||
|
||||
dcd_int_disable(rhport);
|
||||
|
||||
CI_REG->EP[epn].CTL &= ~msk;
|
||||
ep->max_packet_size = 0;
|
||||
ep->length = 0;
|
||||
ep->remaining = 0;
|
||||
bd[0].head = 0;
|
||||
bd[1].head = 0;
|
||||
|
||||
dcd_int_enable(rhport);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
|
||||
(void) rhport;
|
||||
(void) ep_addr;
|
||||
(void) largest_packet_size;
|
||||
return false;
|
||||
}
|
||||
|
||||
bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) {
|
||||
(void) rhport;
|
||||
(void) desc_ep;
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
|
||||
@ -355,24 +355,21 @@ void dcd_sof_enable(uint8_t rhport, bool en)
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoint API
|
||||
//--------------------------------------------------------------------+
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
||||
{
|
||||
(void) rhport;
|
||||
static bool edpt_open(uint8_t rhport, uint8_t ep_addr, uint16_t max_packet_size, tusb_xfer_type_t xfer) {
|
||||
(void)rhport;
|
||||
|
||||
const unsigned ep_addr = ep_desc->bEndpointAddress;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned xfer = ep_desc->bmAttributes.xfer;
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
const unsigned odd = ep->odd;
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
const unsigned odd = ep->odd;
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
|
||||
/* No support for control transfer */
|
||||
TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
|
||||
|
||||
ep->max_packet_size = tu_edpt_packet_size(ep_desc);
|
||||
unsigned val = USB_ENDPT_EPCTLDIS_MASK;
|
||||
val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
|
||||
ep->max_packet_size = max_packet_size;
|
||||
unsigned val = USB_ENDPT_EPCTLDIS_MASK;
|
||||
val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK : 0;
|
||||
val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
|
||||
KHCI->ENDPOINT[epn].ENDPT |= val;
|
||||
|
||||
@ -386,6 +383,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
||||
return true;
|
||||
}
|
||||
|
||||
bool dcd_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) {
|
||||
return edpt_open(rhport, ep_desc->bEndpointAddress, tu_edpt_packet_size(ep_desc), ep_desc->bmAttributes.xfer);
|
||||
}
|
||||
|
||||
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
|
||||
return edpt_open(rhport, ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS);
|
||||
}
|
||||
|
||||
bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) {
|
||||
const unsigned epn = tu_edpt_number(ep_desc->bEndpointAddress);
|
||||
const unsigned dir = tu_edpt_dir(ep_desc->bEndpointAddress);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
|
||||
dcd_int_disable(rhport);
|
||||
ep->max_packet_size = tu_edpt_packet_size(ep_desc);
|
||||
dcd_int_enable(rhport);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void dcd_edpt_close_all(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
@ -408,41 +425,6 @@ void dcd_edpt_close_all(uint8_t rhport)
|
||||
}
|
||||
}
|
||||
|
||||
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
|
||||
const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
KHCI->ENDPOINT[epn].ENDPT &= ~msk;
|
||||
ep->max_packet_size = 0;
|
||||
ep->length = 0;
|
||||
ep->remaining = 0;
|
||||
bd[0].head = 0;
|
||||
bd[1].head = 0;
|
||||
if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
#if 0
|
||||
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
|
||||
(void) rhport;
|
||||
(void) ep_addr;
|
||||
(void) largest_packet_size;
|
||||
return false;
|
||||
}
|
||||
|
||||
bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) {
|
||||
(void) rhport;
|
||||
(void) desc_ep;
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
Reference in New Issue
Block a user