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fix build with dwc2

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hathach
2026-01-03 17:52:58 +07:00
parent 93a1e8093a
commit d457ea3d3c
4 changed files with 65 additions and 69 deletions
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2
src/common/tusb_fifo.h
View File

@ -41,7 +41,7 @@ extern "C" {
// mutex is only needed for RTOS. For OS None, we don't get preempted
#define CFG_FIFO_MUTEX OSAL_MUTEX_REQUIRED
#define CFG_TUSB_FIFO_HWFIFO_API (CFG_TUD_EDPT_DEDICATED_HWFIFO)
#define CFG_TUSB_FIFO_HWFIFO_API (CFG_TUD_EDPT_DEDICATED_HWFIFO || CFG_TUH_EDPT_DEDICATED_HWFIFO)
#ifndef CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 0

8
src/common/tusb_mcu.h
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@ -429,10 +429,6 @@
#define TUP_MCU_MULTIPLE_CORE 1
#endif
// Disable slave if DMA is enabled
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_ESP32
@ -445,10 +441,6 @@
#define TUP_MCU_MULTIPLE_CORE 1
// Disable slave if DMA is enabled
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE

85
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@ -98,10 +98,14 @@ TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_enabled(dwc2_dep_t* dep) {
return (dep->ctl & EPCTL_EPENA) != 0;
}
//--------------------------------------------------------------------
// DMA
//--------------------------------------------------------------------
#if CFG_TUD_MEM_DCACHE_ENABLE
#if CFG_TUD_DWC2_SLAVE_ENABLE
static uint16_t epin_write_tx_fifo(dwc2_regs_t *dwc2, uint8_t epnum);
#endif
//--------------------------------------------------------------------
// DMA
//--------------------------------------------------------------------
#if CFG_TUD_MEM_DCACHE_ENABLE
bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size);
return dwc2_dcache_clean(addr, data_size);
@ -345,39 +349,6 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
}
}
static uint16_t epin_write_tx_fifo(dwc2_regs_t *dwc2, uint8_t epnum) {
dwc2_dep_t *const epin = &dwc2->ep[0][epnum];
xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
dwc2_ep_tsize_t tsiz = {.value = epin->tsiz};
const uint16_t remain_packets = tsiz.packet_count;
uint16_t total_bytes_written = 0;
// Process every single packet (only whole packets can be written to fifo)
for (uint16_t i = 0; i < remain_packets; i++) {
tsiz.value = epin->tsiz;
const uint16_t remain_bytes = (uint16_t) tsiz.xfer_size;
const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
// Check if dtxfsts has enough space available
if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
break;
}
// Push packet to Tx-FIFO
volatile uint32_t *tx_fifo = dwc2->fifo[epnum];
if (xfer->ff) {
tu_hwfifo_write_from_fifo(tx_fifo, xfer->ff, xact_bytes, NULL);
total_bytes_written += xact_bytes;
} else {
tu_hwfifo_write(tx_fifo, xfer->buffer, xact_bytes, NULL);
xfer->buffer += xact_bytes;
total_bytes_written += xact_bytes;
}
}
return total_bytes_written;
}
// Since this function returns void, it is not possible to return a boolean success message
// We must make sure that this function is not called when the EP is disabled
// Must be called from critical section
@ -422,6 +393,7 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
}
}
#if CFG_TUD_DWC2_DMA_ENABLE
const bool is_dma = dma_device_enabled(dwc2);
if(is_dma) {
if (dir == TUSB_DIR_IN && total_bytes != 0) {
@ -433,7 +405,10 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
if (epnum == 0) {
xfer->buffer += total_bytes;
}
} else {
} else
#endif
{
#if CFG_TUD_DWC2_SLAVE_ENABLE
dep->diepctl = depctl.value; // enable endpoint
if (dir == TUSB_DIR_IN && total_bytes != 0) {
@ -445,6 +420,7 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
dwc2->diepempmsk |= (1u << epnum);
}
}
#endif
}
}
@ -850,6 +826,39 @@ TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) {
#endif
#if CFG_TUD_DWC2_SLAVE_ENABLE
static uint16_t epin_write_tx_fifo(dwc2_regs_t *dwc2, uint8_t epnum) {
dwc2_dep_t *const epin = &dwc2->ep[0][epnum];
xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
dwc2_ep_tsize_t tsiz = {.value = epin->tsiz};
const uint16_t remain_packets = tsiz.packet_count;
uint16_t total_bytes_written = 0;
// Process every single packet (only whole packets can be written to fifo)
for (uint16_t i = 0; i < remain_packets; i++) {
tsiz.value = epin->tsiz;
const uint16_t remain_bytes = (uint16_t)tsiz.xfer_size;
const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
// Check if dtxfsts has enough space available
if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
break;
}
// Push packet to Tx-FIFO
volatile uint32_t *tx_fifo = dwc2->fifo[epnum];
if (xfer->ff) {
tu_hwfifo_write_from_fifo(tx_fifo, xfer->ff, xact_bytes, NULL);
total_bytes_written += xact_bytes;
} else {
tu_hwfifo_write(tx_fifo, xfer->buffer, xact_bytes, NULL);
xfer->buffer += xact_bytes;
total_bytes_written += xact_bytes;
}
}
return total_bytes_written;
}
// Process shared receive FIFO, this interrupt is only used in Slave mode
static void handle_rxflvl_irq(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);

39
src/tusb_option.h
View File

@ -268,16 +268,7 @@
//--------------------------------------------------------------------+
//------------- DWC2 -------------//
// Slave mode for device
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT 1
#endif
#define CFG_TUD_DWC2_SLAVE_ENABLE CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
#endif
// DMA for device
// DMA mode for device
#ifndef CFG_TUD_DWC2_DMA_ENABLE
#ifndef CFG_TUD_DWC2_DMA_ENABLE_DEFAULT
#define CFG_TUD_DWC2_DMA_ENABLE_DEFAULT 0
@ -286,16 +277,16 @@
#define CFG_TUD_DWC2_DMA_ENABLE CFG_TUD_DWC2_DMA_ENABLE_DEFAULT
#endif
// Slave mode for host
#ifndef CFG_TUH_DWC2_SLAVE_ENABLE
#ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT 1
// Slave mode for device
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE // disabled if DMA is enabled
#endif
#define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
#define CFG_TUD_DWC2_SLAVE_ENABLE CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
#endif
// DMA for host
// DMA mode for host
#ifndef CFG_TUH_DWC2_DMA_ENABLE
#ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0
@ -304,14 +295,18 @@
#define CFG_TUH_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
#endif
#if defined(TUP_USBIP_DWC2)
#if CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
// Slave mode for host
#ifndef CFG_TUH_DWC2_SLAVE_ENABLE
#ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE // disabled if DMA is enabled
#endif
#if CFG_TUH_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUH_EDPT_DEDICATED_HWFIFO 1
#endif
#define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
#endif
#if defined(TUP_USBIP_DWC2)
#define CFG_TUD_EDPT_DEDICATED_HWFIFO CFG_TUD_DWC2_SLAVE_ENABLE
#define CFG_TUH_EDPT_DEDICATED_HWFIFO CFG_TUH_DWC2_SLAVE_ENABLE
#define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 4 // 32bit access
#define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 0 // fixed hwfifo address