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Merge pull request #3476 from hathach/dwc2_vbus

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DWC2 Vbus sensing enhancement
This commit is contained in:
Ha Thach
2026-02-13 23:46:36 +07:00
committed by GitHub
parent d13284d02d f0b44ec615
commit da10280611
56 changed files with 1090 additions and 374 deletions
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8
hw/bsp/stm32f2/family.c
View File

@ -31,7 +31,6 @@
#include "stm32f2xx_hal.h"
#include "bsp/board_api.h"
#include "board.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
@ -105,9 +104,12 @@ void board_init(void) {
/* Enable USB FS Clocks */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
#if CFG_TUD_ENABLED
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = true;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
}
//--------------------------------------------------------------------+

10
hw/bsp/stm32f4/boards/feather_stm32f405/board.h
View File

@ -43,6 +43,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOC,
@ -106,14 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART3_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

10
hw/bsp/stm32f4/boards/pyboardv11/board.h
View File

@ -43,6 +43,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOB,
@ -106,14 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

11
hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
View File

@ -44,6 +44,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 0
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOC,
@ -107,15 +109,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
// Blackpill doesn't use VBUS sense (B device) explicitly disable it
if (rhport == 0) {
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

11
hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
View File

@ -44,6 +44,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 0
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOA,
@ -106,15 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Black F407VET6 doesn't use VBUS sense (B device) explicitly disable it
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

10
hw/bsp/stm32f4/boards/stm32f407disco/board.h
View File

@ -46,6 +46,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOD,
@ -114,14 +116,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

11
hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
View File

@ -43,6 +43,8 @@
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define VBUS_SENSE_EN 0
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOC,
@ -106,15 +108,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
// Blackpill doesn't use VBUS sense (B device) explicitly disable it
if (rhport == 0) {
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
(void) rhport; (void) state;
}

10
hw/bsp/stm32f4/boards/stm32f411disco/board.h
View File

@ -44,6 +44,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOD,
@ -111,14 +113,6 @@ static inline void board_clock_init(void) {
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
// Enable VBUS sense (B device) via pin PA9
if (rhport == 0) {
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

9
hw/bsp/stm32f4/boards/stm32f412disco/board.h
View File

@ -45,6 +45,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOE,
@ -127,13 +129,6 @@ static inline void board_clock_init(void) {
__HAL_RCC_USART2_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

9
hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
View File

@ -45,6 +45,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOB,
@ -128,13 +130,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART3_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

10
hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
View File

@ -46,6 +46,8 @@
#define PINID_UART_RX 3
#define PINID_VBUS0_EN 4
#define VBUS_SENSE_EN 1
static board_pindef_t board_pindef[] = {
{ // LED
.port = GPIOB,
@ -117,14 +119,6 @@ static inline void board_clock_init(void)
__HAL_RCC_USART3_CLK_ENABLE();
}
static inline void board_vbus_sense_init(uint8_t rhport) {
if (rhport == 0) {
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
}
static inline void board_vbus_set(uint8_t rhport, bool state) {
if (rhport == 0) {
board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];

7
hw/bsp/stm32f4/family.c
View File

@ -180,11 +180,14 @@ void board_init(void) {
#endif
#if CFG_TUD_ENABLED
board_vbus_sense_init(BOARD_TUD_RHPORT);
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(BOARD_TUD_RHPORT, TUD_CFGID_DWC2, &cfg);
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, true);
board_vbus_set(BOARD_TUH_RHPORT, true);
#endif
}

2
hw/bsp/stm32f7/boards/stm32f723disco/board.h
View File

@ -41,7 +41,7 @@
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 1
#define PINID_LED 0
#define PINID_BUTTON 1

4
hw/bsp/stm32f7/boards/stm32f746disco/board.h
View File

@ -40,8 +40,8 @@
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 1
#define PINID_LED 0
#define PINID_BUTTON 1

36
hw/bsp/stm32f7/family.c
View File

@ -154,18 +154,14 @@ void board_init(void) {
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
//------------- rhport1: OTG_HS -------------//
#ifdef USB_HS_PHYC
// MCU with built-in HS PHY such as F723, F733, F730
@ -178,9 +174,6 @@ void board_init(void) {
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
// Enable HS VBUS sense (B device) via pin PB13
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
/* Configure OTG-HS ID pin */
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
@ -243,17 +236,16 @@ void board_init(void) {
__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
#if OTG_HS_VBUS_SENSE
#error OTG HS VBUS Sense enabled is not implemented
#else
// No VBUS sense
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
tud_configure(1, TUD_CFGID_DWC2, &cfg);
#endif
// Turn off device vbus
#if CFG_TUD_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
// Turn on host vbus
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUH_RHPORT, true);

2
hw/bsp/stm32h7/boards/stm32h743eval/board.h
View File

@ -44,7 +44,7 @@
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 1
// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
#define ULPI_PINS \

2
hw/bsp/stm32h7/boards/stm32h747disco/board.h
View File

@ -42,7 +42,7 @@
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 1
// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
#define ULPI_PINS \

42
hw/bsp/stm32h7/family.c
View File

@ -180,18 +180,14 @@ void board_init(void) {
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
//------------- USB HS -------------//
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
// Despite being call USB2_OTG
@ -216,28 +212,24 @@ void board_init(void) {
__HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE();
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
#if OTG_HS_VBUS_SENSE
#error OTG HS VBUS Sense enabled is not implemented
#else
// No VBUS sense
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif
// Force device mode
USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
tud_configure(1, TUD_CFGID_DWC2, &cfg);
#endif
#endif
HAL_PWREx_EnableUSBVoltageDetector();
board_init2(); // optional init
// Turn off device vbus
#if CFG_TUD_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
// Turn on host vbus
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUH_RHPORT, 1);
board_vbus_set(BOARD_TUH_RHPORT, true);
#endif
}

2
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
View File

@ -2,6 +2,8 @@ set(MCU_VARIANT stm32h7s3xx)
set(JLINK_DEVICE stm32h7s3l8)
set(LD_FILE_Clang ${LD_FILE_GNU})
set(RHPORT_DEVICE 1)
set(RHPORT_HOST 1)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC

2
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
View File

@ -44,7 +44,7 @@
#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define PINID_LED 0

51
hw/bsp/stm32h7rs/family.c
View File

@ -356,17 +356,14 @@ void board_init(void) {
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PM14
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device)
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
#endif
//------------- USB HS -------------//
@ -382,33 +379,31 @@ void board_init(void) {
#if OTG_HS_VBUS_SENSE
// Configure VBUS Pin
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PM9
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
GPIO_InitTypeDef GPIO_InitStruct2;
GPIO_InitStruct2.Pin = GPIO_PIN_8;
GPIO_InitStruct2.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct2.Pull = GPIO_NOPULL;
GPIO_InitStruct2.Alternate = GPIO_AF10_OTG_HS;
HAL_GPIO_Init(GPIOM, &GPIO_InitStruct2);
#endif
#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
// B-peripheral session valid override enable
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
#else
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN;
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
tud_configure(1, TUD_CFGID_DWC2, &cfg);
#endif
#endif
#endif
board_init2();
// Turn off device vbus
#if CFG_TUD_ENABLED
board_vbus_set(BOARD_TUD_RHPORT, false);
#endif
// Turn on host vbus
#if CFG_TUH_ENABLED
board_vbus_set(BOARD_TUH_RHPORT, 1);
board_vbus_set(BOARD_TUH_RHPORT, true);
#endif
}

2
hw/bsp/stm32h7rs/family.cmake
View File

@ -24,7 +24,7 @@ if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 1)
endif ()
if (NOT DEFINED RHPORT_HOST)
set(RHPORT_HOST 1)
set(RHPORT_HOST 0)
endif ()
if (NOT DEFINED RHPORT_SPEED)

11
hw/bsp/stm32l4/boards/stm32l476disco/board.h
View File

@ -51,6 +51,8 @@
#define UART_TX_PIN GPIO_PIN_5
#define UART_RX_PIN GPIO_PIN_6
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -128,15 +130,6 @@ static inline void board_clock_init(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
}
static inline void board_vbus_sense_init(void)
{
// L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
// Disable VBUS Sense and force device mode
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
}
#ifdef __cplusplus
}
#endif

8
hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
View File

@ -52,6 +52,8 @@
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 1
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -145,12 +147,6 @@ static inline void board_clock_init(void)
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
}
static inline void board_vbus_sense_init(void)
{
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
#ifdef __cplusplus
}
#endif

8
hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
View File

@ -51,6 +51,8 @@
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 1
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -129,12 +131,6 @@ static inline void board_clock_init(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
}
static inline void board_vbus_sense_init(void)
{
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
#ifdef __cplusplus
}
#endif

8
hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
View File

@ -51,6 +51,8 @@
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 1
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -129,12 +131,6 @@ static inline void board_clock_init(void)
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
}
static inline void board_vbus_sense_init(void)
{
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
#ifdef __cplusplus
}
#endif

10
hw/bsp/stm32l4/family.c
View File

@ -170,10 +170,16 @@ void board_init(void) {
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
#endif
/* Enable USB FS Clocks */
#if defined(USB_OTG_FS)
/* Enable USB FS Clocks */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
board_vbus_sense_init();
#if CFG_TUD_ENABLED
/* Set Vbus sense */
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
#else
__HAL_RCC_USB_CLK_ENABLE();
#endif

2
hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
View File

@ -1,5 +1,5 @@
set(MCU_VARIANT stm32n657xx)
set(JLINK_DEVICE stm32n6xx)
set(JLINK_DEVICE stm32n657x0)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)

41
hw/bsp/stm32n6/boards/stm32n6570dk/board.h
View File

@ -44,17 +44,16 @@ extern "C" {
#define UART_DEV USART1
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
#define BOARD_TUD_RHPORT 1
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 1
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define PINID_LED 0
#define PINID_BUTTON 1
#define PINID_UART_TX 2
#define PINID_UART_RX 3
#define PINID_TCPP0203_EN 4
#define PINID_PWR_USB2 8
static board_pindef_t board_pindef[] = {
{// LED
@ -77,21 +76,22 @@ static board_pindef_t board_pindef[] = {
.port = GPIOA,
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
.active_state = 0},
{
// I2C SCL for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{ // I2C SCL for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// I2C SDA for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{// I2C SDA for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
{// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
},
{// PWR for USB2
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_9, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
}
};
//--------------------------------------------------------------------+
@ -262,9 +262,12 @@ static inline void board_init2(void) {
}
void board_vbus_set(uint8_t rhport, bool state) {
(void) state;
if (rhport == 1) {
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
if (rhport == 0) {
uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
} else if (rhport == 1) {
board_pindef_t *pindef = &board_pindef[PINID_PWR_USB2];
HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state ? GPIO_PIN_SET : GPIO_PIN_RESET);
}
}

9
hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
View File

@ -1,8 +1,15 @@
set(MCU_VARIANT stm32n657xx)
set(JLINK_DEVICE stm32n6xx)
set(JLINK_DEVICE stm32n657x0)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 0)
endif ()
if (NOT DEFINED RHPORT_HOST)
set(RHPORT_HOST 0)
endif ()
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
STM32N657xx

33
hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
View File

@ -44,11 +44,9 @@ extern "C" {
#define UART_DEV USART1
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
#define BOARD_TUD_RHPORT 1
// VBUS Sense detection
#define OTG_FS_VBUS_SENSE 1
#define OTG_HS_VBUS_SENSE 1
#define OTG_FS_VBUS_SENSE 0
#define OTG_HS_VBUS_SENSE 0
#define PINID_LED 0
#define PINID_BUTTON 1
@ -77,20 +75,17 @@ static board_pindef_t board_pindef[] = {
.port = GPIOA,
.pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
.active_state = 0},
{
// I2C SCL for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{// I2C SCL for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// I2C SDA for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
{// I2C SDA for TCPP0203
.port = GPIOB,
.pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
},
{
// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
{// INT for TCPP0203
.port = GPIOD,
.pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
},
};
@ -262,9 +257,9 @@ static inline void board_init2(void) {
}
void board_vbus_set(uint8_t rhport, bool state) {
(void) state;
if (rhport == 1) {
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
if (rhport == 0) {
uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
}
}

5
hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
View File

@ -1,9 +1,12 @@
MCU_VARIANT = stm32n657xx
CFLAGS += -DSTM32N657xx
JLINK_DEVICE = stm32n6xx
JLINK_DEVICE = stm32n657x0
LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
RHPORT_DEVICE ?= 0
RHPORT_HOST ?= 0
# flash target using on-board stlink
flash: flash-stlink

122
hw/bsp/stm32n6/family.c
View File

@ -48,7 +48,8 @@
TU_ATTR_UNUSED static void Error_Handler(void) { }
void HardFault_Handler(void);
static void MPU_Config(void);
static void SystemIsolation_Config(void);
typedef struct {
GPIO_TypeDef* port;
GPIO_InitTypeDef pin_init;
@ -87,20 +88,25 @@ static UART_HandleTypeDef UartHandle = {
// Despite being call USB2_OTG_FS on some MCUs
// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
void USB2_OTG_HS_IRQHandler(void) {
tusb_int_handler(0, true);
tusb_int_handler(1, true);
}
// Despite being call USB1_OTG_HS on some MCUs
// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
void USB1_OTG_HS_IRQHandler(void) {
tusb_int_handler(1, true);
tusb_int_handler(0, true);
}
void board_init(void) {
/* Enable BusFault and SecureFault handlers (HardFault is default) */
SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
MPU_Config();
SystemIsolation_Config();
SCB_EnableICache();
SCB_EnableDCache();
HAL_PWREx_EnableVddA();
HAL_PWREx_EnableVddIO2();
HAL_PWREx_EnableVddIO3();
@ -126,8 +132,6 @@ void board_init(void) {
__HAL_RCC_GPIOP_CLK_ENABLE();
__HAL_RCC_GPIOQ_CLK_ENABLE();
// HAL_ICACHE_Enable();
for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
}
@ -155,7 +159,7 @@ void board_init(void) {
HAL_UART_Init(&UartHandle);
#endif
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_EnableVddUSBVMEN();
@ -196,11 +200,109 @@ void board_init(void) {
/* Peripheral PHY clock enable */
__HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
board_init2();
#if CFG_TUH_ENABLED
#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0
board_vbus_set(BOARD_TUH_RHPORT, 1);
#endif
#endif
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
__HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_EnableVddUSBVMEN();
while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY));
HAL_PWREx_EnableVddUSB();
LL_AHB5_GRP1_ForceReset(0x00800000);
__HAL_RCC_USB2_OTG_HS_FORCE_RESET();
__HAL_RCC_USB2_OTG_HS_PHY_FORCE_RESET();
LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
LL_AHB5_GRP1_ReleaseReset(0x00800000);
/* Peripheral clock enable */
__HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
/* Required few clock cycles before accessing USB PHY Controller Registers */
for (volatile uint32_t i = 0; i < 10; i++) {
__NOP(); // No Operation instruction to create a delay
}
USB2_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
USB2_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
(0x2 << 4) |
(0x1 << 2) |
0x1U;
__HAL_RCC_USB2_OTG_HS_PHY_RELEASE_RESET();
/* Required few clock cycles before Releasing Reset */
for (volatile uint32_t i = 0; i < 10; i++) {
__NOP(); // No Operation instruction to create a delay
}
__HAL_RCC_USB2_OTG_HS_RELEASE_RESET();
/* Peripheral PHY clock enable */
__HAL_RCC_USB2_OTG_HS_PHY_CLK_ENABLE();
#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1
board_vbus_set(BOARD_TUH_RHPORT, 1);
#endif
#endif
board_init2();
}
static void MPU_Config(void)
{
MPU_Region_InitTypeDef default_config = {0};
MPU_Attributes_InitTypeDef attr_config = {0};
uint32_t primask_bit = __get_PRIMASK();
__disable_irq();
/* disable the MPU */
HAL_MPU_Disable();
/* create an attribute configuration for the MPU */
attr_config.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE);
attr_config.Number = MPU_ATTRIBUTES_NUMBER0;
HAL_MPU_ConfigMemoryAttributes(&attr_config);
/* Create a non cacheable region */
/*Normal memory type, code execution allowed */
default_config.Enable = MPU_REGION_ENABLE;
default_config.Number = MPU_REGION_NUMBER0;
default_config.BaseAddress = __NON_CACHEABLE_SECTION_BEGIN;
default_config.LimitAddress = __NON_CACHEABLE_SECTION_END;
default_config.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
default_config.AccessPermission = MPU_REGION_ALL_RW;
default_config.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
default_config.AttributesIndex = MPU_ATTRIBUTES_NUMBER0;
HAL_MPU_ConfigRegion(&default_config);
/* enable the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
/* Exit critical section to lock the system and avoid any issue around MPU mechanisme */
__set_PRIMASK(primask_bit);
}
static void SystemIsolation_Config(void) {
/* set all required IPs as secure privileged */
__HAL_RCC_RIFSC_CLK_ENABLE();
RIMC_MasterConfig_t RIMC_master = {0};
RIMC_master.MasterCID = RIF_CID_1;
RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
/*RIMC configuration*/
HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG1, &RIMC_master);
HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG2, &RIMC_master);
/*RISUP configuration*/
HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG1HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG2HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
}
//--------------------------------------------------------------------+

7
hw/bsp/stm32n6/family.cmake
View File

@ -21,7 +21,7 @@ set(FAMILY_MCUS STM32N6 CACHE INTERNAL "")
# Port & Speed Selection
# ----------------------
if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 1)
set(RHPORT_DEVICE 0)
endif ()
if (NOT DEFINED RHPORT_HOST)
set(RHPORT_HOST 1)
@ -68,6 +68,7 @@ function(family_add_board BOARD_TARGET)
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rif.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@ -80,8 +81,8 @@ function(family_add_board BOARD_TARGET)
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
BOARD_TUH_RHPORT=${RHPORT_HOST}
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
SEGGER_RTT_SECTION="noncacheable_buffer"
BUFFER_SIZE_UP=0x3000
SEGGER_RTT_SECTION=".noncacheable"
BUFFER_SIZE_UP=0x4000
)
update_board(${BOARD_TARGET})

6
hw/bsp/stm32n6/family.mk
View File

@ -12,7 +12,7 @@ CPU_CORE ?= cortex-m55
# ----------------------
# Port & Speed Selection
# ----------------------
RHPORT_DEVICE ?= 1
RHPORT_DEVICE ?= 0
RHPORT_HOST ?= 1
ifndef RHPORT_DEVICE_SPEED
@ -32,8 +32,8 @@ CFLAGS += \
-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
-DBUFFER_SIZE_UP=0x3000 \
-DSEGGER_RTT_SECTION="\".noncacheable\"" \
-DBUFFER_SIZE_UP=0x4000 \
# GCC Flags
CFLAGS_GCC += \

12
hw/bsp/stm32n6/setup_iar.mac Normal file
View File

@ -0,0 +1,12 @@
/* Called once after the target reset. */
execUserReset()
{
/* Re-load image as AIXRAM2 is erased after CPU reset */
__loadImage("$EXE_DIR$\\$TARGET_BNAME$.hex", 0, 0);
__restoreSoftwareBreakpoints();
#PC = __readMemory32(0x34180404, "Memory");
#SP = 0x341FFD00;
}

362
hw/bsp/stm32n6/stm32n6.jdebug Normal file
View File

@ -0,0 +1,362 @@
/*********************************************************************
* (c) SEGGER Microcontroller GmbH *
* The Embedded Experts *
* www.segger.com *
**********************************************************************
File :
Created : 31. Jan 2026 16:34
Ozone Version : V3.40e
*/
/*********************************************************************
*
* OnProjectLoad
*
* Function description
* Project load routine. Required.
*
**********************************************************************
*/
void OnProjectLoad (void) {
//
// Dialog-generated settings
//
Project.SetDevice ("STM32N657X0");
Project.SetHostIF ("USB", "");
Project.SetTargetIF ("SWD");
Project.SetTIFSpeed ("4 MHz");
Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M55F.svd");
//
// User settings
//
File.Open ("$(ProjectDir)/../../../examples/device/cdc_msc/build/stm32n6570dk/RelWithDebInfo/cdc_msc.elf");
}
/*********************************************************************
*
* OnStartupComplete
*
* Function description
* Called when program execution has reached/passed
* the startup completion point. Optional.
*
**********************************************************************
*/
//void OnStartupComplete (void) {
//}
/*********************************************************************
*
* TargetReset
*
* Function description
* Replaces the default target device reset routine. Optional.
*
* Notes
* This example demonstrates the usage when
* debugging an application in RAM on a Cortex-M target device.
*
**********************************************************************
*/
//void TargetReset (void) {
//
// unsigned int SP;
// unsigned int PC;
// unsigned int VectorTableAddr;
//
// VectorTableAddr = Elf.GetBaseAddr();
// //
// // Set up initial stack pointer
// //
// if (VectorTableAddr != 0xFFFFFFFF) {
// SP = Target.ReadU32(VectorTableAddr);
// Target.SetReg("SP", SP);
// }
// //
// // Set up entry point PC
// //
// PC = Elf.GetEntryPointPC();
//
// if (PC != 0xFFFFFFFF) {
// Target.SetReg("PC", PC);
// } else if (VectorTableAddr != 0xFFFFFFFF) {
// PC = Target.ReadU32(VectorTableAddr + 4);
// Target.SetReg("PC", PC);
// } else {
// Util.Error("Project file error: failed to set entry point PC", 1);
// }
//}
/*********************************************************************
*
* BeforeTargetReset
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetReset (void) {
//}
/*********************************************************************
*
* AfterTargetReset
*
* Function description
* Event handler routine. Optional.
* The default implementation initializes SP and PC to reset values.
**
**********************************************************************
*/
void AfterTargetReset (void) {
_SetupTarget();
}
/*********************************************************************
*
* DebugStart
*
* Function description
* Replaces the default debug session startup routine. Optional.
*
**********************************************************************
*/
//void DebugStart (void) {
//}
/*********************************************************************
*
* TargetConnect
*
* Function description
* Replaces the default target IF connection routine. Optional.
*
**********************************************************************
*/
//void TargetConnect (void) {
//}
/*********************************************************************
*
* BeforeTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetConnect (void) {
//}
/*********************************************************************
*
* AfterTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetConnect (void) {
//}
/*********************************************************************
*
* TargetDownload
*
* Function description
* Replaces the default program download routine. Optional.
*
**********************************************************************
*/
//void TargetDownload (void) {
//}
/*********************************************************************
*
* BeforeTargetDownload
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDownload (void) {
//}
/*********************************************************************
*
* AfterTargetDownload
*
* Function description
* Event handler routine. Optional.
* The default implementation initializes SP and PC to reset values.
*
**********************************************************************
*/
void AfterTargetDownload (void) {
//_SetupTarget();
}
/*********************************************************************
*
* BeforeTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetHalt
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetHalt (void) {
//}
/*********************************************************************
*
* BeforeTargetResume
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetResume (void) {
//}
/*********************************************************************
*
* OnSnapshotLoad
*
* Function description
* Called upon loading a snapshot. Optional.
*
* Additional information
* This function is used to restore the target state in cases
* where values cannot simply be written to the target.
* Typical use: GPIO clock needs to be enabled, before
* GPIO is configured.
*
**********************************************************************
*/
//void OnSnapshotLoad (void) {
//}
/*********************************************************************
*
* OnSnapshotSave
*
* Function description
* Called upon saving a snapshot. Optional.
*
* Additional information
* This function is usually used to save values of the target
* state which can either not be trivially read,
* or need to be restored in a specific way or order.
* Typically use: Memory Mapped Registers,
* such as PLL and GPIO configuration.
*
**********************************************************************
*/
//void OnSnapshotSave (void) {
//}
/*********************************************************************
*
* OnError
*
* Function description
* Called when an error occurred. Optional.
*
**********************************************************************
*/
//void OnError (void) {
//}
/*********************************************************************
*
* AfterProjectLoad
*
* Function description
* After Project load routine. Optional.
*
**********************************************************************
*/
//void AfterProjectLoad (void) {
//}
/*********************************************************************
*
* OnDebugStartBreakSymbolReached
*
* Function description
* Called when program execution has reached/passed
* the symbol to be breaked at during debug start. Optional.
*
**********************************************************************
*/
//void OnDebugStartBreakSymReached (void) {
//}
/*********************************************************************
*
* _SetupTarget
*
* Function description
* Setup the target.
* Called by AfterTargetReset() and AfterTargetDownload().
*
* Auto-generated function. May be overridden by Ozone.
*
**********************************************************************
*/
void _SetupTarget(void) {
unsigned int SP;
unsigned int PC;
unsigned int VectorTableAddr;
Debug.Download();
Debug.Halt();
VectorTableAddr = Elf.GetBaseAddr();
//
// Set up initial stack pointer
//
SP = Target.ReadU32(VectorTableAddr);
if (SP != 0xFFFFFFFF) {
Target.SetReg("SP", SP);
}
//
// Set up entry point PC
//
PC = Elf.GetEntryPointPC();
if (PC != 0xFFFFFFFF) {
Target.SetReg("PC", PC);
} else {
Util.Error("Project script error: failed to set up entry point PC", 1);
}
}

2
hw/bsp/stm32n6/stm32n6xx_hal_conf.h
View File

@ -67,7 +67,7 @@
/*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_PSSI_MODULE_ENABLED */
/*#define HAL_RAMCFG_MODULE_ENABLED */
/*#define HAL_RIF_MODULE_ENABLED */
#define HAL_RIF_MODULE_ENABLED
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */

5
hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
View File

@ -55,6 +55,8 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_9
#define UART_RX_PIN GPIO_PIN_10
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -110,6 +112,9 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
}
#ifdef __cplusplus
}
#endif

3
hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
View File

@ -110,6 +110,9 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
}
#ifdef __cplusplus
}
#endif

5
hw/bsp/stm32u5/boards/stm32u575eval/board.h
View File

@ -56,6 +56,8 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_9
#define UART_RX_PIN GPIO_PIN_10
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -111,6 +113,9 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
}
#ifdef __cplusplus
}
#endif

102
hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
View File

@ -37,6 +37,8 @@ extern "C"
{
#endif
#include "stm32u5xx_ll_tim.h"
// LED GREEN
#define LED_PORT GPIOC
#define LED_PIN GPIO_PIN_7
@ -55,6 +57,8 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_7
#define UART_RX_PIN GPIO_PIN_8
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
@ -110,6 +114,104 @@ static void SystemClock_Config(void) {
static void SystemPower_Config(void) {
}
static inline void board_vbus_sense_init(void) {
/* ADC config */
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
__HAL_RCC_ADC12_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
ADC_HandleTypeDef hadc1;
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc1.Init.Resolution = ADC_RESOLUTION_14B;
hadc1.Init.GainCompensation = 0;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc1.Init.LowPowerAutoWait = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc1.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc1) != HAL_OK) {
Error_Handler();
}
ADC_ChannelConfTypeDef sConfig = {0};
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
Error_Handler();
}
HAL_NVIC_EnableIRQ(ADC1_IRQn);
/* TIM1 init for TRGO */
__HAL_RCC_TIM1_CLK_ENABLE();
TIM_HandleTypeDef htim1;
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
htim1.Instance = TIM1;
htim1.Init.Prescaler = 159;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 999;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
Error_Handler();
}
LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
HAL_ADC_Start_IT(&hadc1);
HAL_TIM_Base_Start(&htim1);
}
void ADC1_IRQHandler(void) {
if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
/* Clear flag ADC group regular end of unitary conversion */
LL_ADC_ClearFlag_EOC(ADC1);
/* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
* with R1 = 330kOhm and R2 = 50kOhm
*/
const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
if((ADC1->DR > threshold) && (USB_OTG_FS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
} else {
USB_OTG_FS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
}
}
if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
/* Clear flag ADC group regular overrun */
LL_ADC_ClearFlag_OVR(ADC1);
}
}
#ifdef __cplusplus
}
#endif

106
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
View File

@ -37,6 +37,8 @@ extern "C"
{
#endif
#include "stm32u5xx_ll_tim.h"
// LED GREEN
#define LED_PORT GPIOC
#define LED_PIN GPIO_PIN_7
@ -55,11 +57,13 @@ extern "C"
#define UART_TX_PIN GPIO_PIN_9
#define UART_RX_PIN GPIO_PIN_10
#define VBUS_SENSE_EN 0
//--------------------------------------------------------------------+
// RCC Clock
//--------------------------------------------------------------------+
static void SystemClock_Config(void) {
static inline void SystemClock_Config(void) {
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
@ -128,7 +132,7 @@ static void SystemClock_Config(void) {
}
}
static void SystemPower_Config(void) {
static inline void SystemPower_Config(void) {
HAL_PWREx_EnableVddIO2();
/*
@ -141,7 +145,105 @@ static void SystemPower_Config(void) {
/* USER CODE END PWR */
}
static inline void board_vbus_sense_init(void) {
/* ADC config */
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
__HAL_RCC_ADC12_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
ADC_HandleTypeDef hadc1;
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc1.Init.Resolution = ADC_RESOLUTION_14B;
hadc1.Init.GainCompensation = 0;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc1.Init.LowPowerAutoWait = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc1.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc1) != HAL_OK) {
Error_Handler();
}
ADC_ChannelConfTypeDef sConfig = {0};
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
Error_Handler();
}
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
/* TIM1 init for TRGO */
__HAL_RCC_TIM1_CLK_ENABLE();
TIM_HandleTypeDef htim1;
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
htim1.Instance = TIM1;
htim1.Init.Prescaler = 159;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 999;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
Error_Handler();
}
LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
HAL_ADC_Start_IT(&hadc1);
HAL_TIM_Base_Start(&htim1);
}
void ADC1_2_IRQHandler(void) {
if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
/* Clear flag ADC group regular end of unitary conversion */
LL_ADC_ClearFlag_EOC(ADC1);
/* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
* with R1 = 330kOhm and R2 = 50kOhm
*/
const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
if((ADC1->DR > threshold) && (USB_OTG_HS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
} else {
USB_OTG_HS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
}
}
if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
/* Clear flag ADC group regular overrun */
LL_ADC_ClearFlag_OVR(ADC1);
}
}
#ifdef __cplusplus
}
#endif

30
hw/bsp/stm32u5/family.c
View File

@ -179,18 +179,14 @@ void board_init(void) {
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
// Enable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
// Disable VBUS sense (B device) via pin PA9
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif // vbus sense
#if CFG_TUD_ENABLED
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
/* Enable USB power on Pwrctrl CR2 register */
HAL_PWREx_EnableVddUSB();
@ -218,13 +214,15 @@ void board_init(void) {
/*Configuring the SYSCFG registers OTG_HS PHY*/
HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
// Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
#if CFG_TUD_ENABLED
tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
cfg.vbus_sensing = VBUS_SENSE_EN;
tud_configure(0, TUD_CFGID_DWC2, &cfg);
#endif
#endif // USB_OTG_FS
/* Non-standard VBus sense settings */
board_vbus_sense_init();
}
//--------------------------------------------------------------------+

5
hw/bsp/stm32u5/family.cmake
View File

@ -45,6 +45,9 @@ function(family_add_board BOARD_TARGET)
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc_ex.c
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@ -96,7 +99,7 @@ function(family_configure_example TARGET RTOS)
endif ()
if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes -Wno-self-assign")
endif ()
set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
SKIP_LINTING ON

6
hw/bsp/stm32u5/family.mk
View File

@ -16,6 +16,7 @@ CFLAGS_GCC += \
-Wno-error=undef \
-Wno-error=unused-parameter \
-Wno-error=type-limits \
-Wno-self-assign \
ifeq ($(TOOLCHAIN),gcc)
CFLAGS_GCC += -Wno-error=maybe-uninitialized
@ -35,7 +36,10 @@ SRC_C += \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c
ifneq ($(filter stm32u545xx stm32u535xx,$(MCU_VARIANT)),)
SRC_C += \

4
hw/bsp/stm32u5/stm32u5xx_hal_conf.h
View File

@ -36,7 +36,7 @@
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_MDF_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CORDIC_MODULE_ENABLED */
@ -76,7 +76,7 @@
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
/*#define HAL_TSC_MODULE_ENABLED */
/*#define HAL_RAMCFG_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED

9
hw/bsp/stm32wba/family.c
View File

@ -172,14 +172,7 @@ void board_init(void) {
// Configuring the SYSCFG registers OTG_HS PHY
SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN;
// Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
// B-peripheral session valid override enable
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
#endif // USB_OTG_FS
#endif // USB_OTG_HS
}
void board_led_write(bool state) { HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); }

5
src/device/usbd.h
View File

@ -41,8 +41,13 @@ enum {
typedef struct {
uint16_t bm_double_buffered; // bitmap of IN endpoints to be double buffered, only effective for bulk endpoints
bool vbus_sensing; // Vbus pin is used for device connection detection, mandatory for tud_umount_cb()
} tud_configure_dwc2_t;
#ifndef CFG_TUD_CONFIGURE_DWC2_DEFAULT
#define CFG_TUD_CONFIGURE_DWC2_DEFAULT {.bm_double_buffered = 0, .vbus_sensing = CFG_TUD_VBUS_DETECT_HW}
#endif
typedef union {
tud_configure_dwc2_t dwc2;
} tud_configure_param_t;

20
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@ -77,9 +77,7 @@ CFG_TUD_MEM_SECTION static struct {
TUD_EPBUF_DEF(setup_packet, 8);
} _dcd_usbbuf;
static tud_configure_dwc2_t _tud_cfg = {
.bm_double_buffered = 0
};
static tud_configure_dwc2_t _tud_cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) {
#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
@ -472,12 +470,15 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
// Force device mode
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
// Clear A override, force B Valid
dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
// OTG Ctrl
uint32_t gotgctl = dwc2->gotgctl & ~GOTGCTL_AVALOEN; // Clear A-override
if (!_tud_cfg.vbus_sensing) {
gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; // force B Valid if not sensing VBus
}
dwc2->gotgctl = gotgctl;
#if CFG_TUSB_MCU == OPT_MCU_STM32N6
// No hardware detection of Vbus B-session is available on the STM32N6
dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL;
#ifdef TUP_USBIP_DWC2_STM32
dwc2_stm32_gccfg_cfg(dwc2, _tud_cfg.vbus_sensing, false);
#endif
// Enable required interrupts
@ -780,7 +781,7 @@ static void handle_bus_reset(uint8_t rhport) {
dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
}
dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT | GINTMSK_IISOIXFRM;
dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_OEPINT | GINTMSK_IEPINT | GINTMSK_IISOIXFRM;
}
static void handle_enum_done(uint8_t rhport) {
@ -1180,6 +1181,7 @@ void dcd_int_handler(uint8_t rhport) {
const uint32_t otg_int = dwc2->gotgint;
if (otg_int & GOTGINT_SEDET) {
dwc2->gintmsk &= ~GINTMSK_OTGINT;
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
}

116
src/portable/synopsys/dwc2/dwc2_info.md
View File

@ -1,58 +1,58 @@
| | AT32 F405 FS | AT32 F405 HS | AT32 F415 | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | nRF54 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 |
|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------|
| GUID | 0x00002000 | 0x00000000 | 0x00001000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 |
| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54430A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 |
| - specs version | 4.00a | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 4.30a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W |
| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0xAA555000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DCD00 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x228BFC72 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 |
| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP |
| - arch | Slave only | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only |
| - single_point | hub | hub | hub | hub | hub | n/a | hub | n/a | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub |
| - hs_phy_type | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a | UTMI+/ULPI | UTMI+ | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a |
| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | n/a | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a |
| - num_dev_ep | 7 | 7 | 3 | 7 | 6 | 6 | 15 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
| - num_host_ch | 15 | 15 | 7 | 7 | 13 | 7 | 15 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 |
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - nptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 |
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x020004E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x0BEAC0E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 |
| - xfer_size_width | 8 | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 |
| - packet_size_width | 6 | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 |
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
| - optional_feature_removed | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| - dfifo_depth | 512 | 1008 | 512 | 4080 | 498 | 200 | 896 | 3050 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 |
| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x0000000F | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x1E10AA60 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 |
| - num_dev_period_in_ep | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - partial_powerdown | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - ahb_freq_min | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit |
| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - iddg_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - vbus_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - a_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - b_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - session_end_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| - dedicated_fifos | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - num_dev_in_eps | 7 | 7 | 0 | 7 | 6 | 4 | 7 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| | AT32 F405 FS | AT32 F405 HS | AT32 F415 | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | nRF54 | ST F407/429 HS | ST F207/F407/411/429 FS | ST L476 FS | ST F412/76x FS | ST F76x HS | ST H743/H750 | ST F723/L4P5 FS | ST F723 HS | ST H7RS FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 |
|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:-----------------|:--------------------------|:-------------|:-----------------|:-------------|:---------------|:------------------|:-------------|:-------------|:---------------------|:-------------|:------------|
| GUID | 0x00002000 | 0x00000000 | 0x00001000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00002000 | 0x00002100 | 0x00002300 | 0x00003000 | 0x00003100 | 0x00004000 | 0x00005000 | 0x00AEC000 | 0x00001000 |
| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54430A | 0x4F54281A | 0x4F54281A | 0x4F54310A | 0x4F54320A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54411A | 0x4F54411A | 0x4F54292A | 0x00000000 |
| - specs version | 4.00a | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 4.30a | 2.81a | 2.81a | 3.10a | 3.20a | 3.20a | 3.30a | 3.30a | 3.30a | 4.11a | 4.11a | 2.92a | 0.00W |
| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0xAA555000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DCD00 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x228BFC72 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229ED520 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x229FE1D0 | 0x229ED522 | 0x228FE052 | 0x228F5930 | 0x00000000 |
| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | noHNP noSRP | HNP SRP | HNP SRP |
| - arch | Slave only | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | Slave only | Slave only | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | DMA internal | Slave only |
| - single_point | hub | hub | hub | hub | hub | n/a | hub | n/a | hub | n/a | n/a | n/a | hub | hub | n/a | hub | n/a | hub | n/a | hub |
| - hs_phy_type | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a | UTMI+/ULPI | UTMI+ | ULPI | n/a | n/a | n/a | ULPI | ULPI | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a |
| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | n/a | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a |
| - num_dev_ep | 7 | 7 | 3 | 7 | 6 | 6 | 15 | 15 | 5 | 3 | 5 | 5 | 8 | 8 | 5 | 8 | 5 | 8 | 6 | 0 |
| - num_host_ch | 15 | 15 | 7 | 7 | 13 | 7 | 15 | 15 | 11 | 7 | 11 | 11 | 15 | 15 | 11 | 15 | 11 | 15 | 13 | 0 |
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - nptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 |
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x020004E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x0BEAC0E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03EED2E8 | 0x020081E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 |
| - xfer_size_width | 8 | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 |
| - packet_size_width | 6 | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 |
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| - optional_feature_removed | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| - dfifo_depth | 512 | 1008 | 512 | 4080 | 498 | 200 | 896 | 3050 | 1012 | 512 | 512 | 512 | 1006 | 952 | 512 | 1006 | 512 | 952 | 634 | 0 |
| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x0000000F | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x1E10AA60 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0x23F00030 | 0x1610B230 | 0xE2103E30 | 0xDBF08030 | 0x00000000 |
| - num_dev_period_in_ep | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - partial_powerdown | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - ahb_freq_min | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit |
| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - iddg_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - vbus_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - a_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - b_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - session_end_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| - dedicated_fifos | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| - num_dev_in_eps | 7 | 7 | 0 | 7 | 6 | 4 | 7 | 7 | 5 | 3 | 5 | 5 | 8 | 8 | 5 | 8 | 5 | 8 | 6 | 0 |
| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |

10
src/portable/synopsys/dwc2/dwc2_info.py
View File

@ -16,14 +16,16 @@ dwc2_reg_value = {
'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030],
'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030],
'nRF54': [0, 0x4F54430A, 0xAA555000, 0x228BFC72, 0x0BEAC0E8, 0x1E10AA60],
'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
# ST sort by GUID
'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030],
'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030],
'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
'ST H7RS FS': [0x4000, 0x4F54411A, 0, 0x229ED522, 0x20081E8, 0x1610B230],
'ST U5A5/H7RS/N6 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030],
'GD32VF103': [0x1000, 0, 0, 0, 0, 0],

74
src/portable/synopsys/dwc2/dwc2_stm32.h
View File

@ -85,8 +85,11 @@ extern "C" {
#define EP_MAX_HS 9
#define EP_FIFO_SIZE_HS 4096
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_BASE
#define OTG_HS_IRQn USB1_OTG_HS_IRQn
#define USB_OTG_FS_PERIPH_BASE USB1_OTG_HS_BASE
#define OTG_FS_IRQn USB1_OTG_HS_IRQn
#define USB_OTG_HS_PERIPH_BASE USB2_OTG_HS_BASE
#define OTG_HS_IRQn USB2_OTG_HS_IRQn
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
#include "stm32f7xx.h"
@ -300,6 +303,66 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
}
}
//------------- GCCFG configuration -------------//
static inline void dwc2_stm32_gccfg_cfg(dwc2_regs_t* dwc2, bool vbus_sensing, bool is_host) {
if (is_host) {
vbus_sensing = false;
}
uint32_t gccfg = dwc2->stm32_gccfg;
if (dwc2->guid < 0x2000) {
// use VBUSASEN/VBUSBSEN/NOVBUSSENS bits
if (is_host) {
gccfg &= ~(STM32_GCCFG_NOVBUSSENS | STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
} else {
if (vbus_sensing) {
gccfg &= ~STM32_GCCFG_NOVBUSSENS;
gccfg |= STM32_GCCFG_VBUSBSEN;
} else {
gccfg |= STM32_GCCFG_NOVBUSSENS;
gccfg &= ~(STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
}
}
} else if (dwc2->guid < 0x5000) {
// the later version uses VBDEN with battery charging detection
if (vbus_sensing) {
gccfg |= STM32_GCCFG_VBDEN;
} else {
gccfg &= ~STM32_GCCFG_VBDEN;
}
} else {
// from 0x5000 ST seems to use femtoPHY for UTMI+ HS PHY. Which use VBVALEXTOEN and VBVALOVAL for software override
// external VBUS sensing
// Note: N6 does not support hardware VBUS sensing, so the software override is always active. Therefore, VBDEN and
// VBVALEXTOEN are not available
#if CFG_TUSB_MCU == OPT_MCU_STM32N6
if (is_host) {
gccfg |= STM32_GCCFG_PULLDOWNEN;
gccfg &= ~(STM32_GCCFG_VBVALOVAL);
} else {
gccfg &= ~STM32_GCCFG_PULLDOWNEN;
gccfg |= STM32_GCCFG_VBVALOVAL;
}
#else
if (is_host) {
gccfg |= STM32_GCCFG_PULLDOWNEN;
gccfg &= ~(STM32_GCCFG_VBDEN | STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
} else {
gccfg &= ~STM32_GCCFG_PULLDOWNEN;
if (vbus_sensing) {
gccfg |= STM32_GCCFG_VBDEN;
gccfg &= ~(STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
} else {
gccfg &= ~STM32_GCCFG_VBDEN;
gccfg |= STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL;
}
}
#endif
}
dwc2->stm32_gccfg = gccfg;
}
//------------- DCache -------------//
#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
@ -321,8 +384,13 @@ static mem_region_t uncached_regions[] = {
// DTCM (although USB DMA can't transfer to/from DTCM)
{.start = 0x20000000, .end = 0x2002FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
// DTCM
// DTCM
{.start = 0x20000000, .end = 0x2000FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32N6
// DTCM NS
{.start = 0x20000000, .end = 0x2003FFFF},
// DTCM S
{.start = 0x30000000, .end = 0x3003FFFF},
#else
#error "Cache maintenance is not supported yet"
#endif

42
src/portable/synopsys/dwc2/dwc2_type.h
View File

@ -1650,24 +1650,38 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000
#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable
// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
//#define STM32_GCCFG_SDEN_Pos (22U)
//#define STM32_GCCFG_SDEN_Msk (0x1U << STM32_GCCFG_SDEN_Pos) // 0x00400000
//#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (PD) mode enable
// GUID < 0x2000: VBUSASEN, VBUSBSEN, NOVBUSSENS bits
#define STM32_GCCFG_VBUSASEN_Pos (18U)
#define STM32_GCCFG_VBUSASEN_Msk (0x1UL << STM32_GCCFG_VBUSASEN_Pos) // 0x00040000
#define STM32_GCCFG_VBUSASEN STM32_GCCFG_VBUSASEN_Msk // Enable A-device (host) VBUS sensing
// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
#define STM32_GCCFG_VBVALOVAL_Pos (23U)
#define STM32_GCCFG_VBVALOVAL_Msk (0x1U << STM32_GCCFG_VBVALOVAL_Pos) // 0x00800000
#define STM32_GCCFG_VBVALOVAL STM32_GCCFG_VBVALOVAL_Msk // Value of VBUSVLDEXT0 femtoPHY input
#define STM32_GCCFG_VBUSBSEN_Pos (19U)
#define STM32_GCCFG_VBUSBSEN_Msk (0x1UL << STM32_GCCFG_VBUSBSEN_Pos) // 0x00080000
#define STM32_GCCFG_VBUSBSEN STM32_GCCFG_VBUSBSEN_Msk // Enable B-device (peripheral) VBUS sensing
#define STM32_GCCFG_VBVALEXTOEN_Pos (24U)
#define STM32_GCCFG_VBVALEXTOEN_Msk (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos) // 0x01000000
#define STM32_GCCFG_VBVALEXTOEN STM32_GCCFG_VBVALEXTOEN_Msk // Enables of VBUSVLDEXT0 femtoPHY input override
#define STM32_GCCFG_NOVBUSSENS_Pos (21U)
#define STM32_GCCFG_NOVBUSSENS_Msk (0x1UL << STM32_GCCFG_NOVBUSSENS_Pos) // 0x00200000
#define STM32_GCCFG_NOVBUSSENS STM32_GCCFG_NOVBUSSENS_Msk // VBUS sensing disable option
// GUID < 0x2000: end
#define STM32_GCCFG_PULLDOWNEN_Pos (25U)
#define STM32_GCCFG_PULLDOWNEN_Msk (0x1U << STM32_GCCFG_PULLDOWNEN_Pos) // 0x02000000
#define STM32_GCCFG_PULLDOWNEN STM32_GCCFG_PULLDOWNEN_Msk // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
// TODO: stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
// #define STM32_GCCFG_SDEN_Pos (22U)
// #define STM32_GCCFG_SDEN_Msk (0x1U << STM32_GCCFG_SDEN_Pos) // 0x00400000
// #define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (PD) mode enable
// GUID >= 0x5000 use femtoPHY: VBVALOVA, VBVALEXTOEN, PULLDOWNEN
#define STM32_GCCFG_VBVALOVAL_Pos (23U)
#define STM32_GCCFG_VBVALOVAL_Msk (0x1U << STM32_GCCFG_VBVALOVAL_Pos) // 0x00800000
#define STM32_GCCFG_VBVALOVAL STM32_GCCFG_VBVALOVAL_Msk // Value of VBUSVLDEXT0 femtoPHY input
#define STM32_GCCFG_VBVALEXTOEN_Pos (24U)
#define STM32_GCCFG_VBVALEXTOEN_Msk (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos) // 0x01000000
#define STM32_GCCFG_VBVALEXTOEN STM32_GCCFG_VBVALEXTOEN_Msk // Enables of VBUSVLDEXT0 femtoPHY input override
#define STM32_GCCFG_PULLDOWNEN_Pos (25U)
#define STM32_GCCFG_PULLDOWNEN_Msk (0x1U << STM32_GCCFG_PULLDOWNEN_Pos) // 0x02000000
#define STM32_GCCFG_PULLDOWNEN STM32_GCCFG_PULLDOWNEN_Msk // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
// GUID >= 0x5000: end
/******************** Bit definition for DEACHINTMSK register ********************/
#define DEACHINTMSK_IEP1INTM_Pos (1U)

4
src/portable/synopsys/dwc2/hcd_dwc2.c
View File

@ -428,6 +428,10 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
#endif
while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {}
#ifdef TUP_USBIP_DWC2_STM32
dwc2_stm32_gccfg_cfg(dwc2, false, true);
#endif
// configure fixed-allocated fifo scheme
dfifo_host_init(rhport);

11
src/tusb_option.h
View File

@ -579,9 +579,18 @@
#define CFG_TUD_TEST_MODE 0
#endif
#ifndef CFG_TUD_VBUS_DETECT_HW_DEFAULT
#define CFG_TUD_VBUS_DETECT_HW_DEFAULT 0
#endif
// Enable VBUS Detect hardware, usually via functional GPIO
#ifndef CFG_TUD_VBUS_DETECT_HW
#define CFG_TUD_VBUS_DETECT_HW CFG_TUD_VBUS_DETECT_HW_DEFAULT
#endif
//------------- Device Class Driver -------------//
#ifndef CFG_TUD_BTH
#define CFG_TUD_BTH 0
#define CFG_TUD_BTH 0
#endif
#if CFG_TUD_BTH && !defined(CFG_TUD_BTH_ISO_ALT_COUNT)