mirror of
https://github.com/hathach/tinyusb.git
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address #3787 reviews: bsp fixes, script hardening, board-note accuracy
Bot findings (Copilot/Codex): no-op board_trace_pinmux stubs for lpcxpresso18s37/43s67 (TRACE_ETM otherwise broke their build), SAME70 ID_PIOD clock enable, capture-script duplicate BeforeTargetConnect on the RA references, profile-script support for --no-timestamps itraces. Deep review (whole branch): same70_xplained board row + caveat restored, stale pico2 72 MHz claim corrected to the shipped 48, explicit SetTracePortWidth(4) in the three references that relied on Ozone's default, coverage-cell guard, median-based SysTick calibration, dead session flag removed, stale RA8M1 divider comment fixed (0x02 = /4 is the validated chip max) and the debugger guard indented. EVKB bench findings: only R1884/D3 remains open (D1/D2 meter-verified); RT1176 trace width is 1 or 4 only - J-Link arms the CSSYS TPIU and its own sampler at 4-bit for any width>=2 request; a powered MCU-Link USB breaks the external probe even with JP4 shorted.
This commit is contained in:
hathach
@ -23,11 +23,12 @@ reference.
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| ea4088_quickstart | 120 MHz | 120 MHz | 4 | 0 (unset) | J7 (fully wired) | — |
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| nrf52840dk | 64 MHz | 16 MHz (hw cap) | 4 | 0 (unset) | solder P25, SW7 → Alt | — |
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| nrf5340dk (M33) | 64 MHz | 16 MHz (TAD, forced) | 4 | +3 ns | mount P25; cut SB27/SB28 | — |
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| mimxrt1170_evkb | 996 MHz | 50 MHz (root/2) | 1 | 0 | weld 0 Ω R1881-R1886; JP4 shorted; J58 (populated) | reflow R1882-R1884 (D1-D3 open) → width 4 |
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| mimxrt1170_evkb | 996 MHz | 50 MHz (root/2) | 1 | 0 | weld 0 Ω R1881-R1886; JP4 shorted; J58 (populated) | re-weld R1884 (D3 open; D1/D2 meter-verified good) → width 4 |
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| ra6m5_ek (M33) | 200 MHz | 25 MHz (TRCLK/4 /2) | 4 | 0 (unset) | J9 closed; native J20 trace | — |
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| ra8m1_ek (M85) | 480 MHz | 60 MHz (TRCLK/4 /2) | 4 | 0 (unset) | J9 closed + Table 7 jumpers | — |
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| raspberry_pi_pico2 (RP2350 M33) | 48 MHz | 24 MHz (clk_sys/2) | 4 | 0 (unset) | fly-wire GPIO1-5 → MIPI20 (map in jdebug) | 72-80 MHz per seating (re-qualify); >80 needs V3 probe + trace board |
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| same54_xplained (E54 M4F) | 120 MHz | 60 MHz (CPU/2) | 4 | 0 (unset) | none — populated 20-pin ETM header | — |
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| same70_xplained (E70 M7) | 300 MHz | 37.5 MHz (PCK3/2) | 1 | 0 (unset) | solder 20-pin header on J403 (bottom) | width 4 blocked: D1 (J403.16) dead at speed — probe-channel crosscheck pending |
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| SEGGER H7/F407 ref | demo defaults | demo | 4 | demo | probe-powered: add `--power` | — |
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Board caveats (beyond the table):
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@ -35,7 +36,7 @@ Board caveats (beyond the table):
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- **stm32h743eval**: startup-burst overflow at 400 MHz is normal (reduce
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PLLN in board.h for overflow-free capture); timestamp ref 200 MHz.
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- **stm32n657nucleo** (M55, flashless): **JP2 (BOOT1) must be 1** — the app
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is a RAM image the debugger loads (Development boot); in flash boot theb
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is a RAM image the debugger loads (Development boot); in flash boot the
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bootROM parks the chip un-attachable ("Can not attach to CPU"). SEGGER's
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KB says BOOT0/BOOT1 = 0/0 for their example — that is flash boot and it
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does NOT attach; the board manual's Table 11 is right. 600 MHz core kills
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@ -76,7 +77,12 @@ Board caveats (beyond the table):
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and enables the CM7 platform trace-funnel port, which J-Link doesn't
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program: without it everything reads register-perfect yet zero data
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arrives. JP4 must be shorted (disables MCU-Link SWD) for the external
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J-Trace on J58. FlexSPI apps: ROM bootloader must set SP/PC — the
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J-Trace on J58; a powered MCU-Link USB breaks the external probe's connect
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even with JP4 shorted - power the board from another port. **Width is 1 or
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4 only**: a width-2 request arms the CSSYS TPIU (E004_6000) and the probe
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sampler at 4-bit anyway (CSPSR reads 0x8 after a width-2 session; a live
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CSPSR=2 poke with LAR unlock + Trace.Clear still captures nothing because
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the probe keeps sampling 4-bit). FlexSPI apps: ROM bootloader must set SP/PC — the
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committed reset/download hooks handle this. Startup-burst overflow at
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996 MHz is normal. No Ethernet (100M) while tracing.
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- **ra6m5_ek**: TRCKCR div-2 (100 MHz TRCLK = 50 MHz pin, the chip max) is
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@ -118,7 +124,7 @@ Board caveats (beyond the table):
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trace component map (funnel/TPIU/ETM are not in the ROM table → "Required
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trace components for pin trace not found", 0 fetches) and re-arms the whole
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chip-side path via `OnTraceStart` at every resume. Firmware therefore does
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no trace setup; TRACE_ETM builds only (a) pin clk_sys to 72 MHz from crt0
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no trace setup; TRACE_ETM builds only (a) pin clk_sys to 48 MHz from crt0
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(board.cmake) — the fly-wire ceiling: 96/150 MHz kill the stream in the
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startup burst at any sample timing (and at 150 MHz the saturated probe
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stops answering halts, "CPU could not be halted"); any post-arm clock
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@ -136,5 +142,15 @@ Board caveats (beyond the table):
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`trace_etm_init` feeds it GCLK0. Pins PC24-28 mux to function H. The
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populated 20-pin header runs chip-max 60 MHz TRACECLK width 4 with no
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timing adjustment - the connector-vs-flywire contrast board.
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- **same70_xplained**: J403 is a bottom-side bare footprint — solder the
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header. Trace pins PD4-7 double as the KSZ8081 PHY's RMII receive outputs:
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TRACE_ETM builds hold it in reset (PHY_RESET=PC10) or it drives against
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the stream. TPIU clock = PCK3 (datasheet 16.7.4), run at MCK/2; TPIU
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programming while PCK3 is stopped is silently LOST — the reference starts
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PCK3 in the post-reset/download hooks (a reset wipes the PMC, so
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AfterTargetConnect is too early). Width 1 validated at the stock 300 MHz
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core; width 2/4 blocked on a dead D1 line at J403.16 (clean at DC by
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meter, dead at speed — probe-channel crosscheck on a known-good width-4
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board pending). No Ethernet while tracing.
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- **SEGGER ref boards**: run their own demo (ladder step 3 flags); `--isr`
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degrades gracefully without a live SysTick.
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@ -126,6 +126,12 @@ def resolve_board(board):
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name, block = m.group(1), m.group(0)
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if name == "OnProjectLoad":
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continue
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elif name == "BeforeTargetConnect":
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# the generated project synthesizes its own BeforeTargetConnect
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# (JLINK_SCRIPT_HOOK) from the SetJLinkScript regex below;
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# inheriting the reference's copy too would emit a duplicate
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# function definition
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continue
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elif name == "AfterTargetReset":
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cfg["reset_hook"] = block
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elif name == "AfterTargetDownload":
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@ -472,7 +478,6 @@ def main():
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start_new_session=True)
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profile_out = os.path.join(outdir, "code_profile.txt")
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itrace_out = os.path.join(outdir, "itrace.csv")
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ok = False
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try:
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ses.connect(20)
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ses.drain(3) # version banner
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@ -513,7 +518,6 @@ def main():
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ses.wait_echo(f'Export.PowerGraphs ("{outdir}/power.csv")', 60)
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ses.send("Debug.Stop", 5)
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ses.send("File.Exit", 2)
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ok = True
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finally:
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for _ in range(15):
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if proc.poll() is not None:
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@ -551,9 +555,6 @@ def main():
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sys.exit("error: session completed but NO trace data was collected "
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"(profile totals are zero) - trace signal not reaching the "
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"probe: check wiring/connector, trace pinmux, sample timing.")
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if not ok:
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sys.exit("error: session did not complete cleanly (see session.log)")
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print(f"\ncapture OK: {outdir}")
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print(f" code_profile.txt ({os.path.getsize(profile_out)} bytes)")
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if args.trace_csv:
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@ -66,7 +66,7 @@ def parse_profile(path):
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for module, name, cells in rows(lines[cov_start:prof_start]):
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m_src = cov_pat.match(cells[0]) if cells else None
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m_inst = cov_pat.match(cells[1]) if len(cells) > 1 else None
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if name == "Total" and m_inst:
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if name == "Total" and m_inst and m_src:
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totals["src_cov"] = num(m_src.group(1)), num(m_src.group(2))
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totals["inst_cov"] = num(m_inst.group(1)), num(m_inst.group(2))
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elif name in funcs and m_inst:
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@ -120,14 +120,29 @@ def iter_itrace(path):
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caller reads unit separately with itrace_unit()."""
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with open(path, newline="", errors="replace") as f:
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rd = csv.reader(f)
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next(rd, None)
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hdr = next(rd, None) or []
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# --no-timestamps captures drop the Timestamp column entirely: locate
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# the Address column from the header and yield t=None for such rows
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# (consumers count instructions but skip time math)
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has_ts = any("Timestamp" in c for c in hdr)
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try:
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addr_i = next(i for i, c in enumerate(hdr) if "Address" in c)
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except StopIteration:
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addr_i = 1 if has_ts else 0
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for row in rd:
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if not row or row[0] == "PC" or len(row) < 2:
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if not row or len(row) <= addr_i:
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continue
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try:
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yield float(row[0]), int(row[1], 16)
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addr = int(row[addr_i], 16)
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except ValueError:
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continue
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if has_ts and row[0] != "PC":
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try:
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yield float(row[0]), addr
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continue
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except ValueError:
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pass
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yield None, addr
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def itrace_unit(path):
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@ -144,6 +159,8 @@ def time_by_func(path, syms):
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sample = []
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t_prev = None
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for t, _ in iter_itrace(path):
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if t is None:
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continue
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if t_prev is not None and t_prev - t > 0:
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sample.append(t_prev - t)
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if len(sample) >= 200000:
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@ -158,6 +175,8 @@ def time_by_func(path, syms):
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fn = addr_to_func(syms, a)
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if fn:
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cf[fn] = cf.get(fn, 0) + 1
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if t is None:
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continue
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if t_prev is not None:
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d = t_prev - t
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if 0 < d < cap and fn:
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@ -180,6 +199,8 @@ def isr_report(itrace, elf, isr_arg, top):
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usb_rows, tick_rows, tmin, tmax = [], [], None, None
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for t, a in iter_itrace(itrace):
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if t is None:
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continue # --no-timestamps capture: the <20-rows message below applies
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tmin = t if tmin is None else min(tmin, t)
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tmax = t if tmax is None else max(tmax, t)
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if any(lo <= a < hi for lo, hi in body):
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@ -195,10 +216,12 @@ def isr_report(itrace, elf, isr_arg, top):
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f"({len(tick_rows)} rows) - capture with timestamps enabled")
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return
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# rough raw-units-per-1ms from the large mode of consecutive tick deltas
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# rough raw-units-per-1ms from the large mode of consecutive tick deltas;
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# threshold from the median, not the max - one trace-overflow gap would
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# otherwise inflate the cut and leave only outliers in the sample
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deltas = [b[0] - a[0] for a, b in zip(tick_rows, tick_rows[1:])]
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big = [d for d in deltas if d > max(deltas) / 10]
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raw_ms = statistics.median(big)
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big = [d for d in deltas if d > 10 * statistics.median(deltas)]
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raw_ms = statistics.median(big) if big else statistics.median(deltas)
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gap = 0.03 * raw_ms # 30 us in raw units
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edge = 0.05 * raw_ms
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@ -390,11 +413,18 @@ def main():
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cshare = {k: v / tc for k, v in cf.items()}
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unit = itrace_unit(itrace)
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print(f"\n## Instruction history (itrace.csv, unit '{unit}')\n")
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print(f"- {n:,} instructions; top {args.top} by TIME share "
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f"(vs instruction share):")
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for name, ts in sorted(tshare.items(), key=lambda kv: -kv[1])[:args.top]:
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print(f" - `{short(name)}`: {100 * ts:.1f}% time, "
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f"{100 * cshare.get(name, 0):.1f}% instructions")
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if not tf:
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print(f"- {n:,} instructions, NO timestamps (--no-timestamps "
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f"capture): time shares unavailable, top {args.top} by "
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f"instruction share:")
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for name, cs in sorted(cshare.items(), key=lambda kv: -kv[1])[:args.top]:
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print(f" - `{short(name)}`: {100 * cs:.1f}% instructions")
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else:
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print(f"- {n:,} instructions; top {args.top} by TIME share "
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f"(vs instruction share):")
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for name, ts in sorted(tshare.items(), key=lambda kv: -kv[1])[:args.top]:
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print(f" - `{short(name)}`: {100 * ts:.1f}% time, "
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f"{100 * cshare.get(name, 0):.1f}% instructions")
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lines_csv = os.path.join(args.capture_dir, "profile_lines.csv")
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if os.path.isfile(lines_csv):
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@ -10,6 +10,7 @@
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*/
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void OnProjectLoad (void) {
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Project.SetTraceSource ("Trace Pins");
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Project.SetTracePortWidth (4);
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Project.SetTraceTiming (50, 50, 50, 50);
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Project.SetDevice ("MIMXRT1011xxx4A");
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Project.SetHostIF ("USB", "");
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@ -76,6 +76,12 @@ static inline void board_lpc18_pinmux(void)
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Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
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}
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// TRACE_ETM builds: no trace header is wired out on the LPCXpresso18S37 -
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// provide the no-op the family init expects (see mcb1800/ea4357 for a
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// board that routes the trace pins)
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static inline void board_trace_pinmux(void) {}
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#ifdef __cplusplus
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}
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#endif
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@ -71,6 +71,12 @@ static const PINMUX_GRP_T pinmuxing[] = {
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{0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
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};
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// TRACE_ETM builds: no trace header is wired out on the LPCXpresso43S67 -
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// provide the no-op the family init expects (see mcb1800/ea4357 for a
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// board that routes the trace pins)
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static inline void board_trace_pinmux(void) {}
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#ifdef __cplusplus
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}
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#endif
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@ -10,6 +10,7 @@
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*/
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void OnProjectLoad (void) {
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Project.SetTraceSource ("Trace Pins");
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Project.SetTracePortWidth (4);
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Project.SetDevice ("R7FA8M1AH");
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Project.SetHostIF ("USB", "");
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Project.SetTargetIF ("SWD");
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@ -103,25 +103,27 @@ void board_init(void) {
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// standalone boot must skip trace init or the write wedges the chip into
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// an un-attachable crash loop (recover: power-cycle + immediate erase)
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if (DCB->DHCSR & DCB_DHCSR_C_DEBUGEN_Msk) {
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// TRCKCR is protected by PRCR bit0 register
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R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01);
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// TRCKCR is protected by PRCR bit0 register
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R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01);
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// TCLK pin = TRCLK/2; set the divider with TRCKEN=0 first (HUM procedure).
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// Values are the empirical per-board ceilings: one step below the divider
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// at which the stream dies mid-run.
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// TCLK pin = TRCLK/2; set the divider with TRCKEN=0 first (HUM procedure).
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// Values are the empirical per-board ceilings.
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#if defined(BSP_MCU_GROUP_RA8M1)
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// 480 MHz CPU: /8 -> 60 MHz TRCLK, 30 MHz pin (/4 = 60 MHz pin dies)
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R_SYSTEM->TRCKCR = 0x02;
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R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x02;
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// 480 MHz CPU: /4 -> 120 MHz TRCLK, 60 MHz pin - chip max, clean on
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// EK-RA8M1 with the committed empty-OnTraceStart JLinkScript (which
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// defers the trace clock to firmware; without it the FSP MOCO->PLL
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// switch steps the clock mid-stream and any divider fails)
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R_SYSTEM->TRCKCR = 0x02;
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R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x02;
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#else
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// RA6M5 200 MHz CPU: /4 -> 50 MHz TRCLK, 25 MHz pin. /2 (50 MHz pin) is
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// silent on the EK-RA6M5 in every combination - board path ceiling,
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// reconfirmed with J9 closed and the OnTraceStart override
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R_SYSTEM->TRCKCR = 0x02;
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R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x02;
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// RA6M5 200 MHz CPU: /4 -> 50 MHz TRCLK, 25 MHz pin. /2 (50 MHz pin) is
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// silent on the EK-RA6M5 in every combination - board path ceiling,
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// reconfirmed with J9 closed and the OnTraceStart override
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R_SYSTEM->TRCKCR = 0x02;
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R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x02;
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#endif
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R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY;
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R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY;
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}
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#endif
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@ -82,6 +82,7 @@ void board_init(void) {
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PMC->PMC_SCER = PMC_SCER_PCK3;
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while (!(PMC->PMC_SR & PMC_SR_PCKRDY3)) {}
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}
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_pmc_enable_periph_clock(ID_PIOD);
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uint32_t const clk_pin = PIO_PD8D_TPIU_TRACECLK;
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uint32_t const dat_pin = PIO_PD4C_TPIU_TRACED0 | PIO_PD5C_TPIU_TRACED1 |
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PIO_PD6C_TPIU_TRACED2 | PIO_PD7C_TPIU_TRACED3;
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@ -10,6 +10,7 @@
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*/
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void OnProjectLoad (void) {
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Project.SetTraceSource ("Trace Pins");
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Project.SetTracePortWidth (4);
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Project.SetTraceTiming (100, 100, 100, 100);
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Project.SetSWO (0);
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Edit.SysVar (VAR_TRACE_CORE_CLOCK, 200000000);
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