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hw/bsp/lpc43: configure safe flash timing

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Zixun LI
2026-07-27 20:44:18 +02:00
parent 9a4d71162b
commit edb4a0744a
1 changed files with 12 additions and 1 deletions
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13
hw/bsp/lpc43/family.c
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@ -59,11 +59,22 @@ void SystemInit(void);
// Invoked by startup code
void SystemInit(void)
{
#if defined(__ICCARM__) && !defined(DONT_RESET_ON_RESTART)
__disable_irq();
#endif
if (Chip_CREG_OnChipFlashIsPresent()) {
// The boot ROM configures flash for its 96 MHz clock, and debugger core
// resets can preserve it. Use safe timing before switching the M4 to 204 MHz.
Chip_CREG_SetFLASHAccess(FLASHTIM_SAFE_SETTING);
__DSB();
__ISB();
}
#if defined(__ICCARM__) && !defined(DONT_RESET_ON_RESTART)
// A debugger restart resets the M4 core, but can leave LPC43 peripherals and
// pending interrupts active. Match the GCC startup sequence, which the IAR
// startup lacks, before the C runtime can reuse peripheral DMA memory.
__disable_irq();
LPC_RGU->RESET_CTRL[0] = 0x10DF1000u;
LPC_RGU->RESET_CTRL[1] = 0x01DFF7FFu;
for (uint32_t i = 0; i < 8; i++) {