65714d3e6c
MAX78000: Add ICC to SOC
...
This commit adds the instruction cache controller
to max78000_soc
Signed-off-by: Jackson Donaldson <jcksn@duck.com >
Reviewed-by: Peter Maydell <petermaydell@linaro.org >
Message-id: 20250704223239.248781-4-jcksn@duck.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2025-07-08 17:31:38 +01:00
3ec680e64c
MAX78000: ICC Implementation
...
This commit implements the Instruction Cache Controller
for the MAX78000
Signed-off-by: Jackson Donaldson <jcksn@duck.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20250704223239.248781-3-jcksn@duck.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2025-07-08 17:31:38 +01:00
51eb283dd0
MAX78000: Add MAX78000FTHR Machine
...
This patch adds support for the MAX78000FTHR machine.
The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch
implements only the MAX78000, which is Cortex-M4 based.
Details can be found at:
https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf
Signed-off-by: Jackson Donaldson <jcksn@duck.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-id: 20250704223239.248781-2-jcksn@duck.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org >
2025-07-08 17:31:38 +01:00
84d1639f28
Merge tag 'accel-20250704' of https://github.com/philmd/qemu into staging
...
Accelerators patches
- Generic API consolidation, cleanups (dead code removal, documentation added)
- Remove monitor TCG 'info opcount' and @x-query-opcount
- Have HVF / NVMM / WHPX use generic CPUState::vcpu_dirty field
- Expose nvmm_enabled() and whpx_enabled() to common code
- Report missing com.apple.security.hypervisor entitlement
- Have hmp_info_registers() dump vector registers
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# gpg: Signature made Fri 04 Jul 2025 09:37:32 EDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org >" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'accel-20250704' of https://github.com/philmd/qemu : (35 commits)
MAINTAINERS: Add me as reviewer of overall accelerators section
monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers()
accel/system: Convert pre_resume() from AccelOpsClass to AccelClass
accel: Pass AccelState argument to gdbstub_supported_sstep_flags()
accel: Remove unused MachineState argument of AccelClass::setup_post()
accel: Directly pass AccelState argument to AccelClass::has_memory()
accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()
accel/kvm: Prefer local AccelState over global MachineState::accel
accel/tcg: Prefer local AccelState over global current_accel()
accel/hvf: Re-use QOM allocated state
accel: Propagate AccelState to AccelClass::init_machine()
accel: Keep reference to AccelOpsClass in AccelClass
accel: Expose and register generic_handle_interrupt()
accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'
accel/whpx: Expose whpx_enabled() to common code
accel/nvmm: Expose nvmm_enabled() to common code
accel/system: Document cpu_synchronize_state_post_init/reset()
accel/system: Document cpu_synchronize_state()
accel/kvm: Remove kvm_cpu_synchronize_state() stub
accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com >
Conflicts:
accel/accel-system.c
accel/hvf/hvf-all.c
include/qemu/accel.h
pre_resume_vm()-related conflicts.
2025-07-07 09:18:34 -04:00
9a8e6b9ca1
accel/system: Convert pre_resume() from AccelOpsClass to AccelClass
...
Accelerators call pre_resume() once. Since it isn't a method to
call for each vCPU, move it from AccelOpsClass to AccelClass.
Adapt WHPX.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20250702185332.43650-21-philmd@linaro.org >
2025-07-04 15:37:07 +02:00
261573c772
accel: Pass AccelState argument to gdbstub_supported_sstep_flags()
...
In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-37-philmd@linaro.org >
2025-07-04 15:22:04 +02:00
c7212fd2ce
accel: Remove unused MachineState argument of AccelClass::setup_post()
...
This method only accesses xen_domid/xen_domid_restrict, which are both
related to the 'accelerator', not the machine. Besides, xen_domid aims
to be in Xen AccelState and xen_domid_restrict a xen_domid_restrict
QOM property.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-36-philmd@linaro.org >
2025-07-04 15:22:04 +02:00
14784d00ce
accel: Directly pass AccelState argument to AccelClass::has_memory()
...
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-34-philmd@linaro.org >
2025-07-04 15:22:04 +02:00
9d01d2e86d
accel: Propagate AccelState to AccelClass::init_machine()
...
In order to avoid init_machine() to call current_accel(),
pass AccelState along.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-31-philmd@linaro.org >
2025-07-04 15:22:02 +02:00
e240f6cc25
Merge tag 'pull-riscv-to-apply-20250704' of https://github.com/alistair23/qemu into staging
...
Second RISC-V PR for 10.1
* sstc extension fixes
* Fix zama16b order in isa_edata_arr
* Profile handling fixes
* Extend PMP region up to 64
* Remove capital 'Z' CPU properties
* Add missing named features
* Support atomic instruction fetch (Ziccif)
* Add max_satp_mode from host cpu
* Extend and configure PMP region count
* Fix PPN field of Translation-reponse register
* Use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
* Fix fcvt.s.bf16 NaN box checking
* Avoid infinite delay of async xmit function
* Device tree reg cleanups
* Add Kunminghu CPU and platform
* Fix missing exit TB flow for ldff_trans
* Fix migration failure when aia is configured as aplic-imsic
* Fix MEPC/SEPC bit masking for IALIGN
* Add a property to set vill bit on reserved usage of vsetvli instruction
* Add Svrsw60t59b extension support
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# gpg: Signature made Fri 04 Jul 2025 07:11:26 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me >" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20250704' of https://github.com/alistair23/qemu : (40 commits)
target: riscv: Add Svrsw60t59b extension support
target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction
tests/tcg/riscv64: Add test for MEPC bit masking
target/riscv: Fix MEPC/SEPC bit masking for IALIGN
migration: Fix migration failure when aia is configured as aplic-imsic
target/riscv: rvv: Fix missing exit TB flow for ldff_trans
hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
target/riscv: Add BOSC's Xiangshan Kunminghu CPU
hw/riscv/virt: Use setprop_sized_cells for pcie
hw/riscv/virt: Use setprop_sized_cells for iommu
hw/riscv/virt: Use setprop_sized_cells for rtc
hw/riscv/virt: Use setprop_sized_cells for uart
hw/riscv/virt: Use setprop_sized_cells for reset
hw/riscv/virt: Use setprop_sized_cells for virtio
hw/riscv/virt: Use setprop_sized_cells for plic
hw/riscv/virt: Use setprop_sized_cells for aclint
hw/riscv/virt: Use setprop_sized_cells for aplic
hw/riscv/virt: Use setprop_sized_cells for memory
hw/riscv/virt: Use setprop_sized_cells for clint
hw/riscv/virt: Fix clint base address type
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com >
2025-07-04 08:58:58 -04:00
989dd906ed
Merge tag 'accel-20250704' of https://github.com/philmd/qemu into staging
...
Accelerators patches
- Generic API consolidation, cleanups (dead code removal, documentation added)
- Remove monitor TCG 'info opcount' and @x-query-opcount
- Have HVF / NVMM / WHPX use generic CPUState::vcpu_dirty field
- Expose nvmm_enabled() and whpx_enabled() to common code
- Have hmp_info_registers() dump vector registers
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# gpg: Signature made Fri 04 Jul 2025 06:18:06 EDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org >" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'accel-20250704' of https://github.com/philmd/qemu : (31 commits)
MAINTAINERS: Add me as reviewer of overall accelerators section
monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers()
accel: Pass AccelState argument to gdbstub_supported_sstep_flags()
accel: Remove unused MachineState argument of AccelClass::setup_post()
accel: Directly pass AccelState argument to AccelClass::has_memory()
accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()
accel/kvm: Prefer local AccelState over global MachineState::accel
accel/tcg: Prefer local AccelState over global current_accel()
accel: Propagate AccelState to AccelClass::init_machine()
accel: Keep reference to AccelOpsClass in AccelClass
accel: Expose and register generic_handle_interrupt()
accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'
accel/whpx: Expose whpx_enabled() to common code
accel/nvmm: Expose nvmm_enabled() to common code
accel/system: Document cpu_synchronize_state_post_init/reset()
accel/system: Document cpu_synchronize_state()
accel/kvm: Remove kvm_cpu_synchronize_state() stub
accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field
accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field
accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com >
2025-07-04 08:58:49 -04:00
563ac3d181
Merge tag 'pull-vfio-20250704' of https://github.com/legoater/qemu into staging
...
vfio queue:
* Added small cleanups for b4 and scope
* Restricted TDX build to 64-bit target
* Fixed issues introduced in first part of VFIO live update support
* Added full VFIO live update support
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# gpg: Signature made Fri 04 Jul 2025 04:42:59 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com >" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org >" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-vfio-20250704' of https://github.com/legoater/qemu : (27 commits)
vfio: doc changes for cpr
vfio/container: delete old cpr register
iommufd: preserve DMA mappings
vfio/iommufd: change process
vfio/iommufd: reconstruct hwpt
vfio/iommufd: reconstruct device
vfio/iommufd: preserve descriptors
vfio/iommufd: cpr state
migration: vfio cpr state hook
vfio/iommufd: register container for cpr
vfio/iommufd: device name blocker
vfio/iommufd: add vfio_device_free_name
vfio/iommufd: invariant device name
vfio/iommufd: use IOMMU_IOAS_MAP_FILE
physmem: qemu_ram_get_fd_offset
backends/iommufd: change process ioctl
backends/iommufd: iommufd_backend_map_file_dma
migration: cpr_get_fd_param helper
migration: close kvm after cpr
vfio-pci: preserve INTx
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com >
2025-07-04 08:58:39 -04:00
487b25c9d9
accel: Keep reference to AccelOpsClass in AccelClass
...
Allow dereferencing AccelOpsClass outside of accel/accel-system.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-30-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
b64bb17d14
accel: Expose and register generic_handle_interrupt()
...
In order to dispatch over AccelOpsClass::handle_interrupt(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for each accelerator.
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Mads Ynddal <mads@ynddal.dk >
Message-Id: <20250703173248.44995-29-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
20a0181600
accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'
...
'dummy' helpers are specific to accelerator implementations,
no need to expose them via "system/cpus.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-27-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
a9c2afd74b
accel/whpx: Expose whpx_enabled() to common code
...
Currently whpx_enabled() is restricted to target-specific code.
By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20250703173248.44995-26-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
80a1efdedd
accel/nvmm: Expose nvmm_enabled() to common code
...
Currently nvmm_enabled() is restricted to target-specific code.
By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-25-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
04bd6c3631
accel/system: Document cpu_synchronize_state_post_init/reset()
...
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-24-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
8e825755c5
accel/system: Document cpu_synchronize_state()
...
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-23-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
6f13a0ada0
accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field
...
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Reviewed-by: Mads Ynddal <mads@ynddal.dk >
Message-Id: <20250703173248.44995-19-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
b6340f5866
cpus: Document CPUState::vcpu_dirty field
...
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Message-Id: <20250703173248.44995-18-philmd@linaro.org >
2025-07-04 14:43:46 +02:00
4dc480e7da
accel/hvf: Restrict internal declarations
...
Common code only needs to know whether HVF is enabled and
the QOM type. Move the rest to "hvf_int.h", removing the
need for COMPILING_PER_TARGET #ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-15-philmd@linaro.org >
2025-07-04 14:43:45 +02:00
af065855ce
accel/kvm: Reduce kvm_create_vcpu() declaration scope
...
kvm_create_vcpu() is only used within the same file unit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-7-philmd@linaro.org >
2025-07-04 14:43:45 +02:00
29abd3d112
hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
...
This implementation provides emulation for the Xiangshan Kunminghu
FPGA prototype platform, including support for UART, CLINT, IMSIC,
and APLIC devices. More details can be found at
https://github.com/OpenXiangShan/XiangShan
Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn >
Signed-off-by: Yang Wang <wangyang@bosc.ac.cn >
Signed-off-by: Yu Hu <819258943@qq.com >
Signed-off-by: Ran Wang <wangran@bosc.ac.cn >
Signed-off-by: Borong Huang <3543977024@qq.com >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-ID: <20250617074222.17618-1-wangran@bosc.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2025-07-04 21:09:49 +10:00
842e7eecd4
accel: Pass AccelState argument to gdbstub_supported_sstep_flags()
...
In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20250703173248.44995-37-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
1e9fb43d30
accel: Remove unused MachineState argument of AccelClass::setup_post()
...
This method only accesses xen_domid/xen_domid_restrict, which are both
related to the 'accelerator', not the machine. Besides, xen_domid aims
to be in Xen AccelState and xen_domid_restrict a xen_domid_restrict
QOM property.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20250703173248.44995-36-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
8dd5e6befc
accel: Directly pass AccelState argument to AccelClass::has_memory()
...
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Message-Id: <20250703173248.44995-34-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
51e1896199
accel: Propagate AccelState to AccelClass::init_machine()
...
In order to avoid init_machine() to call current_accel(),
pass AccelState along.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20250703173248.44995-31-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
38623a9f63
accel: Keep reference to AccelOpsClass in AccelClass
...
Allow dereferencing AccelOpsClass outside of accel/accel-system.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Message-Id: <20250703173248.44995-30-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
b9b8ce0384
accel: Expose and register generic_handle_interrupt()
...
In order to dispatch over AccelOpsClass::handle_interrupt(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for each accelerator.
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Message-Id: <20250703173248.44995-29-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
e8388158e6
accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'
...
'dummy' helpers are specific to accelerator implementations,
no need to expose them via "system/cpus.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Message-Id: <20250703173248.44995-27-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
d5a407a576
accel/whpx: Expose whpx_enabled() to common code
...
Currently whpx_enabled() is restricted to target-specific code.
By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20250703173248.44995-26-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
b6637bd556
accel/nvmm: Expose nvmm_enabled() to common code
...
Currently nvmm_enabled() is restricted to target-specific code.
By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-25-philmd@linaro.org >
2025-07-04 12:08:44 +02:00
60c9cec12c
accel/system: Document cpu_synchronize_state_post_init/reset()
...
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-24-philmd@linaro.org >
2025-07-04 12:08:41 +02:00
1f8b0b6473
accel/system: Document cpu_synchronize_state()
...
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-23-philmd@linaro.org >
2025-07-04 12:08:38 +02:00
93bbbcb8d6
accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field
...
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-19-philmd@linaro.org >
2025-07-04 12:08:25 +02:00
332ad068a0
cpus: Document CPUState::vcpu_dirty field
...
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Message-Id: <20250703173248.44995-18-philmd@linaro.org >
2025-07-04 12:08:25 +02:00
0175310c38
accel/hvf: Restrict internal declarations
...
Common code only needs to know whether HVF is enabled and
the QOM type. Move the rest to "hvf_int.h", removing the
need for COMPILING_PER_TARGET #ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-15-philmd@linaro.org >
2025-07-04 12:08:16 +02:00
06810394fd
accel/kvm: Reduce kvm_create_vcpu() declaration scope
...
kvm_create_vcpu() is only used within the same file unit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com >
Reviewed-by: Zhao Liu <zhao1.liu@intel.com >
Message-Id: <20250703173248.44995-7-philmd@linaro.org >
2025-07-04 12:02:52 +02:00
92096685a0
hw/arm/aspeed: Add second SPI chip to Aspeed model
...
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous <etanous@nvidia.com >
Reviewed-by: Cédric Le Goater <clg@redhat.com >
Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@nvidia.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 17:36:45 +02:00
99cedd5d55
vfio/container: delete old cpr register
...
vfio_cpr_[un]register_container is no longer used since they were
subsumed by container type-specific registration. Delete them.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Reviewed-by: Cédric Le Goater <clg@redhat.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-21-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
f2f3e4667e
vfio/iommufd: cpr state
...
VFIO iommufd devices will need access to ioas_id, devid, and hwpt_id in
new QEMU at realize time, so add them to CPR state. Define CprVFIODevice
as the object which holds the state and is serialized to the vmstate file.
Define accessors to copy state between VFIODevice and CprVFIODevice.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-15-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
a6f2f9c42f
migration: vfio cpr state hook
...
Define a list of vfio devices in CPR state, in a subsection so that
older QEMU can be live updated to this version. However, new QEMU
will not be live updateable to old QEMU. This is acceptable because
CPR is not yet commonly used, and updates to older versions are unusual.
The contents of each device object will be defined by the vfio subsystem
in a subsequent patch.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-14-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
06c6a65852
vfio/iommufd: register container for cpr
...
Register a vfio iommufd container and device for CPR, replacing the generic
CPR register call with a more specific iommufd register call. Add a
blocker if the kernel does not support IOMMU_IOAS_CHANGE_PROCESS.
This is mostly boiler plate. The fields to to saved and restored are added
in subsequent patches.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-13-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
a434fd8f64
vfio/iommufd: device name blocker
...
If an invariant device name cannot be created, block CPR.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-12-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
184053f04f
vfio/iommufd: add vfio_device_free_name
...
Define vfio_device_free_name to free the name created by
vfio_device_get_name. A subsequent patch will do more there.
No functional change.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Cédric Le Goater <clg@redhat.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-11-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
fb32965b6d
vfio/iommufd: use IOMMU_IOAS_MAP_FILE
...
Use IOMMU_IOAS_MAP_FILE when the mapped region is backed by a file.
Such a mapping can be preserved without modification during CPR,
because it depends on the file's address space, which does not change,
rather than on the process's address space, which does change.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-9-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
d7ae4a740c
physmem: qemu_ram_get_fd_offset
...
Define qemu_ram_get_fd_offset, so CPR can map a memory region using
IOMMU_IOAS_MAP_FILE in a subsequent patch.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Peter Xu <peterx@redhat.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-8-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
ab48cedc64
backends/iommufd: change process ioctl
...
Define the change process ioctl
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Cédric Le Goater <clg@redhat.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-7-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
e563dc88c2
backends/iommufd: iommufd_backend_map_file_dma
...
Define iommufd_backend_map_file_dma to implement IOMMU_IOAS_MAP_FILE.
This will be called as a substitute for iommufd_backend_map_dma, so
the error conditions for BARs are copied as-is from that function.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com >
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com >
Link: https://lore.kernel.org/qemu-devel/1751493538-202042-6-git-send-email-steven.sistare@oracle.com
Signed-off-by: Cédric Le Goater <clg@redhat.com >
2025-07-03 13:42:28 +02:00
