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The MASTER_DISABLE bit (aka mask-all) masks all the interrupts. According to Sun-4M System Architecture "The level–15 interrupt sources [...] are maskable with the Interrupt Target Mask Register. While these interrupts are considered ’non–maskable’ within the SPARC IU, a mask capability is provided to allow the boot firmware to establish a basic environment before receiving any level–15 interrupts, which are non–maskable within SPARC. A mask–all bit is provided to allow disabling of all external interrupts during change of the CIT." Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Read the documentation in qemu-doc.html. Fabrice Bellard.
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