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Processors supporting the MIPS16 or microMIPS ISAs set bit 0 in target addresses to indicate that the target is written using a compressed ISA. During signal handling, when jumping to or returning from a signal handler, bit 0 of the destination PC is inspected and MIPS_HFLAG_M16 in hflags cleared or set accordingly. Bit 0 of the PC is then cleared. Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Read the documentation in qemu-doc.html or on http://wiki.qemu.org - QEMU team
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