ra: TRACE_ETM for ra6m5_ek and ra8m1_ek

Generic TRCKCR setup gated on DHCSR.C_DEBUGEN (a standalone-boot TRCKCR
write wedges the chip un-attachable until power-cycle), two-step write per
the hardware manual. ra6m5_ek: div-4 (25 MHz pin) - div-2 is dead on this
board at every width/timing; J9 must be closed. ra8m1_ek: chip-max
120 MHz TRCLK / 60 MHz pin via the committed JLinkScript whose empty
OnTraceStart defers the trace clock to firmware (J-Link's from-reset
enable steps the clock mid-stream at the FSP MOCO-to-PLL switch);
ReadIntoTraceCache covers runtime ROM execution. J9 closed on both EKs -
open = SWD contention up to apparent bricks.

hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug

@@ -15,7 +15,7 @@ void OnProjectLoad (void) {
   Project.SetDevice ("R7FA6M5BH");
   Project.SetHostIF ("USB", "");
   Project.SetTargetIF ("SWD");
-  Project.SetTIFSpeed ("50 MHz");
+  Project.SetTIFSpeed ("4 MHz");   // 50 MHz SWD gave intermittent "Failed to initialize DAP"
 
   Project.SetTraceSource ("Trace Pins");
   Project.SetTracePortWidth (4);

hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug

@@ -13,7 +13,7 @@ void OnProjectLoad (void) {
   Project.SetDevice ("R7FA8M1AH");
   Project.SetHostIF ("USB", "");
   Project.SetTargetIF ("SWD");
-  Project.SetTIFSpeed ("50 MHz");
+  Project.SetTIFSpeed ("4 MHz");   // 50 MHz SWD gave intermittent "Failed to initialize DAP"
 
   Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M85F.svd");
   Project.AddSvdFile ("../../../../../../../cmsis-svd-data/data/Renesas/R7FA6M5BH.svd");
@@ -32,7 +32,7 @@ void OnProjectLoad (void) {
 void BeforeTargetConnect (void) {
   // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
 	//Project.SetJLinkScript("../../../debug.jlinkscript");
-  Project.SetJLinkScript ("$(ProjectDir)/Renesas_RA8_TracePins.pex");
+  Project.SetJLinkScript ("./ra8m1_trace.JLinkScript");
 }
 
 /*********************************************************************
@@ -83,8 +83,12 @@ void BeforeTargetConnect (void) {
 */
 void AfterTargetDownload (void) {
   _SetupTarget();
+  // RA8 executes chip-ROM code at runtime (seen at ~0x3B20); without this the
+  // trace decoder dies there ("not covered by trace cache" -> unknown packet)
+  Exec.Command("ReadIntoTraceCache 0x0 0x10000");
 }
 
+
 /*********************************************************************
 *
 *       BeforeTargetDisconnect

hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1_trace.JLinkScript

@@ -0,0 +1,20 @@
+/* RA8M1 pin trace: CSTF funnel and TMC are off the core ROM table (AP1) -
+ * declare them or trace init cannot route the M85 ETM stream (addresses per
+ * SEGGER's RA8 trace example script). Pins + TRCKCR belong to firmware
+ * (trace_etm_init): the SEGGER pex also muxed them at trace start, and its
+ * clock choice fought the firmware's mid-run = decoder desync.
+ */
+int ConfigTargetSettings(void) {
+  JLINK_ExecCommand("CORESIGHT_SetCSTFBaseAddr = 0x80013000 ForceUnlock = 1 APIndex = 1");
+  JLINK_ExecCommand("CORESIGHT_SetTMCBaseAddr = 0x80014000 ForceUnlock = 1 APIndex = 1");
+  return 0;
+}
+
+/* Replace J-Link's built-in RA8 trace start, which enables the trace clock
+ * from reset - bsp_clock_init's MOCO -> 480 MHz PLL switch would then step
+ * TRCLK mid-stream and desync the decoder. The firmware's trace_etm_init
+ * enables TRCKCR at the final clock instead.
+ */
+int OnTraceStart(void) {
+  return 0;
+}

hw/bsp/ra/family.c

@@ -99,13 +99,30 @@ void board_init(void) {
   R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME);
 
 #ifdef TRACE_ETM
+  // TRCKCR is only writable while a debugger is connected (RA HUM) - a
+  // standalone boot must skip trace init or the write wedges the chip into
+  // an un-attachable crash loop (recover: power-cycle + immediate erase)
+  if (DCB->DHCSR & DCB_DHCSR_C_DEBUGEN_Msk) {
   // TRCKCR is protected by PRCR bit0 register
   R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01);
 
-  // Enable trace clock (max 100Mhz). Since PLL/CPU is 200Mhz, clock div = 2
-  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
+  // TCLK pin = TRCLK/2; set the divider with TRCKEN=0 first (HUM procedure).
+  // Values are the empirical per-board ceilings: one step below the divider
+  // at which the stream dies mid-run.
+#if defined(BSP_MCU_GROUP_RA8M1)
+  // 480 MHz CPU: /8 -> 60 MHz TRCLK, 30 MHz pin (/4 = 60 MHz pin dies)
+  R_SYSTEM->TRCKCR = 0x02;
+  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x02;
+#else
+  // RA6M5 200 MHz CPU: /4 -> 50 MHz TRCLK, 25 MHz pin. /2 (50 MHz pin) is
+  // silent on the EK-RA6M5 in every combination - board path ceiling,
+  // reconfirmed with J9 closed and the OnTraceStart override
+  R_SYSTEM->TRCKCR = 0x02;
+  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x02;
+#endif
 
   R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY;
+  }
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS